HRP921047A2 - Watthour meter or wattmeter comprising hall sensors - Google Patents

Description

The technical field to which the invention belongs

This invention generally belongs to the field of measuring electrical variable quantities (variables). The device presented here for measuring electrical energy or strength with a Hall sensor uses a Hall element as a current converter and multiplier, so this invention, in a narrower sense, belongs to the area of measuring electrical strength using devices with a galvanomagnetic effect, which also includes devices with the Hall effect. The corresponding designation according to the international patent classification Int.XXX 4 is G01R 21/08. The proposed device can also be envisioned as a plurality of semiconductor or other "solid state" components, formed on a common substrate or in it, including components that use a galvanomagnetic effect, such as the Hall effect, so the proposed invention can according to Int. Cl. 4 to be included in group H01L 27/22.

Technical problem

The technical problem, which is solved by this application, is the high precision of the linear conversion of a voltage signal with a relatively low class level of 1 mV, into a frequency in a wide dynamic range. Moments that interfere or which when measuring low-level signals are the causes of imprecise conversion and which we therefore have to compensate for, are primarily the following: the influence of the offset voltage of the operational amplifiers, the influence of time and temperature instability of the electrical parameters of the integrator elements, the influence of parasitic currents or current due to charge injections of electronic switches, current that occurs when the switch leaks (leakage) and the deviation of the measuring sensor from the ideal linear dependence of the output voltage on the strength of the magnetic field in the sensor, and the effect of aging and the voltage and temperature dependence of the Hall element are also compensated. the problem of protection against external interference is also not negligible.

State of the art

Patent applications DE 37 02 344 A1 and DE 26 12 764 02 (Iskra) present similar solutions for converting Hall voltages into frequency using a converter that works on the principle of turning the integration capacitor to reduce the influence of zero voltages. In both solutions, the influence of charge injections introduced by electronic switches is neglected, and in addition, the turning system of the integration capacitor is less suitable for manufacturing in monolithic technology because the capacitors contain considerable parasitic capacities. The cited patent applications do not address the problem of temperature compensation, aging and voltage dependence of the Hall sensor.

The literature was used as the known state of the art:

1. High-Frequency Voltage-Controlled Continuos-Time Lowpass Filter Using Linearized CMOS Integrators, published in Electronics Letters 3rd July Vol. 22 No. 14 i

2. A Versatile Building Block: The CMOS Differential Difference Amplifier, published in IEEE Journal of Solid State Circuits, Vol. SC-22, No. 2, April 1987.

Description of the solution

The connection circuit according to this invention solves the problem of accurate measurement of electrical energy and strength by means of a Hall element, which is used as a current collector and as a multiplier of quantities proportional to the line voltage UL and the "load" current. At least two elements are used, which are placed in such a way that the influence of the magnetic field originating from the current "on the load" in both Hall elements is added, while the influence of any external interference is subtracted and thereby canceled. The Hall voltage-to-current converter includes an amplifier with variable gain, which, using a functional generator, compensates for the influence of the supply voltage VB and temperature VT on the sensitivity of the sensor, and at the same time compensates for the voltage dependence of the sensor VS.

The current-to-frequency converter uses a differential integrator with an active feedback loop to dampen the common mode in the system for canceling the influence of static offsets by switching the signal source between both inputs of the differential integrator, synchronously with switching the polarity of the input current of the measurement signal, and at the same time, it has a conversion based on the principle of integration up/down with the change of the phase of the change of the polarity of the measuring signal, which reduces the influence of the dynamic interference signal caused by the injection of charges when the switch is switched on.

The system also includes a feedback connection for compensating the influence of static offset voltages, a feedback connection for reducing the size of the voltage waves at the output of the integrator, which is a consequence of the asymmetry of the Hall sensor. There is also a solution for damping the input signal waves with a filter based on the principle of turning the capacitor.

The described measures increase the accuracy, the dynamic range of the measurement and the sensitivity of the measuring device, and at the same time, the connection circuit, with the exception of the quartz crystal, can be realized in monolithic technology on a semiconductor plate, without external elements, together with Hall sensors.

Image descriptions

Figure 1 is a block diagram of the entire measuring device

Figure 2 electrical diagram of a differential integrator solution variant and control logic in a system with an I/F (=current/frequency) converter

Figure 3 electrical diagram of a variant of the differential integrator solution and control logic in a system with a delta modulator

Figure 4 electrical schematic of a feedback loop with a group mode attenuation filter

Figure 5 electrical schematic of a feedback loop with a transconductance amplifier for common mode damping

Figure 6 Hall voltage to current converter

Figure 7 bipolar reference current source

Figure 8 double bipolar reference current source

Figure 9 housing of the measuring device for single-phase measurement

Figure 10 housing of the measuring device for three-phase measurement.

The task of the invention is to replace the known principle of compensation of zero voltages with the turning of the capacitor with the principle of switching the measuring current between the inputs of the differential integrator synchronously with the turning of the polarity of the measuring current with a periodic signal, which phase is changed by the exor gate with the purpose of achieving integration down and down, which dynamic interference signals introduced by electronic switches are compensated. The advantage of using a differential integrator instead of an integrator with capacitor rotation is, apart from a simpler practical implementation, also reflected in the fact that all switches for switching signal sources operate at a voltage close to zero potential, which ensures equal working conditions for all switches, and in addition, the switches are smaller in size , both of which ensure the minimal impact of charge injections that occur when switching the switch on the accuracy of the conversion of the measured strength into frequency.

Figure 1 shows the block diagram of the entire measuring device, which receives information about the mains voltage UL via one or two voltage-to-current converters (1, 2), through which it supplies both sensors S1 and S2 (4, 5), which are connected in cascade with by an integrator of Hall voltages (3) which enables polarity reversal by means of an exor gate (16), depending on the signals C (=C1 or C2 or C3, depending on the variant) and P (=P1 or P2 or P3 or P4, depending on the variant) which generate a time base based on a quartz oscillator (19) or time base based on the line frequency (18) or control logic 10. The amplitude of the measuring current (±IS) is affected by the amplifier with variable gain (8) whose functional generator (177) depending on the supply voltage of the connection VB, the voltage drop on the supply terminals of the sensor VS and the voltage, which is linearly proportional to the temperature VT, adjusts the gain with the purpose of compensating the effect of aging and voltage dependence of the Hall element for the precision of the measurement device. Measuring current (±IS), reference current sources (±IR1) (6) and (±IR2) (7), wave compensation current (±IV), zero voltage compensation current (IO) and switch charge injection compensation current (±IC) are fed to the input of the differential integrator (9) which converts the measured current (±IS) into a pulse sequence FOUT with control logic (10). Switching signals for periodic polarity switching to the measuring current (±IS) and switching signal P for determining the direction of integration are also determined by the control logic from the time bases (18) or (19), depending on the used variant of the conversion effect. Internally generated interference compensation signals (±IV), (IO) and (±IC) are generated based on the fact that interfering signals of different nature affect the probability of arrival of the output pulse FOUT differently. The compensation current (±IV) is generated when it is at the output of the converter, at the moment when the periodic signal C(C= or C1 or C2 or C3) is in the logical state 1, the number of pulses is different from that at the moment when it is in the state O These differences are registered by the two-way counter U/D (v 12), the content of which is transferred to the memory L at the moment of switching the signal P, and the output of the memory L is controlled by the D/A converter using the current output, the polarity of which is controlled by the signal P. The compensating current (±IC) was generated in a similar way, with the difference that the roles of signals C and P were swapped. The compensating current (IO), which equalizes the influence of the offset voltage, is exceptional according to the criterion of the frequency of occurrence of the output pulse FOUT depending on the state of signals C and P at the entrance to the exor gate (15).

Figure 2 shows blocks (9) and (10) from Figure 1 in more detail. The first variant of the measuring current converter (±IS) with frequency can be seen, which works on the principle of integration down/up with charge compensation. The measured current is integrated in a differential integrator (9) with two integrators (101, 102), whose outputs are connected to switches (127 to 130), which connect the compensation outputs (103d, 103f) of the feedback loop (103) with the inverting inputs of the integrator (101, 102). Switches (127 to 130) have the task of switching the measured current (±IS), reference currents (±IR1) and (±IR2) and compensation currents (±IK1) and (±IK2) from the feedback loop (103) between both inverting inputs integrators (101) and (102) for the purpose of canceling the offset voltage of operational amplifiers and sensors.

The polarity of the input signal changes synchronously with switching on the switch, so the measured current is integrated smoothly, while all signals, whose polarity is not changed by switching on the switch, are canceled after two switching on. The outputs of the integrator (101, 102) enter the differential amplifier (106), whose output is connected to a comparative stage without hysteresis (108) and a comparative stage with hysteresis (107), which generate the signal R with the control logic (10), which serves to activate the compensation pulse through the switches (123, 124), signal P4, which by changing the phase determines the direction of integration of the periodic signal C, signal C3 for switching the switches (127, 130) and the output frequency FOUT from the input signals C1, P1, CL or C2, P2, CL which we get from time bases (18) or (19). The input signals C1 and P1 are generated in the frequency divider (18) on the basis of the network frequency via the comparative stage (17). The frequency of the signal P1 is much lower than the frequency of C1. The time base (19) in addition to signals C2 and P2, which in the solution variant we use instead of signals C1 and P1, also generates a quantization signal CL to create the output frequency.

The switching signal P4 is generated on the basis of the switching of the comparator stage (108), which detects the passage of the voltage of the integrator (9) through zero, with the fact that with each passage of the stage (108) from the logical state 0 to the state 1 it transmits the signal P1 or P2 from the input of cell D (113) to the output, thereby synchronizing the polarity switching signal P4 with the integrator voltage crossings through potential zero. The NAND gate (109) is used to prevent the influence of disturbances in such a way that the signal passes from the stage (108) only during the time when there is a compensating pulse, and the EXOR gate (110) ensures the correct mode of operation when the polarity of the P4 signal is changed. The signal for activating the compensation pulse R determines the comparative stage with hysteresis (107) by means of the EXOR gate (111), which takes into account the change of the integration direction, and the D cell (114), which synchronizes the compensation pulse with the clock signal CL from the quartz oscillator XXXX. the pulse is quantized using the inverter (117) and the NAND gate XXX and divided by the frequency divider (122) which generates the output frequency FOUT at the output.

Depending on the nature of the reference current source, we distinguish between three sub-variants of this first variant in case of charge compensation.

The first subvariant of the first variant includes a double bipolar reference current source (±IR1, ±IR2), which ensures symmetrical initiation of both integrators, and the consequence is that the compensation currents IK and IK2 from the feedback loop (103) do not receive information about the compensation pulse. This fact can be used in a variant, because in the feedback loop there is a filter for damping the waves of the measurement signal (±IS). Changing the polarity of both reference currents with the P signal ensures the cancellation of the influence of the offset voltage of the operational amplifiers used in the reference current generators (6, 7).

The second sub-variant of the first variant for compensation includes only the reference source (±IR1), is simpler but does not allow the use of a filter for damping the waves of the measured current.

The third sub-variant of the first variant uses a simple reference current generator without the ability to change polarity. In this case, the down/up integration takes place by changing the control of the switches (127 to 130) with the signal C3 generated by the gates (115, 116, 119, 120, 121). During the duration of the compensating pulse, the C3 signal occupies the logical state 1 when the integration takes place upwards regardless of the C1 signal or C2, and logical state 0 during the duration of the compensating pulse when the integration takes place downwards. During the time when there is no compensation pulse, signal C3 is identical to signal C1 or C2. This variant enables the simplest implementation, but does not remove the influence of the offset voltage of the operational amplifier in the reference current generator.

Fig. 3 shows another variant of the voltage-to-frequency converter based on a delta modulator or pulse width modulator. In this variant, the reference current source (±IR1) is connected to the inputs of the differential integrator (9) via switches (161, 162) controlled by signals (QR, QR) from the control logic (10).

In the first variant of the second variant, the switches (161, 162) are controlled by a delta modulator, which is composed of: a comparative stage (108) which registers the polarity of the output voltage of the differential integrator (9), a D cell (15) which synchronizes the signal from the stage (108) with by the reference frequency CL and the exor gate (152) which via the RS cell (154) determines the control signals (QR) and (QR) for the switches (161, 162), depending on the state of the periodic signal P1 or P2 and the state of the Q output of the D cell (151 ). The output frequency FOUT is achieved by means of a two-way counter (156), whose output for determining the direction of counting (U/D) is connected to the output of the cell (151) via the exor gate, while the counting input is connected to the reference frequency CL. The outputs (QN-1, QN) of the counter (156) are connected via the inverter (157) and the gate (158, 159) to the RS inputs of the cell (16) which generates the output frequency. This frequency is further divided by a frequency divider (122).

The second sub-variant of the second variant differs from the first only in that instead of the comparative stage (108) a comparative stage with hysteresis (107) is used, which reduces the signal switching frequency (QR and QR) and increases the conversion accuracy. In this sub-variant, the change of polarity or the direction of integration must be synchronized with the switching of the comparative stage (107), and this is done by the D cell (150), which from the signal P1 or P2 creates the signal P3, which through the exor gate (16) changes the phase to the periodic signal C.

In both sub-variants, a bipolar reference current source can be used, the polarity of which is changed by the P signal, which removes the influence of the offset voltage of the operational amplifier, which is located in the reference source. In the case when a simple reference source is used without the possibility of changing the polarity, the logic state 1 is pushed to the input gate (152) instead of the signal P1 or P2.

The first variant of the return loop

Fig. 4 shows the diagram of the electrical connection circuit of the first variant of the feedback loop for damping the collective mode (103) from the filter for damping the size of the waves of the measured signal. The task of the feedback loop is to ensure the symmetrical flow of the output voltage of the integrators (101) and (102) regardless of their asymmetrical activation. To increase the symmetry, an active feedback loop with operational amplifier (54) is used, whose amplification is determined by resistors (55, 56). In the case when the voltages at the inputs 103a and 103b are not symmetrical in relation to the zero potential, at the point of mutual contact of the resistors (58, 59) there is a voltage UCM, which is amplified by the amplifier (54), and at the output using the resistor distributor (50, 51) that is, (52, 53) creates compensatory flows to equalize the asymmetry (IK1) and (IK2). Resistors (50, 53) have negative values of resistors (51, 52), which is achieved by a negative impedance converter. This ensures a high output impedance at the compensation outputs (103d) and (103f). Resistors 50 and 51 can have the same or different values as resistors (52, 53). In the case when resistors (50) and (51) have a factor N smaller than resistors (52, 53), the input current to the differential integrator is attenuated. In this case, smaller capacities of integration capacitors are required, which is highly desirable in monolithic technology.

The wave damping filter can be connected in parallel with the resistor (51). The filter consists of a capacitor (57), to which the connecting terminals with a contact bridge (60, 61, 62, 63) are turned using the signal from the output of the RS cell (64), depending on the signals C and P at the input of the exor gate (66).

Another variant of the return loop

The second variant of the feedback loop (103) in Fig. 5 is performed with a transconductive amplifier (67) with parallel outputs (68, 69) (103d, 103f) and two differential inputs (see literature: (2)), whose inverting inputs are connected to terminal 103c, and non-inverting inputs to terminals (103a) and (103b). The transconductive amplifier is made in the manner shown in the literature (1), with the difference that its output transistors are doubled with the purpose of creating two independent outputs, and it also has two input differential stages, as shown in the literature (2).

The Hall voltage-to-current converter (±IS) is shown in Fig. 6. The converter includes two inputs for powering the sensors (I1, I2), which can be short-circuited if both sensors are fed from only one transmission voltage-to-current converter (1). At least two Hall elements (170, 171) are connected in series using control amplifiers (174, 175) so that the Hall voltages of individual sensors are added. The sum of the voltages of both sensors is then amplified by an amplifier with a variable gain (176), and its amplification depends on the level of the output signal of the functional generator (177), which changes the gain of the stage (176) depending on the supply voltage V3, the voltage drop on the supply terminals of the sensor VS and a voltage that is proportional to the temperature VT, in order to compensate for the effects of aging, changes in supply voltage and temperature on the sensitivity of the sensor.

The functional dependence of the stage gain (176) was determined experimentally based on sensor measurements. The conversion of voltage into current takes place on the resistor (178), which is connected at one end to the output of the amplifier (176), and at the other end to the non-inverting input of the first regulatory amplifier (175). The output terminal (±IS) is connected to the virtual mass of the differential integrator (9) via a switch. The polarity of the measurement signal is changed by turning the supply terminals of the sensor (170, 171) using contact bridges (172, 173), which are controlled by the signals (QS, QS) at the output of the RS cell (179), which is controlled via the EXOR gate (16) by periodic signals C and P.

It is considered that signal C represents one of the variants of signals C1, C2, C3, depending on the used variant. The same applies to signal P, which represents one of the variant signals P1, P2, P3 or P4.

The diagram of the electrical connection circuit of the bipolar reference current generator is shown in Fig. 7. The reference voltage generator (81) is powered by current generators (80) and an analog inverter (82), which determines the symmetry of the positive and negative terminals of the reference voltage in relation to the potential of the output terminal (±IR). Conversion of the reference voltage into current (±IR) takes place on the resistor (84), which is connected to the voltage monitor (83) by the first connection, and to the non-inverting input of the analog inverter (82) by the second connection. The polarity of the reference current is determined by the signal P via analog switches (85, 86) by switching the non-inverting input of the voltage monitor (83) between both terminals of the reference generator (81).

The opposite-phase bipolar reference current source (±IR1, ±IR2) is shown in Fig. 8. Reference currents are obtained at the output of resistor distributors (93, 95) and (94, 96), respectively, which are connected at the input to voltage monitors (91) and (92) ). The inputs of these monitors are connected to the opposite poles of the reference generator (81) via a contact bridge (90). The polarity of the output currents is determined by the signal P (=P1 or P2 or P3) for controlling the contact bridge (90). Resistors (95) and (96) have negative values and are designed with a negative impedance converter, which ensures a high output resistance of the current generator. In case, when the return loop (103) on sI. 2 and 4 have asymmetrically dimensioned resistor distributors, resistors (93, 95) have values that are changed by the same factor N in relation to resistors (94, 96). The anti-phase reference current source is used in the variant with a filter for damping the measured current waves.

The described measurement system can be implemented on a semiconductor board, which is enclosed in the housing shown in Fig. 9. The semiconductor board (205) consists of two Hall sensors (203, 204) located on opposite edges, and in the middle there is a circuit for measurement which is enclosed in a ceramic or plastic case (201), which is inserted into an insulated slot (207) in the conductor (206) through which the long-distance current flows. The current conductor (206) activates the magnetic field in the ferromagnetic core (202), which is surrounded by the housing with the measuring system (201), and in the place where the Hall sensors (203, 204) are located, it forms two air slots in which the magnetic field is activated oppositely oriented. Such an arrangement enables the compensation of the influence of possible magnetic fields, which cause interference, because they are equally oriented in the slots and because the integrator of Hall voltages is connected in such a way that it adds the oppositely oriented values, while canceling those that are equally oriented.

The measurement system with two Hall elements, which are located on two opposite edges of the semiconductor wafer, in addition to the single-phase measurement of electricity, also enables two-phase and three-phase measurement by using Aron connections.

The case for two-phase or three-phase measurement is shown in Fig. 10. In this arrangement, the sensors (203) and (204) are located in air slots (212, 213) in two separate ferromagnetic rings (207, 209). They are activated by the current of different phases through conductors (208), (210). The entire system is protected from foreign magnetic fields by a ferromagnetic housing (21), which is cut in half by a rock (214), on which there is a crack (215) in which the housing (201) with a semiconductor plate (205) is located, and that is so that the bisector rocks (214) identical to the bisector between the Hall sensors (203, 204).

The case shown in Figure 10 can also be used for a single-phase system when we want an extremely protected measuring system that will be well protected from external fields, and that is so that the cores (207, 209) are activated by single-phase current.

Claims (15)

1. A device for measuring electrical energy or strength with a Hall sensor for the generation of a useful signal with variable polarity (±IS), which is linearly proportional to the current consumption in the network, and which is converted into an impulse sequence (FOUT) by a current-to-frequency converter, indicated by the fact that includes at least two Hall elements (203, 204), which are located in different air slots (212, 213) in the ferromagnetic core (202) and (207 and 209), respectively, so that the direction of the vector H of the magnetic field strength in the first slot (212 ) oppositely polarized in relation to the direction of the vector H in the second slot (213); that the converter (3, 4, 5, 8) of the Hall voltage into the current (±IS) includes an amplifier with variable amplification and an integrator of the Hall voltages of individual sensors and a circuit for reversing the polarity of the useful signal using the periodic signal C, the phase of which is determined by the periodic signal P using exor door (16). 2. Connection circuit according to claim 1, indicated by the fact that the current (IS) to frequency (FOUT) converter is made with a differential integrator (9), which consists of two integrators (101) and (102), whose outputs are feedback loops to dampen the collective mode (103) via a contact bridge with switches (127, 128, 129, 130) connected to the non-inverting inputs of the integrator (101) and (102); that the non-inverting inputs (103a, 103b) of the feedback loop (103) are connected to the integrator outputs (101, 102), while the inverting input (103c) is connected to ground; that the switches (127, 128, 129, 130) are controlled via the RS cell (163) by a periodic signal generated by the time base (18) or the time base (19) or the control logic (10); that the outputs of the integrator (101, 102) are connected to the input of the differential amplifier (106), whose output is connected to the input of the control logic (10). 3. The connection circuit according to claim 1 or 2, characterized in that the feedback loop for damping the collective mode (103) comprises an amplifier (54), whose non-inverting input is connected via resistors (58) and (59) to the inputs (103a) and ( 103b), while the inverting input is connected to the input (103c) through the resistor (56); that the output of the amplifier (54) is connected to the outputs (103d) and (103f) via resistor distributors with resistors (50, 51, 52, 53); that a filter formed by a capacitor (57) with a contact bridge (60, 61, 62, 63) and a control circuit (64, 65, 66) is connected between the output of the amplifier (54) and the output (103d). 4. The connection circuit according to claim 1 and 2, characterized in that the feedback loop for damping the collective mode (103) comprises a transconductive amplifier (67) with two parallel current outputs (68, 69) and a double differential stage at the input; that the non-inverting input of the first differential stage is connected to input 103a, and the second non-inverting input to input (103b), while both inverting inputs are connected to input (103c); that current outputs (68) and (69) are directly connected to outputs (103d) and (103f). 5. Connection circuit according to claims 1 to 4 and Fig. 2, characterized in that the current source of the input signal (±IS) is connected to the input of the differential integrator (9) at the contact point of the switches (127) and (128); that the reference current sources (±IR1) and (±IR2) are connected via switches (123) and (124) to the contact point of switches (128, 129) or (127, 130); that the signal R for controlling the compensation pulse via the switch (123, 124) is generated at the output of the D cell (114), whose D input is connected via the gate (111) to the output of the tolerance stage with hysteresis (107), while the clock input of the D cell (114) connected to the CL output of the time base (19); that the P4 polarity signal is generated at the output of the D cell (113) and the P1 or P2 signal, depending on the state of the output of the tolerance stage 108, which is connected to the clock input of the D cell via the gates (109), (110) and the inverter (112) ( 113); that the QC and QC signals for switching the contact bridge (127, 128, 129, 130), which do not overlap, are generated at the output of the RS cell (131) from the clock signals C1 and C2 respectively from the time bases (18) or (19) that is, from signal C3, generated by gates (115, 116, 119, 120, 121), depending on signals R, P and C1, respectively C2; that the output frequency FOUT is created by means of a frequency divider (122), whose input for counting is connected to the output of the cell (114) and the time base (19) through the gate (118) and the inverter (117). 6. Connection circuit according to claims 1 to 4 and Fig. 3, characterized in that the current source of the input signal (±IS) is connected to the input of the differential integrator (9) in the common point of the switch (127, 130); and the reference current source (±IR1) via the switch (161, 162) connected to the inverting inputs of the integrator (101, 102); that the QR and QR signals are generated at the outputs of the RS cell (154), whose R and S inputs are controlled by the gate (152), one input of which is connected to the output of the D cell (151) for synchronizing the signals from the tolerance stage (108) or the tolerance stage with hysteresis (107) with reference frequency CL from time base 19, and the second input to the exor gate (152) is connected to signals P1 or P2 from time bases (18, 19) or to logic state 1; that the signals QC and QC for switching the contact bridge (127, 128, 129, 130) at the output of the RS cell (163) are generated from the clock signals C1 and C2 respectively from the time bases (18) or (19); that the Q output of the synchronization cell (151) via the first input of the exor gate (153) is connected to the input for determining the counting direction (U/D) of the counter (156), while the second input of the exor gate (153) is connected to the signal P1 or P2 from of time bases (18), (19) or to the signal P3 from the output of the D cell (150), which the signal P1 or P2 on the D gate of the D cell (150) via the clock input synchronizes with the output signal of the comparative stage with hysteresis (107); that the output frequency FOUT is generated (RS) by the cell (160), whose R and S inputs are connected via the gates (158) and (159), and the inverter (157) to the QN and QN-1 outputs of the two-way counter (156), while is the clock input (RS) of the cell (160) connected to the signal CL from the time base, and the output of the cell (160) to the input of the output frequency divider (122). 7. Connection assembly according to claims 1 to 6, which includes a feedback loop for compensation of zero voltages (13), which consists of a two-way counter, a shutter (LATCH) and a D/A converter with a current output, characterized in that the input for determining the counting direction of the two-way counter (U/D) controls the exor gate (15) depending on the signals C and P from the time bases, and the counting input by the output frequency FOUT. 8. The connection circuit according to claims 1 to 6, characterized in that it includes a feedback connection for compensating the alternating component in the input signal (12), which contains a two-way counter, which has an input for determining the direction of counting controlled by the signal C, and an input for counting the output frequency FOUT, latch (L) = (LATCH) and a D/A converter with a current output, the polarity of which is determined by the P signal from the time base. 9. The connection circuit according to claims 1 to 6, characterized in that it includes a feedback loop (14) for compensation of dynamic interference signals, which includes a two-way counter (U/D), which has an input for determining the direction of counting controlled by the signal P from the time base , and the counting input with the output frequency FOUT, shutter (L) and D/A converter with current output, whose polarity is determined by signal C from the time base. 10. Connection circuit according to claims 1 to 9, characterized in that the bipolar current reference source (±IR) is derived from the reference voltage (81), which is supplied via two current sources (80) and an analog inverter (82), whose the non-inverting input connected to the first terminal of the resistor (84), and the second terminal to the output of the voltage monitor (83), to which the non-inverting input is connected to both terminals of the voltage reference (81) through the switches (85) and (86), controlled by the signal P . 11. Connection circuit according to claims 1 to 9, indicated by the fact that the opposite-phase bipolar current source (±IR1) and (±IR2) is via voltage monitors (91) and (92) and resistor distributors (93, 95) and (94, 96) designed so that the polarity is determined by the signal P from the time base (18, 19) via the contact bridge (90). 12. Connection circuit according to claims 1 to 11, characterized in that the signal current source (±IS) is derived from Hall voltages, which are generated by Hall elements (170) and (171) via control amplifiers (174) and (175) and stage amplification with variable amplification (176) with a resistor (178), the first connection of which is connected to the output of the amplifier (176), and the second to the non-inverting input of the control amplifier (175); that the amplification of the stage (176) is determined by the voltage from the functional generator (177), which is a function of the supply voltage of the connection circuit VB, the supply voltage (VS) at the supply connections of the sensor (170), (171) and the voltage VT, which is linearly proportional to temperature; that the power connections of the sensors (I1) and (I2) are connected to the sensors via contact bridges (172) and (173) and controlled by the signal QS from the RS cell (179), whose output state is determined by the exor gate 816) depending on the signals P and C from time bases (18) or (19) or control logic (10). 13. Connection assembly according to claims 1 to 12, Figure 9, characterized by the fact that the sensors (203, 204) are located on opposite edges of the semiconductor plate (205), and other parts of the connection assembly are located in between, so that across the bisector between both of the sensor, long-distance current flows through the split conductor (206), which activates oppositely polarized magnetic fields in the slots (212) and (213) of the ferromagnetic ring (202); that the current conductor (206) is connected to the non-ferromagnetic housing (201) by means of a semiconductor plate (205) and that the air slots (212) and (213) in relation to the semiconductor plate (205) are located in the places where they are on the semiconductor plate (202) ) are found by both Hall sensors (203, 204). 14. Connection assembly according to claims 1 to 13, Fig. 10, rearranged for two- or three-phase measurement of electrical energy or strength in Aron connections, indicated by the fact that the sensors (203), (204), which are located on the opposite edges of the semiconductor plate (205) on which all other connections are normally located, inserted into the air slots (212), (213) of two separate ferromagnetic rings (207), (209), which are activated by currents from different lines of the transmission line through conductors (208) and (210), and the entire arrangement is located in a closed ferromagnetic housing (211), which is bisected by a ferromagnetic wall (214) with a slot (215), into which a non-ferromagnetic housing (201) with a semiconductor plate (205) is arranged so that the bisector rock (214) identical to the bisector between both Hall sensors (203), (204). 15. Housing according to claim 14, characterized in that both ferromagnetic rings (207), (209) are activated by the same current.