HK40047089A - Sort and merge instruction for a general-purpose processor - Google Patents

Description

Ordering and merging instructions for general purpose processors

Technical Field

One or more aspects relate generally to facilitating processing within a computing environment, and more particularly to facilitating ordering and merging processes.

Background

One aspect of computer processing that employs a sort and merge process is database processing. A database is an organized collection of data, usually divided into data records. Sorting and merging collections of data records is a common database operation performed by software applications. When an application is intended to be executed on a general-purpose processor, the application is responsible for generating the many basic sequences of instructions that are used to perform the desired database operations.

To optimize performance, the application may also attempt to optimize the basic instruction sequence of each model of the processor on which the application may execute, thereby exacerbating the complexity of the application.

Disclosure of Invention

The shortcomings of the prior art are overcome and additional advantages are provided through the provision of a computer program product for facilitating processing within a computing environment. The computer program product includes a computer-readable storage medium readable by a processing circuit and storing instructions for performing a method. The method includes obtaining an instruction to perform a sort operation. The instructions are single architected machine instructions of an instruction set architecture and are executed by a general purpose processor of the computing environment. The performing includes sorting a plurality of input lists to obtain one or more sorted output lists, and providing the one or more sorted output lists as output.

By using a single architected instruction to perform the ordering (and/or merging) operations on a general purpose processor, a significant subset of the basic software instructions for performing those operations are replaced by a single architected instruction. Replacing those basic instructions with a single architected instruction reduces program complexity and does not need to include code to optimize primitive instructions. Furthermore, the overall performance is improved.

In one example, the instructions include: an opcode field including an opcode to specify a list sort (sort) operation; and a field for specifying a location for storing the one or more ordered output lists. In a further example, the instruction includes another field to specify another location that stores one or more output list descriptions.

As an example, the one field is a register field specifying a register comprising the address of the one location and the another field is another register field specifying another register comprising the address of the another location.

In one example, the instruction employs an implicit register to determine the function to be performed by the instruction. The function is selected from the group of functions consisting of: a query available function, a fixed length record ordering function, and a variable length record ordering function.

As another example, the instruction employs another implicit register to locate a block of parameters in memory used by the instruction. The parameter block includes information that the instruction uses depending on the function to be performed. In one example, the function to be performed is a fixed length record ordering function or a variable length record ordering function, and the parameter block includes information for locating a plurality of input lists and information to continue ordering based on the ordering being interrupted.

In a further embodiment, the one implicit register further comprises an operation mode indicator for specifying whether the merging of the one or more sorted output lists is to be performed.

As a specific example, the instructions include: an opcode field comprising an opcode to specify a list sort operation; a designated first register field comprising a first register comprising an address for storing the one or more sorted output lists; and a specified second register field comprising a second register comprising an address for storing one or more output list descriptions. The instruction employs a first implicit register to determine a function to be performed by the instruction and a second implicit register to locate a block of parameters in memory used by the instruction.

Computer-implemented methods and systems relating to one or more aspects are also described and claimed herein. Further, services relating to one or more aspects are also described and may be claimed herein.

Additional features and advantages are realized through the techniques described herein. Other embodiments and aspects are described in detail herein and are considered a part of the claimed aspects.

Drawings

One or more aspects that are exemplary are particularly pointed out and distinctly claimed in the claims at the conclusion of the specification. The foregoing and objects, features, and advantages of one or more aspects are apparent from the following detailed description taken in conjunction with the accompanying drawings in which:

FIG. 1A illustrates one example of a computing environment to incorporate and use one or more aspects of the present invention;

FIG. 1B shows further details of the processor of FIG. 1A in accordance with one or more aspects of the present invention;

FIG. 2 illustrates another example of a computing environment to incorporate and use one or more aspects of the present invention;

FIG. 3A illustrates one format of a List ordering (Sort Lists) instruction, in accordance with an aspect of the present invention;

FIG. 3B depicts one example of a field of an implicit register (general register 0) used by a list sort instruction, in accordance with an aspect of the present invention;

FIG. 3C illustrates one example of functional code for a list sort instruction in accordance with an aspect of the present invention;

FIG. 3D depicts one example of a field of an implicit register (general register 1) used by a list sort instruction, in accordance with an aspect of the present invention;

FIG. 3E depicts a register R specified by a list sort instruction in accordance with an aspect of the present invention₁One example of the content of (1);

FIG. 3F illustrates a register R used by a list sort instruction in accordance with an aspect of the present invention₁One example of content of + 1;

FIG. 3G illustrates a register R specified by a list sort instruction in accordance with an aspect of the present invention₂One example of the content of (1);

FIG. 3H illustrates a register R used by a list sort instruction in accordance with an aspect of the present invention₂One example of content of + 1;

FIG. 3I illustrates one example of the contents of a parameter block used by the SORTL-QAF function of the List ordering instruction, in accordance with an aspect of the present invention;

FIG. 3J illustrates one example of a fixed length record format used by the list sort instruction in accordance with an aspect of the present invention;

FIG. 3K illustrates one example of the contents of a parameter block used by the SORTL-SFLR function of the list sort instruction, in accordance with an aspect of the present invention;

4A-4B illustrate SORTL-SFLR examples in accordance with one or more aspects of the present invention;

FIG. 5A depicts one example of a summary of values of inputs to the SORTL-SFLR function, in accordance with an aspect of the present invention;

FIG. 5B illustrates one example of restrictions on modification of the incoming list address and length fields of the SORTL-SFLR function, in accordance with an aspect of the present invention;

FIG. 6A depicts one example of a first operand location/first operand before performing a merge mode indicates SORTL set to zero, in accordance with an aspect of the present invention;

FIG. 6B depicts one example of a first operand location/first operand after performing a merge mode indicating SORTL set to zero, in accordance with an aspect of the present invention;

FIG. 6C depicts one example of a second operand position/second operand before performing a merge mode indication SORTL set to zero, in accordance with an aspect of the present invention;

FIG. 6D depicts one example of a second operand location/second operand after performing a merge mode indicating SORTL set to zero, in accordance with an aspect of the present invention;

FIG. 7A depicts one example of a first operand location/first operand before a merge mode indication SORTL is set to 1 is performed, in accordance with an aspect of the present invention;

FIG. 7B depicts one example of a first operand location/first operand after a merge mode indication SORTL is set to 1 is performed, in accordance with an aspect of the present invention;

FIG. 8 illustrates one example of certain fields of a parameter block used in accordance with an aspect of the present invention;

FIG. 9 illustrates one example of a variable length record format used by the list sort instruction in accordance with an aspect of the present invention;

10A-10B illustrate one example of processing associated with a list sort instruction in accordance with an aspect of the present invention;

11A-11B illustrate one example of facilitating processing within a computing environment in accordance with an aspect of the present invention;

FIG. 12A illustrates another example of a computing environment to incorporate and use one or more aspects of the present invention;

FIG. 12B shows further details of the memory of FIG. 12A;

FIG. 13 illustrates one embodiment of a cloud computing environment; and

fig. 14 shows an example of the abstraction model layer.

Detailed Description

According to one aspect of the present invention, an ability to facilitate processing within a computing environment is provided. As one example, a single instruction (e.g., a single architected hardware machine instruction at a hardware/software interface) is provided to perform operations, such as ordering and/or consolidating data records. The instructions are executed, for example, on a general purpose processor. By using a single instruction to order and/or merge data records, e.g., of a database, execution time within a processor (such as a general purpose processor) is reduced, and the amount of memory utilized in the ordering and/or merging is reduced.

One embodiment of a computing environment to incorporate and use one or more aspects of the present invention is described with reference to FIG. 1A. Computing environment 100 includes, for instance, a processor 102 (e.g., a central processing unit), a memory 104 (e.g., a main memory; also known as a system memory, a main storage, a central storage, a storage), and one or more input/output (I/O) devices and/or interfaces 106 coupled to one another via, for instance, one or more buses 108 and/or other connections.

In one example, the processor 102 is based on that provided by International Business machines corporation, Armonk, N.Y.Hardware architecture, and is such as IBMA server, such as a server, also offered by international business machines corporation and implementing the z/Architecture hardware Architecture. One embodiment of the z/Architecture hardware Architecture is described in a publication entitled "z/Architecture Principles of Operation" (IBM publication SA22-7832-11, 12 th edition, 9.2017), which is hereby incorporated by reference in its entirety. However, the z/Architecture hardware Architecture is onlyIs an example architecture; other architectures and/or other types of computing environments can include and/or use one or more aspects of the present invention. In one example, the processor executes an operating system, such as that also provided by International Business machines corporationOperating system

The processor 102 includes a number of functional components for executing instructions. As depicted in fig. 1B, these functional components include: for example, an instruction fetch component 120 for fetching instructions to be executed; an instruction decode unit 122 to decode the fetched instruction and obtain operands of the decoded instruction; an instruction execution component 124 for executing the decoded instructions; a memory access component 126 for accessing memory for instruction execution if necessary; and a write back component 130 to provide results of executed instructions. In accordance with one or more aspects of the present invention, one or more of these components may include or have access to at least a portion of one or more other components that provide sequencing/merging processing (or other processing that may use one or more aspects of the present invention). The one or more other components include, for example, a ranking/merging component (or other component) 136. The functionality provided by the components 136 is described in further detail below.

Another example of a computing environment to incorporate and use one or more aspects of the present invention is described with reference to FIG. 2. In one example, the computing environment is based on a z/Architecture hardware Architecture; however, the computing environment may be based on other architectures offered by International Business machines corporation or other companies.

Referring to FIG. 2, in one example, a computing environment includes a Central Electronics Complex (CEC) 200. CEC 200 includes a plurality of components, such as memory 202 (a.k.a. system memory, main memory, primary storage, central storage, storage) coupled to one or more processors (a.k.a. Central Processing Unit (CPU))204 and an input/output subsystem 206.

Memory 202 includes, for example, one or more logical partitions 208, a hypervisor (hypervisor)210 that manages the logical partitions, and processor firmware 212. One example of hypervisor 210 is the Processor Resource/System Manager (PR/SMTM) hypervisor offered by International Business machines corporation, Armonk, N.Y.. As used herein, firmware includes, for example, microcode of a processor. Including, for example, hardware-level instructions and/or data structures used in the implementation of higher-level machine code. In one embodiment, it includes proprietary code, such as that typically delivered as microcode, including trusted software or microcode specific to the underlying hardware, and controls operating system access to the system hardware.

Each logical partition 208 can act as a separate system. That is, each logical partition may be independently reset, run a guest operating system 220, such as the z/OS operating system or another operating system, and operate with different programs 222. The operating system or application running in the logical partition appears to have access to the complete system, but in practice only a portion of it is available.

The memory 202 is coupled to processors (e.g., CPUs)204, which are physical processor resources that may be allocated to logical partitions. For example, the logical partition 208 includes one or more logical processors, each of which represents all or a share of the physical processor resources 204 that may be dynamically allocated to the logical partition.

Further, the memory 202 is coupled to an I/O subsystem 206. The I/O subsystem 206 may be part of or separate from the central electronic complex. It directs the flow of information between main memory 202 and input/output control unit 230 and input/output (I/O) devices 240 coupled to the central electronic complex.

Many types of I/O devices may be used. One particular type is a data storage device 250. The data storage device 250 may store one or more programs 252, one or more computer-readable program instructions 254, and/or data, among others. The computer-readable program instructions may be configured to perform the functions of embodiments of aspects of the present invention.

In one example, the processor 204 includes a sorting/merging component (or other component) 260 to perform one or more sorting and/or merging (or other operations that may use one or more aspects of the present invention). In different examples, there may be one or more components that perform these tasks. Many variations are possible.

The central electronic complex 200 may include and/or be coupled to removable/non-removable, volatile/nonvolatile computer system storage media. For example, it may include and/or be coupled to non-removable, nonvolatile magnetic media (commonly referred to as a "hard disk drive"), a magnetic disk drive for reading from and writing to a removable, nonvolatile magnetic disk (e.g., a "floppy disk"), and/or an optical disk drive for reading from or writing to a removable, nonvolatile optical disk (e.g., a CD-ROM, DVD-ROM, or other optical media). It should be understood that other hardware and/or software components may be used in conjunction with central electronic complex 200. Examples include, but are not limited to: microcode, device drivers, redundant processing units, external disk drive arrays, RAID systems, tape drives, data archival storage systems, and the like.

Further, central electronic complex 200 may operate with numerous other general purpose or special purpose computing system environments or configurations. Examples of well known computing systems, environments, and/or configurations that may be suitable for use with central electronic complex 200 include, but are not limited to: personal Computer (PC) systems, server computer systems, thin clients, thick clients, hand-held or laptop devices, multiprocessor systems, microprocessor-based systems, set top boxes, programmable consumer electronics, network PCs, minicomputer systems, mainframe computer systems, and distributed cloud computing environments that include any of the above systems or devices, and the like.

Although various examples of computing environments are described herein, one or more aspects of the present invention may be used with many types of environments. The computing environments provided herein are merely examples.

According to one aspect of the present invention, a processor (e.g., processor 102 or 204) employs an enhanced sorting facility that provides a mechanism for sorting a plurality of unsorted input data lists into one or more sorted output data lists. In one example, the enhanced sequencing facility is installed in the system when the facility indicator is set to, for example, 1. As one specific example of a z/Architecture hardware Architecture, when an enhanced sequencing facility is installed in z/Architecture mode, the facility bit 150 is set to, for example, 1. In one embodiment, the facility also provides a mechanism for merging multiple sorted input data lists into a single sorted output data list. The facility includes, for example, list ordering instructions, embodiments of which are described below.

One embodiment of details related to the list sort instruction is described with reference to FIGS. 3A-3K. In one example, the instructions are executed on a general purpose processor (e.g., processor 102 or 204). In the description herein, specific locations, specific fields, and/or specific sizes of fields (e.g., specific bytes and/or bits) are indicated. However, other locations, fields, and/or sizes may be provided. Further, although it is specified that a certain bit (bit) is set to a specific value (for example, 1 or 0), this is merely an example. In other examples, the bit may be set to a different value, such as an opposite value or another value. Many variations are possible.

Referring to fig. 3A, in one example, the format of a list Sort (SORTL) instruction 300 is an RRE format that represents registers and register operations with extended opcodes. By way of example, the instruction includes an opcode field 302 (e.g., bits 0-15) having an opcode indicating an sort and/or merge operation, a first register field (R) specifying a first pair of general purpose registers₁)304 (e.g., bits 24-27) and a second register field (R) specifying a second pair of general purpose registers₂)306 (e.g., bits 28-31). From R₁The contents of the register specified by field 304 specify the location of the first operand (in storage), and is specified by R₂The contents of the register specified by field 306 specify the location of the second operand (in storage). R₁The content of +1 specifies the length of the first operand, R₂The content of +1 specifies the length of the second operand. In one example, bits 16-23 of the instruction are reserved bits and should contain zeros; otherwiseThe program may not operate compatibly in the future. As used herein, a program is a program that issues a list sort instruction. It may be a user program, an operating system, or another type of program.

In one embodiment, execution of an instruction includes the use of one or more implicit general purpose registers (i.e., registers not explicitly specified by the instruction). For example, general registers 0 and 1 are used to execute a list sort instruction, as described herein. In one example, general register 0 is used to specify whether a merge is to be performed and to specify the ordering function to be performed by the instruction, and general register 1 is used to provide the location of the parameter block used by the instruction. In another example, general register 0 is not used to specify whether a merge is to be performed; instead, the merge is set/unset by the machine (e.g., processor) and may not be changed by the mode indicator. Other variations are possible.

By way of example, referring to FIG. 3B, general register 0(308) includes a merge mode field 310 (described below) and a function code field 312. In one particular example, bit positions 57-63 of general register 0 contain a function code; in other embodiments, however, other bits may be used to contain the function code. In one example, a specified exception is identified when bits 57-63 of general register 0 specify unassigned or uninstalled function code.

Example assigned function codes for the list sort instruction are shown in FIG. 3C, including, for example: function code 0(313) indicating a SORTL-QAF (query available function) function; function code 1(315) indicating a SORTL-SFLR (fixed length record ordering) function; and a function code 2(317) indicating a SORTL-SVLR (variable length record sorting) function. Each code uses a parameter block, and in one example, the size of the parameter block depends on the function. For example, for the SORTL-QAF function, the parameter block is 32 bytes; for SORTL-SFLR and SORTL-SVLR, the parameter block is 576+16xN_ISIn which N is_ISIs the number of input lists specified by the interface size. In this example, no other functional code is assigned. Although example functions and functional code are described, other functions and/or functional code may be used.

As indicated previously, general register 0 also includes a merge mode field 310. In one example, bit 56 of general register 0 specifies the mode of operation (merge mode) that applies to, for example, SORTL-SFLR and SORLT-SVLR functions. In one example, when the specified function is SORTL-QAF, bit 56 of general register 0 is ignored. Further, in one example, bit positions 0-55 of general register 0 are ignored.

Further details regarding another implicit register (general register 1) used by the list sort instruction are described with reference to FIG. 3D. The contents of general register 1(314) specify, for example, the logical address 316 of the leftmost byte of the parameter block in the storage device. In one example, the parameter block is specified on a doubleword boundary; otherwise, a specified exception is identified. Further details regarding the parameter block are described further below.

For a given function (e.g., SORTL-QAF, SORTL-SFLR, SORTL-SVLR), the contents of general registers 0 and 1 are not modified. Further, in one example, R₁The field 304 specifies the even-odd pair (even-odd pair) of general purpose registers. Even registers are to be designated, general register 0 is not to be designated; otherwise, a specified exception is identified. When the specified function is SORTL-SFLR or SORTL-SVLR, as shown in FIGS. 3E-3F, the general register R₁318 specifies a logical address 320, e.g., the leftmost byte of the first operand, and a general register R₁The contents of +1(322) specify the length 324, e.g., number of bytes, of the first operand. When the specified function is SORTL-SFLR or SORTL-SVLR, for example, the first operand is to be specified on a doubleword boundary; otherwise, a specified exception is identified. Selecting data from a set of input lists in the form of records and storing the data at a first operand location (e.g., in R₁Starting at the specified address). When the SORTL-QAF function is specified, the general register R is ignored₁And R₁Content of + 1.

Further, for a given function (e.g., SORTL-QAF, SORTL-SFLR, SORTL-SVLR), in one example, R₂The field 306 specifies the even-odd pair of general purpose registers. To specify even registers, not toSetting a general register 0; otherwise, a specified exception is identified. When the designated function is SORTL-SFLR or SORTL-SVLR and the Merge Mode (MM) is zero, as shown in FIGS. 3G-3H, the general register R₂326 specifies a logical address 328, e.g., the leftmost byte of the second operand, a general register R₂The contents of +1(330) specify the length 332 of the second operand, e.g., the number of bytes. In one example, when the specified function is SORTL-SFLR or SORTL-SVLR and the Merge Mode (MM) is zero, a second operand is to be specified on a doubleword boundary; otherwise, a specified exception is identified. When MM is zero, the starting address and length of each output list, referred to as the Output List Description (OLD), are stored at a second operand location (e.g., in R₂Starting at the specified address). When the SORTL-QAF function or MM is designated as 1, the general register R is ignored₂And R₂Content of + 1.

In execution, in one embodiment, the function specified by the function code in general register 0 is executed. In one embodiment, as part of the operations when the specified function is SORTL-SFLR or SORTL-SVLR, the following operations occur:

general register R₁Increment the address in (1) by the number of bytes stored at the first operand location, and the general register R₁The length in +1 is decremented by the same number.

When MM is 0, general register R is set₂Increment the address in (1) by the number of bytes stored at the second operand location, and the general register R₂The length in +1 is decremented by the same number.

In one example, the formation and updating of addresses and lengths depends on the addressing mode.

In the 24-bit addressing mode, in one embodiment, the following applies:

bit positions 40-63, R of general register 1₁And R₂Constitutes the address of the parameter block, the first operand and the second operand, respectively, and ignores the contents of bit positions 0-39.

Bits 40-63 of the updated first operand and second operand addresses replace general register R, respectively₁And R₂Corresponding bit in (a). Ignore the carry of bit position 40 of the updated address and register R₁And R₂The contents of bit positions 32-39 are set to 0. General register R₁And R₂The contents of bit positions 0 to 31 remain unchanged.

General register R₁+1 and R₂The contents of bit positions 32-63 of +1 form a 32-bit unsigned binary integer that specifies the number of bytes in the first and second operands, respectively. Ignoring general purpose register R₁+1 and R₂The contents of bit positions 0 to 31 of + 1.

Bits 32-63 of the updated first operand and second operand lengths, respectively, replace general register R₁+1 and R₂The corresponding bit in + 1. General register R₁+1 and R₂The contents of bit positions 0 to 31 of +1 remain unchanged.

In the 31-bit addressing mode, in one embodiment, the following applies:

bit positions 33-63, R of general register 1₁And R₂Constitutes the address of the parameter block, the first operand and the second operand, respectively, and ignores the contents of bit positions 0-32.

Bits 33-63 of the updated first operand and second operand addresses replace general register R, respectively₁And R₂The corresponding bit in (a). The carry of bit position 33 of the updated address is ignored and the contents of bit position 32 of general registers R1 and R2 are set to 0. The contents of bit positions 0-31 of general registers R1 and R2 remain unchanged.

The contents of bit positions 32-63 of general registers R1+1 and R2+1 form a 32-bit unsigned binary integer that specifies the number of bytes in the first and second operands, respectively. Ignoring general purpose register R₁+1 and R₂The contents of bit positions 0-31 of + 1.

Bits 32-63 of the updated first operand and second operand lengths, respectively, replace general register R₁+1 and R₂The corresponding bit in + 1. General register R₁+1 and R₂The contents of bit positions 0-31 of +1 remain unchanged。

In the 64-bit addressing mode, in one embodiment, the following applies:

the contents of bit positions 0-63, R1, and R2 of general register 1 constitute the addresses of the parameter block, the first operand, and the second operand, respectively.

Bits 0-63 of the updated first and second operand addresses replace corresponding bits in general registers R1 and R2, respectively. The carry bit position 0 of the updated address is ignored.

General register R₁+1 and R₂The contents of bit positions 0-63 of +1 form a 64-bit unsigned binary integer that specifies the number of bytes in the first operand and the second operand, respectively.

Bits 0-63 of the updated first operand and second operand lengths, respectively, replace general register R₁+1 and R₂The corresponding bit in + 1.

In the access register mode, registers 1, R are accessed₁And R₂Address spaces containing a parameter block, a first operand, and a second operand are specified, respectively.

Further details regarding the different functions are described below:

function code 0: SORTL-QAF (Query Available Functions)

The SORTL-QAF (query) function provides a mechanism to indicate the availability of all installed functions, the installed parameter block format, and the available interface size. The interface size is the number of input lists available to the program. The size of the parameter blocks of the SORT-SFLR and SORT-SVLR functions is proportional to the interface size specified by the program.

One example format of the parameter block for the SORTL-QAF function is described with reference to FIG. 3I. In one example, the parameter block 340 for the SORTL-QAF function (e.g., function code 0) contains an installed function vector 342, an installed interface size vector 344, and an installed parameter block format vector 346. In one particular example, these vectors are stored to bytes 0 through 15, byte 16, and bytes 24 through 25, respectively, of the parameter block. Each of these vectors is described further below.

As an example, bits 0-127 of installed function vector 342 correspond to function codes 0-127, respectively, of the list sort instruction. If a bit is, for example, 1, the corresponding function is installed; otherwise, the function is not installed.

Further, in one example, bits 0-7 of installed interface size vector 344 indicate the interface size available to the program. The interface size is the number of input lists specified by the program for the SORT-SFLR and SORTL-SVLR functions. In one example, bits 0-7 of installed interface size vector 344 correspond to the following interface sizes: bits 0, 1, 5-7 are reserved; bits 2-32 input lists; bits 3-64 input lists; and bits 4-128 input lists. Other examples are possible.

When a bit of the installed interface size vector 344 is, for example, 1, the corresponding interface size is available to the program. One or more bits may be stored as a 1. For example, the binary value 00101000 indicates that interface sizes of 32 and 128 input lists are available. In one example, bits 0-1 and 5-7 are reserved bits and are stored as 0. Further, in one example, an interface size of 32 input lists is available when the enhanced ranking facility is installed. Thus, bit 2 is stored as a 1. Other examples are possible.

In addition to the above, in one example, bits 0-15 of the installed parameter block format vector 346 correspond to parameter block formats 0 through 15, respectively. When a bit is 1, the corresponding parameter block format is installed, otherwise, the parameter block format is not installed. In one example, 0's are stored to reserved bytes 17-23 and 26-31 of the parameter block.

SORT-QAF function ignores general register R₁、R₂、R₁+1 and R₂Content of + 1.

When applicable, change events are stored for parameter block identification PER (program event recording). When applicable, a PER zero address detection event is identified for the parameter block.

The condition code 0 is set when the execution of the SORTL-QAF function is completed; in one example, condition codes 1, 2, and 3 are not applicable to the query function.

Function code 1: SORTL-SFLR (Fixed Length record sorting) (Sort Fixed-Length Records)

In one example, the input list set is ordered and stored as the output list set at the first operand location. Each list is a set of records, and referring to fig. 3J, each record 350 includes a key 352 (e.g., a fixed length key) and a payload 354 (e.g., a fixed length payload).

Records from the input list are sorted based on the value of the key. As described below, the records may be sorted in ascending or descending order, as specified in the Sort Order (SO) field of the parameter block associated with function code 1. The records of the input list may be listed in sorted order or not.

The records of the output list may be derived from multiple input lists and stored in sorted order. The number of output lists stored at the first operand location depends on the input data. In one example, only one output list is generated when each active input list contains records listed in the same order as specified in the SO field.

As indicated above, bit 56 of general register 0 specifies the mode of operation (referred to as the Merge Mode (MM)) suitable for the SORTL-SFLR function. When the merge mode is, for example, 0, for each output list stored at a first operand location, a corresponding Output List Description (OLD) is stored at a second operand location. Each OLD includes, for example, an 8-byte OLD-address specifying the location of the first record in the corresponding output list and an 8-byte OLD-length specifying the length, for example in bytes, of the corresponding output list. When the merge mode is 1, the input list is considered pre-ordered. That is, each active input list is considered to contain the same records in the order specified by the SO field of the parameter block.

When MM is 1 and each input list is pre-ordered, the result stored at the first operand location is a single output record list in the ordered order. When the MM is 1 and each input list is not pre-ordered, the result is unpredictable.

When MM is, for example, 1, general register R is ignored₂And R₂+1, and no information is stored at the second operand location. When the MM is 1, the procedure for distinguishing the separation between the output lists may not be performed, thereby potentially improving the performance of the operation. When the MM is 1, data is not stored to a recording record recall buffer (recording record recall buffer) described below.

In one example, to generate a single record list in sorted order from a collection of records in a random order, a program may perform the following process:

1. the set of records is divided evenly among the set of initial lists, with each list containing a random order of records. The list sort instruction is executed with the initial set of lists as input lists and the merge mode equal to 0 to produce an intermediate set of lists (where each list contains records in sort order), and a storage location and length of each list in the intermediate set of lists.

2. The list sort instruction is executed with the intermediate list set as the input list and the merge mode equal to 1 to produce a final and single list containing records in sort order.

An example of SORTL-SFLR with merge mode equal to 0 is illustrated in FIG. 4A. Including input and result output in this example. As shown, there are three input lists 400: input list0, input list1, and input list 2. Further, examples of the resulting first operand 402 and second operand 404 are shown. In one example, there are three lists in the first operand 402 (FIG. 4A), and one starts at address 1000 and has a length of 18, as shown in the second operand 404; the other starts at address 1018 and has a length of 28; and the third starts at address 1040 and has a length of 20.

In one example, an operation with a larger number of input lists results in a smaller number of output lists when two operations perform the same SORTL-SFLR function on the same set of unsorted input records with merge mode equal to 0 and the only difference between the two operations is the number of input lists used to specify the input data. Fig. 4B shows an example of using six input lists 450 to operate on the same input data as the example in fig. 4A using three input lists. Also shown is a result first operand 452 having two output lists instead of three and a second operand 454 providing a description of the two output lists.

As indicated, the SORTL-SFLR function uses a parameter block, an example of which is described with reference to FIG. 3K. In the example parameter blocks described herein, specific locations (e.g., specific bytes and/or bits) within the parameter block for specific fields and specific sizes of fields are indicated. However, other locations and/or sizes may be provided for one or more fields. Further, although it is specified that the bit is set to a specific value (for example, 1 or 0), this is merely an example. In other examples, the bits may be set to different values, such as an opposite value or another value. Many variations are possible.

In one example, the parameter block 360 of the SORTL-SFLR function contains the following:

parameter Block Version Number (PBVN/Parameter Block Version Number) 362: bytes 0-1 of the parameter block specify the version and size of the parameter block. Bits 0-7 of the PBVN have the same format and definition as bits 0-7 of the interface size list vector (byte 16) for installation of the parameter block for the SORTL-QAF (query) function. Bits 0-7 specify the number N of input lists described in the parameter block_IS. By evaluating the formula (576+16 xN)_IS) To determine the size (in bytes) of the parameter block. One of bits 0-7 is to have a value of 1; otherwise, a general operand data exception is identified. Bits 8-11 of PBVN are reserved bits and should contain a 0; otherwise, the program may not operate compatibly in the future. Bits 12-15 of the PBVN contain unsigned binary integers that specify the format of the parameter block. The SORTL-QAF function provides a mechanism to indicate the available parameter block formats. When the size or format of the specified parameter block is not supported by the model, a general operand data exception is identified. The PBVN is specified by the program and is not modified during execution of the instructions.

Model Version Number (MVN/Model Version Number) 364: byte 2 of the parameter block is an unsigned binary integer that identifies the model of the executing instruction. MVN are updated during execution of instructions by, for example, a processor. MVN are model dependent.

When a continuation flag (CF/continuation flag)368 described below is 1, MVN is an input to the operation. When CF is 1 and MVN identifies the same model as the currently executing instruction, data from the continue state buffer (CSB/continuation state buffer)390 described below may be used to resume operation. When CF is 1 and MVN identifies a model that is different from the model of the currently executing instruction, some or all of the CSB field may be ignored.

In one example, the program initializes MVN to zero. It is desirable that in the case of re-execution of the instruction for the purpose of a recovery operation, the program does not modify MVN; otherwise, the result is unpredictable.

Sort Order (SO/Sort Order) 366: the parameter block has a bit 56 of 0, which designates an ascending sort order, and a bit 56 of 1, which designates a descending sort order. When an ascending order is specified, each record of the output list contains keys greater than or equal to the keys of adjacent records in the same output list (e.g., to the left). When a descending order is specified, each record of the output list contains keys less than or equal to the keys of adjacent records in the same output list (e.g., to the left). The SO is not updated during execution of the instruction.

Continuation Flag (CF) 368: bit 63 of the parameter block, when 1, indicates that the operation is partially complete and continues the contents of the status buffer 390, and when the Merge Mode (MM) is 0, the operation can be resumed with the contents of the resume record recall buffer. The program initializes a Continuation Flag (CF) to zero and does not modify the CF if the instruction is re-executed for the purpose of resuming operation; otherwise, the result is unpredictable. In one example, the processor modifies the CF in the event that the instruction is to be re-executed.

Record key length 370: bytes 10-11 of the parameter block contain unsigned binary integers that specify the size in bytes of the key in the record processed during operation. In one example, a general operand data exception is identified for any of the following conditions:

a key size of zero bytes is specified.

Key sizes that are not multiples of 8 are specified.

A key size greater than 4096 bytes is specified.

The record key length is not updated during execution of the instruction.

Record payload length 372: when specifying the SORTL-SFLR function, bytes 14-15 of the parameter block contain unsigned binary integers that specify the size in bytes of the payload in the record processed during operation. In one example, a general operand data exception is identified for any of the following conditions:

a payload size that is not a multiple of 8 is specified.

The sum of the specified key and the payload size is greater than 4096 bytes.

A payload size of zero is valid.

The record payload length field of the parameter block is ignored when the SORTL-SVLR function is specified. The record payload length is not updated during execution of the instruction.

Operand Access Intent (OAI/Operand Access Intent) 374: bits 0-1 of byte 32 of the parameter block signal the CPU of future access intents to the input list and the first operand. The provided access intents may be used to modify cache line installation and replacement policies for corresponding storage locations at different levels of cache in the storage hierarchy.

When bit 0 of the OAI field is a 1, the storage location designated to contain data for any active input list will be referenced as one or more operands of a subsequent instruction. When bit 0 of the OAI field is 0, the storage locations designated to contain data for any active input list will not be referenced as one or more operands of a subsequent instruction.

When bit 1 of the OAI field is 1, the storage location designated as containing the first operand will be referenced as one or more operands of a subsequent instruction. When bit 1 of the OAI field is 0, the storage location designated as containing the first operand will not be referenced as one or more operands of a subsequent instruction.

The CPU cannot be guaranteed to use this information. The duration for which this information can be used is undefined but limited.

When the Next sequential Instruction following the Next Instruction Access Intent (NIAI/Next Instruction Access Intent) is list Sort (SORTL), execution of SORTL is not affected by NIAI.

The OAI is not updated during execution of the instruction.

Active Input list Count Code (AILCC/Active Input Lists Count Code) 376: bits 1-7 of byte 33 of the parameter block are 7-bit unsigned integers that specify the number of input lists indicating the boundary between the active input list and the inactive input list. An input list with a list number, for example, less than or equal to the value of the AILCC field, is active. An input list with a list number, for example, greater than the value of the AILCC field, is in an inactive state. The number of input lists in the active state is 1 more than the value in the AILCC field.

The input list in the active state participates in the operation. The input list in the inactive state does not participate in the operation.

Bit 0 of byte 33 of the parameter block is a reserved bit and should contain zero; otherwise, the program may not operate compatibly in the future.

In one example, a general operand data exception is identified when the value of the AILCC field plus one is greater than the number of input lists described in the parameter block (as specified by bits 0 through 7 of the PBVN field).

The value specified in the aiccc field does not affect the size of the parameter block. The access exception applies to a reference to a field of the parameter block that specifies an input list address or length of the input list corresponding to the inactive state.

The AILCC is not updated during execution of the instruction.

Empty Input list Control (EILCL/Empty Input Lists Control) 378: when bit 0 of byte 40 of the parameter block is 1, the operation ends when the length of input list0 becomes zero during the operation. When bit 0 of byte 40 of the parameter block is zero, the operation continues when the length of input list0 becomes zero during the operation. When bit 1 of byte 40 of the parameter block is 1, the operation ends when the length of the active input list other than input list0 becomes zero during the operation. When bit 1 of byte 40 of the parameter block is zero, the operation continues when the length of the active input list other than input list0 becomes zero during the operation.

When the length of the active input list is initially zero before the instruction is executed, the corresponding bit of the EILCL does not apply.

The EILCL is not updated during execution of the instruction.

It is desirable that in the case of re-execution of an instruction for the purpose of a recovery operation, the program does not modify the EILCL; otherwise, the result is unpredictable.

Empty Input List Flag (EILF/Empty Input List Flag) 380: when the EILCL is binary 11 and the operation ends because the updated length of the active input list is equal to zero, and the condition code 2 is set, then a value of 1 is stored, for example by the processor, to bit 2 of byte 40 of the parameter block; otherwise, the value 0 is stored to bit 2 of byte 40 of the parameter block. When the EILF contains a value of 1, the entry list number of the entry list that became empty during operation is placed in the EILN field of the parameter block. In one example, the program initializes the EILF to zero.

The EILF may be referenced at the beginning of execution of the instruction when the operation is being resumed. It is expected that in the case of re-execution of the instruction for the purpose of a recovery operation, the program does not modify the EILF; otherwise, the result is unpredictable.

Empty Input List Number (EILN/Empty Input List Number) 382: when the condition is such that the value 1 is stored in the EILF field, the entry list number of the entry list that becomes empty during operation is stored, for example, by the processor in byte 41 of the parameter block; otherwise, the value 0 is stored in byte 41 of the parameter block.

The EILN is ignored at the beginning of the operation. In one example, the program initializes the EILN to zero.

Incomplete Input List Flag (IILF/Incomplate Input List Flag) 384: when the operation ends due to an attempt to process an incomplete input list, e.g., a value of 1 is stored by the processor to bit 0 of byte 46 of the parameter block; otherwise, a zero value is stored to bit 0 of byte 46 of the parameter block. An active input list is considered incomplete when the corresponding input list length is greater than zero and less than the number of bytes of the record specified by the input list address. This condition may exist at the beginning of the operation, or may be encountered during the operation. When IILF contains a value of 1, the entry list number of the encountered incomplete entry list is placed in the IILN field of the parameter block. In one example, the program initializes IILF to zero.

When the operation ends with the set condition code 2 and the result value in the IILF field is zero, the operation ends due to a null input list. When the operation ends with the setting condition code 2 and the result value in the IILF field is 1, the operation ends because the input list is incomplete.

When an operation is being resumed, the IILF may be referenced at the beginning of execution of the instruction. It is expected that in the case of re-execution of the instruction for the purpose of a resume operation, the program does not modify IILF; otherwise, the result is unpredictable.

Incomplete Input List Number (IILN/Incomplex Input List Number) 386: when the condition causes the value 1 to be stored in the IILF field, the entry list number of the encountered incomplete entry list is stored, for example by the processor, in byte 47 of the parameter block; otherwise, a zero value is stored in byte 47 of the parameter block. When multiple input lists are incomplete, which incomplete input list number to store in the IILN field depends on the model. In one example, the program initializes the IILN to zero.

The IILN is ignored at the beginning of the operation.

Recording resume Buffer Origin (Continuation Record Buffer Origin) 388: a 4 kbyte buffer in storage (called the continue record recall buffer) is provided by the program for the CPU to store and reference data between two executions of the same list sort instruction (in case the operation ends and can be resumed later). The 52 bits of the parameter block, starting from bit 0 of byte 56 to bit 3 of byte 62, contain unsigned binary integers used in forming the resume record recall address, which are aligned on a 4 kbyte boundary. The resume recording recall address is, for example, a logical address of the leftmost byte of the resume recording recall buffer.

In the 24-bit addressing mode, bits 40 to 51 with the start of the continue recording recall buffer appended to the right 12 zeros form the continue recording recall address. In the 31-bit addressing mode, bits 33-51 with the start of the continue recording recall buffer appended to the right 12 zeros form the continue recording recall address. In the 64-bit addressing mode, bits 0 to 51 having the start of the continuous recording recall buffer appended to the right 12 zeros form the continuous recording recall address.

In the access register mode, the access register 1 designates an address space in the storage device containing a resume record recall buffer.

When the Merge Mode (MM) is zero, the operation ends after storing one or more entries, and normal completion does not occur, the key stored to the last entry of the first operand is also stored to the continue entry recall buffer. When MM is 1, the resume recording recall buffer start point is ignored.

The resume record recall buffer start is not modified during execution of the instruction.

In the event that the instruction is re-executed for the purpose of a recovery operation, the program does not modify the resume record recall buffer starting point; otherwise, the result is unpredictable.

Continue status Buffer (CSB/Continuation State Buffer) 390: when the condition is such that the value 1 is stored in the CF field, the internal state data is stored, for example by the processor, to bytes 64-575 of the parameter block; otherwise, bytes 64-575 of the parameter block are undefined and modifiable. The stored internal state data is model dependent and can subsequently be used to resume operations when instructions are re-executed. In one example, the program initializes the resume state buffer to zero. In the event that the instruction is re-executed for the purpose of a resume operation, the program is expected not to modify the resume state buffer; otherwise, the result is unpredictable.

As an example, the internal state data includes information related to the input list, such as information regarding a previous comparison of records of the input list to determine a next comparison to be made. The internal state data is model dependent in that it may be stored or committed differently depending on the processor model. Other variations are possible.

In one embodiment, the instructions may be partially completed by one model in the configuration, and execution may resume on a different model in the configuration. While different models may maintain different internal states in one embodiment, in one example, each model is to be able to interpret those of the CSB (if any) for recovery operations. When the operation resumes, MVN indicates which, if any, of the CSBs the machine is able to interpret.

Input list N Address (Input list N Address)392, 394, 396: the parameter block defines a plurality of input lists. Number N of input lists defined in parameter block_ISSpecified by bits 0-7 of PBVN 362. Input list from zero to (N)_IS-1) numbering. For each input list, the parameter block specifies an input list address of, for example, 8 bytes. For the nth input list, the contents of bytes 576+16xN through 583+16xN of the parameter block specify, for example, the logical address of the leftmost byte of the nth input list in the storage device.

Each entry list address corresponding to an entry list in the active state, specified by the aiccc field, is an input to the operation and is updated by the operation. Each entry list address corresponding to an entry list in the inactive state, as specified by the aiccc field, is ignored by the operation.

In one embodiment, when the input list address is an input to an operation, the following applies:

in the 24-bit addressing mode, bits 40-63 of the input list address specify the location of the leftmost byte of the input list in the storage device, and the contents of bits 0-39 of the input list address are treated as 0.

In the 31-bit addressing mode, bits 33-63 of the input list address specify the location of the leftmost byte of the input list in the storage device, and the contents of bits 0-32 of the input list address are treated as 0.

In the 64-bit addressing mode, bits 0-63 of the input list address specify the location in the storage device of the leftmost byte of the input list.

In the access register mode, access register 1 specifies the address space in the memory device containing the list of active inputs.

For an input list in an active state, designating a corresponding input list address on a double-word boundary; otherwise, in one example, a general operand data exception is identified.

In one embodiment, when the input list address is updated by an operation, the following applies:

when one or more records of the input list have been processed as part of the operation, the corresponding input list address is incremented by the number of bytes occupied by the processed record in the storage device. The formation and updating of the input list addresses depends on the addressing mode.

In the 24-bit addressing mode, bits 40-63 of the updated input list address replace corresponding bits in the input list address field of the parameter block, the carry (carry out) of bit position 40 of the updated input list address is ignored, and the contents of bit positions 0-39 of the input list address field of the parameter block are set to zero.

In the 31-bit addressing mode, bits 33-63 of the updated input list address replace corresponding bits in the input list address field of the parameter block, the carry in bit position 33 of the updated input list address is ignored, and the contents of bit positions 0-32 of the input list address field of the parameter block are set to zero.

In the 64-bit addressing mode, bits 0-63 of the updated input list address replace corresponding bits in the input list address field of the parameter block, ignoring the carry of bit position 0 of the updated input list address.

In the 24-bit and 31-bit addressing modes, when execution of an instruction is complete and the instruction is not suppressed, invalidated, or terminated, the input list address corresponding to each 64-bit of the active input list is updated even when the address is not incremented.

Input list N Length (Input ListN Length)393, 395, 397: for each input list, the parameter block specifies an input list length of 8 bytes. For the nth input list, bytes 584+16xN through 591+16xN of the parameter block contain an unsigned integer specifying the number of bytes in the nth input list.

Each entry list length corresponding to an entry list in the active state, as specified by the AILCC field, is an input to the operation and is updated by the operation. The length of each entry list corresponding to the entry list in the inactive state, as specified by the AILCC field, is ignored by the operation.

In various addressing modes, the contents of bit positions 0-63 of the input list length field specify the length of the corresponding input list.

When one or more records of the input list have been processed as part of the operation, the corresponding input list length is decremented by the number of bytes occupied in the storage device by the processed record. Bits 0-63 of the updated input list length replace bits 0-63 in the corresponding input list length field of the parameter block in various addressing modes.

And (4) reserving a field: there are multiple reserved fields (e.g., fields that contain no other information) in the parameter block. As an input to the operation, the reserved field should contain zero; otherwise, the operation of the future program may not be compatible. When the operation ends, the reserved field may be stored as zero or may remain unchanged.

Fig. 5A-5B summarize one example of the original and final values of the inputs for the sottl-SFLR function, including the fields in the parameter block.

In one embodiment, it is not necessary and desirable for a program to modify the parameter block to re-execute instructions between ending the operation with the condition code 3 set and branching back to the instruction for the purpose of resuming the operation.

In one embodiment, the SORTL-SFLR function includes multiple comparisons between keys of records from different input lists. In one example, when comparing keys, the following applies:

the keys are considered unsigned binary integers, also known as unstructured data.

When determining which key contains the lowest or highest value, it may not be necessary to access all bytes for each key being compared. The number of bytes per key per comparison (referred to as the unit of key comparison) is model dependent. The number of bytes of the key accessed is an integer unit of key comparison.

When comparing keys of equal value, in one example, the key from the input list with the highest input list number is selected to precede other keys with the same value in sorted order. In this case, the corresponding record from the input list with the highest input list number is stored to the first operand before the other records with the same key value. This applies to both ascending and descending sort orders.

One implementation may maintain a history of previous comparisons between records from the active input list. Instead of accessing and comparing previously compared records, the history may be referenced when available and applicable. The reference to the history reduces the execution time required to generate the results, thereby improving processing within the computing environment.

The SORTL-SFLR function includes selecting records from the set of input lists in a specified sorted order, and placing the selected records at a first operand location. As the operation proceeds, the current values of the first operand address and the address of the active input list are maintained. This function is performed in units of operations (units). During each unit of operation, for each active input list, the key specified by the corresponding current input list address is checked and one record is placed at the first operand location.

When the Merge Mode (MM) is zero, the active input list specifies lists in random order, e.g., left to right, each of which is considered to include a record. When MM is zero, the records stored to the first operand location constitute one or more output lists, and the starting address and length of each output list are stored to the second operand location. When MM is zero, each operation unit includes the following steps in a specified order as an example:

1. determining whether a next record to be stored to the first operand location can be included in a most recent output list (an output list including records most recently stored to the first operand location) as follows:

when the Continuation Flag (CF) is zero and the first operation unit is being processed, no record has been stored to the first operand location and the next record to be stored will be the first record of the output list.

When the CF is 1, the previous execution of the instruction ends with condition code 1, and the first unit of operation is being processed for the current execution of the instruction, the next record to be stored will be the first record of the output list.

When CF is 1, IILF is zero, EILF is zero, the previous execution of the instruction ends with condition code 2, and the first unit of operation is being processed for the current execution of the instruction, the next record to be stored will be the first record of the output list.

When CF is 1, IILF or EILF is 1, the previous execution of the instruction ends with condition code 2, and the first unit of operation is being processed for the current execution of the instruction, the next record to be stored may be included in the most recent output list.

When the CF is 1, the previous execution of the instruction ends with the condition code 3, and the first unit of operation is being processed for the current execution of the instruction, the next record to be stored may be included in the most recent output list.

When the operating unit being processed is not the first operating unit of the instruction to be currently executed, the next record to be stored may be included in the most recent output list.

2. When the next record to be stored can be included in the most recent output list, a set of records that are eligible for inclusion in the most recent output list is determined. For each input list that is active, non-empty, and not incomplete, the key of the record specified by the current input list address (the current input key) is compared to the key of the record most recently stored to the first operand location (the previously stored key). To this end, the reference to the previously stored key is not a reference to the first operand location. Instead, it is a reference to the list of inputs from which to select a key, or it is a reference to the continue recording recall buffer. When the operation is being resumed and the current execution of the instruction has not placed any records at the first operand location, it is a reference to the continue record recall buffer.

When the sort order is ascending and the value of the current input key is greater than or equal to the value of the previously stored key, the current input key is considered to belong to the set of keys eligible for inclusion in the most recent output list. When the sort order is descending and the value of the current input key is less than or equal to the value of the previously stored key, the current input key is considered to belong to the set of keys eligible for inclusion in the most recent output list. When the number of keys in the set of keys eligible for inclusion in the most recent output list is zero, the next record to be stored will be the first record of the output list. When the number of keys in the set of keys eligible for inclusion in the most recently output list is non-zero, the next record to be stored will be included in the most recently output list.

3. When the next record to be stored is included in the most recently output list, the keys in the set of keys that qualify for inclusion in the most recently output list are compared. When the sorting order is ascending, the smallest key value and the corresponding record are selected. When the sort order is descending, the largest key value and corresponding record are selected.

4. When the next record to be stored will be the first record of the output list, the key of the record specified by the current input list address corresponding to the active, non-empty and non-incomplete input list is compared. When the sorting order is ascending, the smallest key value and the corresponding record are selected. When the sorting order is descending, the largest key value and corresponding record are selected.

5. The selected record is placed at the current first operand location.

6. The current first operand address is incremented by a number of bytes equal to the selected record length.

7. The current entry list address corresponding to the entry list containing the selected record is incremented by a number of bytes equal to the length of the selected record.

As part of the operation when the merge mode is zero, for each output list stored at a first operand location, a corresponding Output List Description (OLD) is stored at a second operand location. Each OLD includes an OLD address of, for example, 8 bytes specifying the location of the first record in the corresponding output list, and an OLD length of, for example, 8 bytes specifying the length (in bytes) of the corresponding output list. When an operation ends with condition code 3 equal to 1, condition code 2, and EILF equal to 1, or with condition code 2 and IILF equal to 1, the most recent output list being processed at the end of the operation may be partially processed and incompletely processed. That is, the number of records in the output list of the partial process is an intermediate value, and may be increased when the operation is resumed. In this case, the Output List Description (OLD) corresponding to the partially processed output list is not placed at the second operand location until after the operation is resumed and the output list is fully processed.

When the merge mode is zero and the operation ends after storing one or more records and normal completion does not occur, the key of the last record stored to the first operand location is also stored to the continue record recall buffer.

When the merge mode is zero and the operation ends due to normal completion, one or more output lists have been placed at the first operand location and the output list has been depicted as being placed at the second operand location. The program may use the output list description as an input list address and length value in a parameter block for a subsequent SORTL operation.

6A-6D illustrate a first operand and a second operand before and after performing SORTL-SFLR in merge mode equal to zero. Referring to FIGS. 6A-6B, the FOSA600 is the first operand starting address: from R₁A specified location; FOEA602 is the first operand end address: from R₁+(R₁+1) -1 designated position; and OL 604 is an output list (e.g., output list1 … … output list N). Further, referring to fig. 6C-6D, SOSA610 is the second operand start address: r₂A specified location; SOEA612 is the second operand end address: from R₂+(R₂+1)-1 a specified location; and the OLD 614 is an output list designation (e.g., output list designation 1 … … output list designation N).

When the Merge Mode (MM) is 1, the active input list specifies a list that each is treated as having records in the sort order specified by the SO field of the parameter block from left to right. When MM is 1, the records stored to the first operand location constitute a single output list. When MM is 1, each unit operation includes, for example, the following steps in the specified order:

1. the keys of the records specified by the current entry list address corresponding to the active, non-empty, and incomplete entry list are compared. When the sorting order is ascending, the smallest key value and the corresponding record are selected. When the sorting order is descending, the largest key value and corresponding record are selected.

2. The selected record is placed at the current first operand location.

3. The current first operand address is incremented by a number of bytes equal to the selected record length.

4. The current entry list address corresponding to the entry list containing the selected record is incremented by a number of bytes equal to the length of the selected record.

7A-7B illustrate the first operand before and after executing SORTL-SFLR with merge mode equal to 1. Referring to FIGS. 7A-7B, the FOSA 700 is the first operand starting address: from R₁A specified location; FOEA 702 is the first operand end address: from R₁+(R₁+1) -1 designated position; and OL 704 is an output list (e.g., output list 1).

As part of the operation when the merge mode is zero or one, the entry list address and length of the entry list in the active state are updated. For each input list that is in an active state, the input list address is incremented by the number of bytes from the record of the input list that was selected and placed at the first operand location during the operation, and the input list length is decremented by the same number. The formation and updating of the input list addresses depends on the addressing mode.

As the operation proceeds, an incomplete input list may be encountered. An incomplete input list is identified during an operation cell attempting to reference a record from the incomplete input list. Multiple operating units may be completed before an incomplete input list is identified. This applies when the merge mode is 0 or 1.

As the operation proceeds, an access exception may be encountered to access the input list, the first operand, or the second operand (as applicable). An access exception is identified during an operating unit attempting to access a storage location for which there is an access exception. Multiple operating units may be completed before an incomplete input list is identified. This applies when the merge mode is 0 or 1.

When the operation ends with partial completion, internal state data, which may contain a history of previous comparisons between records, may be stored to the Continue State Buffer (CSB) field of the parameter block. Subsequently, when the instruction is re-executed, the contents of the CSB may be loaded into the implementation for the purpose of resuming the operation, and the history may be referenced when the operation resumes. This applies when the merge mode is 0 or 1.

Normal completion occurs when records from the active input list have been sorted and stored to the first operand.

In one embodiment, when an operation ends due to normal completion, the following occurs:

general register R₁And R₁The address and length in +1 are updated separately.

When MM is zero, the general register R₂And R₂The address and length in +1 are updated separately.

The input listN address and input listN length fields are updated for the input list in the active state.

The set model version number is set.

The continue flag is set to zero.

The empty input list flag is set to zero.

The null input list number is set to zero.

The incomplete input list flag is set to zero.

The incomplete input list number is set to zero.

The condition code 0 is set.

The formation and updating of addresses and lengths depends on the addressing mode.

When normal completion occurs, the CSB field of the parameter block is undefined after the operation is finished.

In one embodiment, when the number of bytes determined by the CPU has been processed, the operation ends and the following occurs:

general register R₁And R₁The address and length in +1 are updated separately.

When MM is zero, the general register R₂And R₂The address and length in +1 are updated separately.

The input listN address and input listN length fields are updated for the input list in the active state.

The model version number is set.

The continuation flag is set to 1.

When the MM is zero and one or more records have been placed at the first operand location during execution of the instruction, the key value is stored to the continue record recall buffer.

The continue status buffer is updated.

The empty input list flag is set to zero.

The null input list number is set to zero.

The incomplete input list flag is set to zero.

The incomplete input list number is set to zero.

The condition code 3 is set.

The formation and updating of addresses and lengths depends on the addressing mode.

The number of bytes determined by the CPU depends on the model and may be a different number each time an instruction is executed. The number of bytes determined by the CPU is typically non-zero. Although this number may be zero and represent a no-progress case, the CPU protects against constant recurrence of the no-progress case.

After the instruction ends with, for example, condition code 3 set, it is desirable that the program does not modify any input or output specification of the instruction and branches back to re-execute the instruction to resume operation.

In one embodiment, when bit 0 of the Empty Input List Control (EILCL) is 1, and the length of the input list0 becomes zero during the operation, and normal completion is not applicable, the operation ends and the following occurs:

general register R₁And R₁The address and length in +1 are updated separately.

When MM is zero, the general register R₂And R₂The address and length in +1 are updated separately.

The input listN address and input listN length fields are updated for the input list in the active state.

The model version number is set.

The continuation flag is set to 1.

When EILCL is binary 10 and MM is zero, the key value may be stored to the continue recording recall buffer. When the EILCL is binary 11 and the MM is zero, the key value is stored to the continue recording recall buffer. In either case, one or more records have been placed at the first operand location during execution of the instruction.

The continue status buffer is updated.

The empty input list flag is set (refer to fig. 8, which shows various parameter block fields when the operation ends).

The empty input list number is set (refer to fig. 8).

The incomplete input list flag is set to zero.

The incomplete input list number is set to zero.

The condition code 2 is set.

The formation and updating of addresses and lengths depends on the addressing mode.

In one embodiment, when bit 1 of the Empty Input List Control (EILCL) is 1, and the length of the active input list other than input list0 becomes zero during the operation, and normal completion is not applicable, the operation ends and the following occurs:

general register R₁And R₁The address and length in +1 are updated separately.

When MM is zero, the general register R₂And R₂The address and length in +1 are updated separately.

The input listN address and input listN length fields are updated for the input list in the active state.

The model version number is set.

The continuation flag is set to 1.

When the EILCL is 01 binary and the MM is 0, the key value may be stored to the continue recording recall buffer. When the EILCL is binary 11 and the MM is zero, the key value is stored to the continue recording recall buffer. In either case, one or more records have been placed at the first operand location during execution of the instruction.

The continue status buffer is updated.

The empty input list flag is set (refer to fig. 8).

The empty input list number is set (refer to fig. 8).

The incomplete input list flag is set to zero.

The incomplete input list number is set to zero.

The condition code 2 is set.

The formation and updating of addresses and lengths depends on the addressing mode.

In one embodiment, when an incomplete input list is encountered in the active state, the operation ends and the following occurs:

general register R₁And R₁The address and length in +1 are updated separately.

When MM is zero, the general register R₂And R₂The address and length in +1 are updated separately.

The input listN address and input listN length fields are updated for the input list in the active state.

The model version number is set.

The continuation flag is set to 1.

When the MM is zero and one or more records have been placed at the first operand location during execution of the instruction, the key value is stored to the continue record recall buffer.

The continue status buffer is updated.

The empty input list flag is set to zero.

The null input list number is set to zero.

The Incomplete Input List Flag (IILF) is set to 1.

The input list numbers of the encountered incomplete input list are placed in the Incomplete Input List Number (IILN) field of the parameter block.

The condition code 2 is set.

The formation and updating of addresses and lengths depends on the addressing mode.

In one embodiment, when the length of the first operand is not sufficient to store another record, the operation ends and the following occurs:

updating general registers R separately₁And R₁Address and length in + 1.

When MM is zero, the general register R is updated respectively₂And R₂Address and length in + 1.

The input listN address and input listN length fields are updated for the input list in the active state.

The set model version number is set.

The continue flag is set to 1.

When the MM is zero and one or more records have been placed at the first operand location during execution of the instruction, the key value may be stored to the continue record recall buffer.

The resume state buffer is updated.

The empty input list flag is set to zero.

The null input list number is set to zero.

The incomplete input list flag is set to zero.

Incomplete input list number set to zero

A condition code 1 is set.

The formation and updating of addresses and lengths depends on the addressing mode.

In one embodiment, when the Merge Mode (MM) is zero and the length of the second operand is less than 16, the operation ends and the following occurs:

updating general registers R separately₁And R₁Address and length in + 1.

Updating general registers R separately₂And R₂Address and length in + 1.

The input listN address and input listN length fields are updated for the input list in the active state.

The model version number is set.

The continue flag is set to 1.

When one or more records have been placed at the first operand location during execution of the instruction, the key value may be stored to the continue record recall buffer.

The resume state buffer is updated.

The empty input list flag is set to zero.

The null input list number is set to zero.

The incomplete input list flag is set to zero.

The incomplete input list number is set to zero.

A condition code 1 is set.

The formation and updating of addresses and lengths depends on the addressing mode.

An operation end condition is referred to as partial completion when execution of an instruction ends in completion (not in throttling, invalidation, or termination) and normal completion does not occur.

When applicable, PER store change events are identified for the first operand location, the second operand location, the continue record recall buffer, and the portion of the stored parameter block. When a PER storage change event is identified, less than 4K additional bytes are stored to operand locations that intersect the designated PER storage area before the event is reported.

When applicable, a PER zero address detection event is identified for the parameter block, the first operand location, and the second operand location. Zero address detection does not apply to the input list address and the resume record recall buffer start specified in the parameter block.

For a description of examples of Other Conditions applied to the SORTL-SFLR function, reference is made to the following Other Conditions (Other Conditions).

When the instruction ends with condition code 1, the program may modify the first operand address, the first operand length, the second operand address, the second operand length, any active input list addresses, and any active input list lengths as appropriate, followed by resuming operation.

When the instruction ends with condition code 2, IILF equal to zero, and EILF equal to zero, the program may modify the first operand address, the first operand length, the second operand address, the second operand length, any active input list addresses, and any active input list lengths as appropriate, and then resume operations.

When the instruction ends with condition code 2 and EILF equal to 1, the program can modify the entry list address and length of the entry list specified by the EILN appropriately, followed by resuming operation. In this case, the program may also modify the first operand address and the first operand length when the Merge Mode (MM) is 1.

When the instruction ends with condition code 2 and IILF equal to 1, the program can appropriately modify the entry list address and length of the entry list specified by IILN, and then resume operation. In this case, the program may also modify the first operand address and the first operand length when the Merge Mode (MM) is 1.

When an instruction ends with the condition code 3, and before the instruction is re-executed for a resume operation, the program modifies any active input list address or length, first operand address or length, or second operand address or length, the result being unpredictable.

Function code 2: SORTL-SVLR (Variable Length record sorting) (Sort Variable-Length Records)

The operation of the SORTL-SVLR function is the same as that of the SORTL-SFLR function, except that:

the record includes, for example, a fixed length key 900, an 8 byte Payload Length (PL)902, and a variable length payload 904 as shown in fig. 9. Thus, the recording has a variable length.

Bytes 14 to 15 of the parameter block of the SORTL-SVLR function are ignored.

The least significant, e.g., 2 bytes, of the payload length field of each record specifies the length in bytes of the payload in the same record. A payload length of zero is valid. In one example, the payload length will be a multiple of, for example, 8; otherwise, a general operand data exception is identified. The most significant of the payload length field-e.g. -6 bytes is reserved bytes and should contain zeros; otherwise, the operation of the future program may not be compatible. The sum of the key length 8 and the payload length is no greater than, for example, 4096; otherwise, in one example, a general operand data exception is identified. When a general operand data exception is identified due to an inappropriate payload length, the input list address corresponding to the active input list that encountered the exception specifies the logical address of the leftmost byte of the error record. When the variable length record is stored to the first operand location, the reserved bytes of the payload length field are not modified.

The incomplete input list may not be recognized during an operation unit that attempts to reference only keys from records of the input list having an input list length larger than the key size and smaller than the record size. In this case, an incomplete input list will be identified when attempting to store a record from the incomplete input list to the first operand location.

The parameter blocks of the SORTL-SVLR function are the same as those of the SORTL-SFLR function, except for bytes 14 through 15 as shown above.

For a description of other conditions applicable to the SORTL-SVLR function, please refer to the following other conditions. Special Conditions (Special Conditions)

In one embodiment, a specified exception is identified when an attempt is made to perform list ordering and any of the following applies:

bits 57-63 of general register 0 specify unassigned or uninstalled function codes.

R₁The field specifies the odd numbered register or general register 0.

R₂The field specifies the odd numbered register or general register 0. This applies when the Merge Mode (MM) is 0 or 1.

The parameter block is not specified on a doubleword boundary.

The SORTL-SFLR function or the SORTL-SVLR function is specified, and the first operand is not specified on a doubleword boundary.

When MM is zero, the SORTL-SFLR or SORTL-SVLR function is specified, and the second operand is not specified on a doubleword boundary.

In one embodiment, a specified exception is identified when a list ordering is attempted to be performed and any of the following applies:

the SORTL-SFLR or SORT-SVLR function is specified and no bit or bits of bits 0-7 of the parameter block version number contain the value 1, in which case operation is suppressed.

The SORTL-SFLR or SORTL-SVLR functionality is specified and the size or format of the parameter block specified by the parameter block version number is not supported by the model, in which case operation is suppressed.

The SORTL-SFLR or SORTL-SVLR function is specified, and the record key length is specified as a key size of 0, a key size other than a multiple of 8, or a key size larger than 4096, in which case the operation is suppressed.

The SORTL-SFLR function is specified, and the record payload length specifies a payload size that is not a multiple of 8, or is greater than 4096 when the payload size is added to the key size, in which case operation is suppressed.

The SORTL-SVLR function is specified, and the record payload length specifies a payload size that is not a multiple of 8, or greater than 4088 when the payload size is added to the key size, in which case whether the operation is inhibited or terminated depends on the model.

The SORTL-SFLR or SORTL-SVLR function is specified and the value of the active entry list count code (AILCC) plus one is greater than the number of entry lists described by the parameter block, in which case operation is inhibited.

The SORTL-SFLR or SORTL-SVLR function is specified, and no entry list address corresponding to the active entry list is specified on the doubleword boundary, in which case operation is suppressed.

Other conditions

In one embodiment, the following conditions apply:

execution of the instruction is interruptible. Updating general register R when an interrupt occurs₁And R₂General register R of₁+1 and R₂Length in +1 and specific fields of the parameter block, so that the instruction resumes at the point of interruption when it is re-executed.

For locations more than 4 kbytes to the right of the location specified by the first operand address, an access exception is not identified. For locations more than 4 kbytes to the right of the location specified by the input list address, an access exception is not identified.

If an access exception is identified due to being directed to the first operand, the second operand, or any input list, the result is that an exception is identified or the condition code 3 is set. If the condition code 3 is set, assuming the exception condition still exists, an exception will be identified when the instruction is executed again to continue processing the same operands.

When a recorded key crosses a page boundary and an access exception condition exists for both pages, either access exception may be identified.

When an access exception condition exists for a plurality of keys being processed during a single unit of operation, any of these conditions can be identified.

When a parameter block crosses a page boundary and an access exception condition exists for both pages, an access exception is identified for the leftmost page.

When the operation ends with a partial completion, up to 4 kbytes of data may have been stored within the first operand at the location specified by the updated first operand address or to the right thereof. Such storage results in setting the change bit (when applicable) and identifying the PER storage change event (when applicable). When the instruction is executed again to continue processing the same operands, the store will be repeated to these locations.

As observed by the CPU, other CPUs, and channel programs, references to the parameter block, first operand, output list description buffer, and input list in the active state may be multiple access references, accesses to these storage locations are not necessarily block parallel, and the sequence of these accesses or references is undefined.

In one embodiment, when the specified function is SORTL-SFLR or SORTL-SVLR and any of the following applies, the result is unpredictable:

the parameter block overlaps with any active input list or first operand.

Any active input list overlaps the first operand.

The merge mode is zero and the parameter block overlaps the second operand or the continue record recall buffer.

The merge pattern is zero and any active input list overlaps with the second operand or the continue record recall buffer.

The merge pattern is zero and the first operand overlaps the second operand or the resume record recall buffer.

The merge pattern is zero and the second operand overlaps the continue record recall buffer.

Another CPU or channel program is stored to the input list or key to continue recording the record in the recall buffer.

Example result condition code:

0 is normally done

1 the length of the first operand is less than the size of the record, or the merge pattern is zero and the length of the second operand is less than 16 (i.e., the first or second operand is not long enough to continue)

2 encountered an incomplete input list (IILF ═ 1), or EILCL was non-zero and the length of the input list became equal to zero during operation (i.e., encountered an incomplete or empty input list)

3 the amount of data determined by the CPU is processed (i.e., completion of the CPU determination)

Program exception:

access (extract, input list; extract and store, parameter Block and resume record Recall buffers; store, operands 1 and 2)

Data with DXC (Data Exception Code/Data Exception Code) 0, general purpose operand

Operation (if no enhancement sequencing facility is installed)

Specification of

Transaction constraints

An example of the execution priority of the list sort instruction is shown below. When there are multiple conditions with priority values beginning with 13, the condition identified is the condition encountered first as the operation proceeds. When the operation is being resumed (continuation flag is 1 at the beginning of execution of the instruction), the history of previous comparisons between keys may be used instead of initially accessing the active and not empty input list. As a result, access exceptions to access a particular input list may not be encountered at the same processing point as when the history of previous comparisons is not used. When variable length records are processed, the evaluation may be performed partially before the payload length is determined and fully after the payload length is determined, as a condition for the function of the record length. As a result, the priority observed among such conditions may be different when the condition is determined to exist after only partial evaluation of the requirements, rather than after full evaluation of all the requirements.

Example execution priority (SORTL)

1. Exceptions with the same priority as the program interrupt condition for the general case.

An access exception to the A second instruction halfword.

B operation is abnormal.

C transaction constraints.

8. A specified exception (specification exception) due to an invalid function code or an invalid register number.

B due to a specified exception to the first operand that is not specified on a doubleword boundary.

C due to a specified exception to the first operand that is not specified on a doubleword boundary.

D is due to a specified exception for the second operand that is not specified on a doubleword boundary and the merge pattern is zero.

9. Access to bytes 0-7 of the parameter block is abnormal.

10. General operand data exceptions caused by unsupported values of the PBVN field in the parameter block.

11. Access to bytes other than bytes 0-7 in the access parameter block is abnormal.

12. Invalid values of fields in the parameter block other than the PBVN cause general operand data exceptions.

An access exception to A access the active input list.

B when the merge mode is 0, the access continues to record the access exception of the recall buffer.

C access first operand access exception.

An access exception to access the second operand when the D merge mode is 0.

E due to condition code 2 of the incomplete input list.

F conditional code 1 due to an insufficient length of the first operand

G is due to the condition code 1 that the length of the second operand is insufficient when the merge mode is 0.

H a general operand data exception due to an invalid payload length of a variable length record.

I is due to condition code 2 of the empty input list.

14. Condition code 3.

Programming Notes. In one embodiment:

1. the intended use of the Empty Input Lists Control (EILCL) is as follows:

EILCL (0:1) (binary) description

00 stops after the records of the active input list (e.g., all records of all active input lists) are sorted.

10 stops after the input list0 (always active) becomes empty.

11 stop after any active input list becomes empty.

2. When the Active Input List Count Code (AILCC) is zero, there is, for example, only one active input list, and the result stored at the first operand location is the same as the data obtained from input list 0.

3.A model implementing separate instruction and data caches may use an instruction cache to perform store operand fetch references to data in an active input list.

4. When a program desires to call list ordering multiple times in a merge mode equal to zero, as part of processing a large data set, the program, in one example, utilizes the available input lists and divides records evenly among the input lists. This reduces the number of times data is accessed when sorting the entire data set.

5. After a list sort operation with merge mode equal to zero ends with condition code 0 set and multiple Output List Descriptions (OLDs) in the second operand, a program that is intended to generate a single record list in sort order is to invoke another list sort operation, in which the input list is designated as the result OLD from the previous list sort call. In this case, in one example, the second call to sort the list specifies a merge mode equal to 1.

Similarly, in one embodiment, to generate a complete set of ordered lists from a large number of randomly ordered records after invoking a list ordering with a merge pattern equal to zero as many times as needed or desired, in one example, invoking a list ordering with a merge pattern equal to 1 as many times as needed or desired generates a single ordered list.

6. In one embodiment, to reduce the number of times each record is accessed when merging multiple sorted lists into a single list sorted in ascending order (for example), the program performs the following:

the maximum number N of input lists available for list ordering is determined.

The key of the first record of the sorted list that has not yet been merged into the single list is compared. The N lists with the smallest first key values are selected.

List ordering with Merge Mode (MM) equal to 1 is performed, with Empty Input List Control (EILCL) equal to binary 10, input list0 specifying only the first record of the list with the highest first key value of the selected N lists, and the remaining input lists specifying the other N-1 selected lists.

The process is repeated after sorting the list ending with condition code 2, IILF equal to zero and EILF equal to zero.

7. After the list sort ends with condition code 1 set, in one example, before calling the list sort again, the program performs the following actions to resume operation:

if the first operand length is less than the maximum record length of the record being processed, the first operand length or first operand address and length should be updated as appropriate.

If the merge pattern (MM) is zero and the second operand length is less than 16, the second operand length or the second operand address and length should be updated as appropriate.

If the length of any active input list is equal to zero, the corresponding input list address and length may be updated to specify another record list to be included in the sort operation.

8. After the list sort ends with condition code 2 set, in one example, before calling the list sort again, the program performs the following actions to resume operation:

if the Incomplete Input List Flag (IILF) is 1, the input list length or input list address and the length of the input list identified by the Incomplete Input List Number (IILN) should be updated as appropriate.

If the empty entry list flag (EILF) is 1, the entry list length or entry list address and the length of the entry list identified by the empty entry list number (EILN) should be updated as appropriate.

If IILF is zero, EILF is zero, and input list0 is zero in length, either the input list0 length or the input list0 address and length should be updated as appropriate. In addition, the entry list address and length of the active entry list may also be updated, which may be an appropriate action if there is only one record originally specified by entry list0 and the empty entry list control (EILCL) is a binary 10.

If the Merge Mode (MM) is 1 and the first operand length is less than the maximum record length of the record being processed, the first operand length or the first operand address and length should be updated as appropriate.

If MM is zero and IILF is 1 or EILF is 1, the first operand address and length and the second operand address and length should not be updated.

If MM is zero, IILF is zero, EILF is zero, and the first operand length is less than the maximum record length of the record being processed, the first operand length or first operand address and length should be updated as appropriate.

If MM is zero, IILF is zero, EILF is zero, and the second operand length is less than 16, then the second operand length or the second operand address and length should be updated as appropriate.

As described herein, in one aspect, a single instruction (e.g., a single architected machine instruction, list ordering) is provided to perform the ordering and/or merging operations on a general purpose processor. In one example, a program implementing sort and/or merge operations for a database and executing on a general purpose processor can replace a significant subset of basic instructions with a single instruction to implement the operations. The instruction is, for example, a hardware instruction defined in an Instruction Set Architecture (ISA). As a result, the complexity of procedures associated with the sort and/or merge operations is reduced. Furthermore, the performance of the operation, and thus the processor, is improved.

Advantageously, the list sort instructions are executed on a general purpose processor (e.g., a central processing unit, referred to herein as a processor) rather than a special purpose processor, such as a Graphics Processing Unit (GPU), a database engine (DBE), or other type of special purpose processor.

Although different fields and registers are described, one or more aspects of the present invention may use other, additional, or fewer fields or registers, or other sized fields and registers, etc. Many variations are possible. For example, an implicit register may be used in place of an explicitly specified instruction register or field, and/or an explicitly specified register or field may be used in place of an implicit register or field. Other variations are also possible.

In one example, the list sort instruction works on a large amount of data (such as megabytes or megabytes) of a database (e.g., a business database). Thus, the instruction is interruptible and processing can resume where interrupted.

Further details of one embodiment of processing associated with a list sort instruction are described with reference to FIGS. 10A-10B. In one example, the processing is performed by a processor, such as processor 102 or 204.

In one example, a list sort instruction is obtained and execution begins (step 1000). As indicated above, multiple functions may be specified for the list sort instruction, and thus, the function to be performed is determined (step 1002). If the function is a query function (e.g., function code 0 is specified in general register 0) (query 1004), then the available functions are provided (step 1006). For example, an installed function vector 342, an installed interface size vector 344, and an installed parameter block format vector 346 are stored in the parameter block.

However, if the request is not for a query function (INQUIRY 1004), then a determination is made as to whether an ordering function is being requested, such as ordering fixed length records or ordering variable length records (INQUIRY 1008). If no query or ranking function is specified, then processing ends, in one example, with, for example, specifying an exception (step 1010). However, if a sort function is specified, then a further determination is made as to whether a merge is requested (e.g., merge mode 310 is set to 1) (INQUIRY 1012).

If no merge is requested, sorting is performed on the multiple input lists obtained with the parameter block specified by general register 1 (e.g., input list address fields 392, 394, 396 of the parameter block) (step 1020). In one embodiment, the plurality of records are partitioned (e.g., uniformly) by issuing a list sort instruction to the program in the plurality of input lists. At step 1022, the multiple input lists are sorted using the recorded keys. The ordering may be in ascending or descending order, as indicated in the order of ordering field 366 of the parameter blocks.

Sorting produces intermediate output lists, each in sorted order. These output lists are stored in a first operand, step 1024, and then the description of each list is stored in a second operand, step 1026.

If a single list of records is desired to be sorted, in one embodiment, the list sort instruction specifying the merge option is re-executed.

Returning to INQUIRY 1012, if merging is specified, the input is a plurality of lists in a pre-ordered order, which in one example is specified with a parameter block (step 1030). At step 1032, the lists are merged into a single list using the keys of the records in the list. At step 1034, the merged list is stored in the first operand.

In one embodiment, referring to FIG. 10B, the sort or merge operation may be interrupted, so in one example, if the operation is interrupted (query 1050), then a continuation indicator (e.g., continuation flag 368 for the parameter block) is set to, for example, 1 (step 1052). Further, information available for subsequent recovery operations is stored, for example, in a parameter block (step 1054). For example, metadata (such as information related to previously performed comparisons) is stored in the continuation status buffer 390 so that those comparisons do not have to be repeated. Additional or other information may also be stored, and/or other indicators may be set. Many variations are possible.

One or more aspects of the present invention are inseparable from computer technology and facilitate processing within a computer, thereby improving its performance. The use of a single architected machine instruction to perform the ordering and/or consolidation of a large number of database records of a database replaces many software instructions, thereby improving performance within a computing environment. These sorted and/or merged records may be used in many areas of technology that manage and/or use large amounts of data, such as computer processing, medical processing, security, and the like. By providing optimizations in the ordering/merging, these areas of technology are improved by reducing the execution time in acquiring and using information, as well as reducing storage requirements.

11A-11B depict further details of one embodiment of facilitating processing within a computing environment as it relates to one or more aspects of the present invention.

Referring to FIG. 11A, an instruction to perform a sort operation is obtained (1100). The instructions are single architected machine instructions of an instruction set architecture (1102), and are executed by a general purpose processor of the computing environment (1104). The performing includes, for example, sorting the plurality of input lists to obtain one or more sorted output lists (1106), and providing the one or more sorted output lists as output (1108).

In one embodiment, the instructions include: an opcode field comprising an opcode to specify a list sort operation; and a field for specifying a location for storing the one or more ordered output lists (1110). In another embodiment, the instruction includes another field to specify another location that stores one or more output list descriptions (1112). As an example, the one field is a register field that specifies a register that includes an address of the one location, and the other field is another register field that specifies another register that includes an address of the other location (1114).

In one example, referring to FIG. 11B, the instruction employs an implicit register to determine the function to be performed by the instruction (1120). As an example, the function is selected from a group of functions consisting of: a query available function, a fixed length record sort function, and a variable length record sort function (1122).

As another example, the instruction employs another implicit register to locate a parameter block in memory used by the instruction (1123). The parameter block includes information used by the instruction depending on the function to be performed (1124). In one particular example, the function to be performed is a fixed length record ordering function or a variable length record ordering function, and the parameter block includes information to locate a plurality of input lists and information to continue ordering based on the ordering being interrupted (1126).

In one embodiment, the one implicit register further includes an operation mode indicator for specifying whether a merge of the one or more sorted output lists is to be performed (1128).

As a specific example, the instructions include: an opcode field comprising an opcode to specify a list sort operation; a first register field comprising a designation of a first register comprising an address for storing the one or more sorted output lists; and a second register field comprising a specification of a second register comprising an address for storing one or more output list descriptions, and wherein the instruction employs the first implicit register to determine a function to be performed by the instruction and the second implicit register to locate a block of parameters in memory used by the instruction (1130).

Other variations and embodiments are possible.

Aspects of the present invention may be used by many types of computing environments. Another embodiment of a computing environment to incorporate and use one or more aspects of the present invention is described with reference to FIG. 12A. In this example, computing environment 10 includes, for example, a local Central Processing Unit (CPU)12, a memory 14, and one or more input/output devices and/or interfaces 16 coupled to each other by, for example, one or more buses 18 and/or other connections. By way of example, computing environment 10 may include that provided by International Business machines corporation, Armonk, N.Y.A processor; HP Superdome with an Intel Itanium II processor, available from Palo Alto Hewlett packard, Calif., USA; and/or baseOther machines in the framework provided by international business machines corporation, hewlett-packard, intel corporation, oracle, or other companies. IBM, Z/Architecture, IBM Z, Z/OS, PR/SM, and PowerPC are trademarks or registered trademarks of International Business machines corporation in at least one jurisdiction. Intel and Itanium are trademarks or registered trademarks of Intel corporation or its subsidiaries in the united states and other countries.

The local central processing unit 12 includes one or more local registers 20, such as one or more general purpose registers and/or one or more special purpose registers used during processing within the environment. These registers include information that represents the state of the environment at any particular point in time.

In addition, the local central processing unit 12 executes instructions and code stored in memory 14. In one particular example, the central processing unit executes emulator code 22 stored in memory 14. This code enables a computing environment configured in one architecture to emulate another architecture. For example, the emulator code 22 allows machines based on architectures other than the z/Architecture hardware Architecture (such as PowerPC processors, HPSuperdome servers, or others) to emulate the z/Architecture hardware Architecture and execute software and instructions developed based on the z/Architecture hardware Architecture.

Further details regarding emulator code 22 are described with reference to FIG. 12B. The guest instructions 30 stored in the memory 14 include software instructions (e.g., related to machine instructions) developed for execution in an architecture different from that of the local CPU 12. For example, the guest instructions 30 may have been designed to execute on a z/Architecture-based hardware Architecture processor, but instead emulate on a local CPU12, which local CPU12 may be, for example, an Intel Itanium II processor. In one example, the emulator code 22 includes an instruction fetch routine 32 to obtain one or more guest instructions 30 from the memory 14 and optionally provide local buffering for the obtained instructions. It also includes an instruction conversion routine 34 to determine the type of guest instruction that has been obtained and to convert the guest instruction into one or more corresponding native instructions 36. This conversion includes, for example, identifying the function to be performed by the guest instruction and selecting the native instruction to perform the function.

Further, the emulator code 22 includes an emulation control routine 40 to cause native instructions to be executed. Emulation control routine 40 may cause local CPU12 to execute a routine of native instructions that emulate one or more previously obtained guest instructions, and at the end of such execution, return control to the instruction fetch routine to emulate the obtaining of the next guest instruction or set of guest instructions. Execution of the native instructions 36 may include loading data from the memory 14 into registers as determined by the conversion routine; storing data from the register back to the memory; or perform some type of arithmetic or logical operation.

Each routine is implemented, for example, in software that is stored in memory and executed by the local central processing unit 12. In other examples, one or more of the routines or operations are implemented in firmware, hardware, software, or some combination thereof. The registers of the emulated processor may be emulated using registers 20 of the local CPU or by using locations in memory 14. In embodiments, guest instructions 30, native instructions 36, and emulator code 22 may reside in the same memory or may be distributed among different memory devices.

The computing environments described above are only examples of computing environments that may be used. Other environments may be used, including but not limited to other non-partitioned environments, other partitioned environments, and/or other simulation environments; embodiments are not limited to any one environment.

Each computing environment can be configured to include one or more aspects of the present invention. For example, each computing environment may be configured to provide for ordering and/or merging in accordance with one or more aspects of the present invention.

One or more aspects may relate to cloud computing.

It should be understood that although the present disclosure includes detailed descriptions with respect to cloud computing, implementation of the teachings referenced herein is not limited to cloud computing environments. Rather, embodiments of the invention can be implemented in connection with any other type of computing environment now known or later developed.

Cloud computing is a service delivery model for enabling convenient, on-demand network access to a shared pool of configurable computing resources (e.g., networks, network bandwidth, servers, processing, memory, storage, applications, virtual machines, and services) that can be quickly configured and released with minimal administrative effort or interaction with service providers. The cloud model may include at least five characteristics, at least three service models, and at least four deployment models.

The characteristics are as follows:

self-service as required: cloud consumers can unilaterally provision computing capabilities, such as server time and network storage, automatically on demand without manual interaction with the service provider.

Wide network access: functionality is provided over a network and accessed through standard mechanisms that facilitate use by heterogeneous thin clients or thick client platforms (e.g., mobile phones, laptops, and PDAs).

Resource pooling: the provider's computing resources are pooled to serve multiple consumers using a multi-tenant model, with different physical and virtual resources dynamically allocated and reallocated as needed. There is a sense of location independence in that consumers typically have no control or knowledge over the exact location of the provided resources, but may be able to specify a location of higher level of abstraction (e.g., country, state, or data center).

Quick elasticity: in some cases, the functions may be quickly and elastically configured to expand and contract quickly and release quickly to contract quickly. The functionality available for configuration generally appears unlimited to the consumer and may be purchased in any number at any time.

Service of the metric: cloud systems automatically control and optimize resource usage by leveraging some level of abstraction metering capability that is appropriate to the type of service (e.g., storage, processing, bandwidth, and active user accounts). Resource usage can be monitored, controlled and reported, providing transparency to the provider and user of the service used.

The service model is as follows:

software as a service (SaaS): the capability provided to the consumer is to use the provider's applications running on the cloud infrastructure. These applications may be accessed from different client devices through a thin client interface, such as a web browser (e.g., web-based email). Consumers do not manage or control the underlying cloud infrastructure including network, server, operating system, storage, or even individual application functionality, with the possible exception of limited user-specific application configuration settings.

Platform as a service (PaaS): the capability provided to the consumer is to deploy consumer-created or acquired applications on the cloud infrastructure, created in programming languages and tools supported by the provider. The consumer does not manage or control the underlying cloud infrastructure, including the network, servers, operating system, or storage, but has control over the deployed applications and possibly the application hosting environment configuration.

Infrastructure as a service (IaaS): the capability provided to the consumer is to provide the consumer with the processing, storage, networking, and other basic computing resources that can deploy and run any software that can include operating systems and applications. The consumer does not manage or control the underlying cloud infrastructure, but has control over the operating system, storage, deployed applications, and possibly limited control over selected networking components (e.g., host firewalls).

The deployment model is as follows:

private cloud: the cloud infrastructure operates only for the organization. It may be managed by an organization or a third party and may exist either on-site or off-site.

Community cloud: the cloud infrastructure is shared by multiple organizations and supports specific communities with common concerns (e.g., tasks, security requirements, policies, and compliance considerations). It may be managed by an organization or a third party and may exist either on-site or off-site.

Public cloud: the cloud infrastructure is available to the public or large industry groups and is owned by organizations that sell cloud services.

Mixing cloud: a cloud infrastructure is made up of two or more clouds (private, community, or public) that remain unique entities but are bound together by standardized or proprietary techniques that enable portability of data and applications (e.g., cloud bursting for load balancing between clouds).

Cloud computing environments are service-oriented, with emphasis on statelessness, low coupling, modularity, and semantic interoperability. At the heart of cloud computing is an infrastructure that includes a network of interconnected nodes.

Referring now to FIG. 13, an illustrative cloud computing environment 50 is depicted. As shown, cloud computing environment 50 includes one or more cloud computing nodes 52, with which local computing devices used by cloud consumers, such as Personal Digital Assistants (PDAs) or cellular telephones 54A, desktop computers 54B, laptop computers 54C, and/or automobile computer systems 54N, may communicate. The nodes 52 may communicate with each other. They may be grouped, physically or virtually, in one or more networks (not shown), such as in the private, community, public, or hybrid clouds described above, or a combination thereof. This allows the cloud computing environment 50 to provide an infrastructure, platform, and/or software as a service for which cloud consumers do not need to maintain resources on local computing devices. It should be understood that the types of computing devices 54A-N shown in fig. 13 are intended to be illustrative only, and that computing node 52 and cloud computing environment 50 may communicate with any type of computerized device over any type of network and/or network addressable connection (e.g., using a web browser).

Referring now to FIG. 14, a set of functional abstraction layers provided by cloud computing environment 50 (FIG. 13) is shown. It should be understood in advance that the components, layers, and functions shown in fig. 14 are intended to be illustrative only and embodiments of the present invention are not limited thereto. As shown, the following layers and corresponding functions are provided:

the hardware and software layer 60 includes hardware and software components. Examples of hardware components include: a host computer 61; a RISC (reduced instruction set computer) architecture based server 62; a server 63; a blade server 64; a storage 65; and a network and networking component 66. In some embodiments, the software components include web application server software 67 and database software 68.

The virtualization layer 70 provides an abstraction layer from which the following examples of virtual entities may be provided: the virtual server 71; a virtual storage 72; virtual networks 73, including virtual private networks; virtual applications and operating systems 74; and virtual client 75.

In one example, the management layer 80 may provide the functionality described below. Resource provisioning 81 provides for dynamic acquisition of computing resources and other resources for performing tasks within the cloud computing environment. Metering and pricing 82 provides cost tracking when resources are utilized within the cloud computing environment and bills or invoices for consumption of those resources. In one example, these resources may include application software licenses. Security provides authentication for cloud consumers and tasks, as well as protection of data and other resources. The user portal 83 provides access to the cloud computing environment for consumers and system administrators. Service level management 84 provides cloud computing resource allocation and management such that the required service level is met. Service Level Agreement (SLA) planning and fulfillment 85 provides pre-arrangement and procurement of cloud computing resources for future requirements of the cloud computing resources as expected by the SLA.

Workload layer 90 provides an example of the functionality that may utilize a cloud computing environment. Examples of workloads and functions that may be provided from this layer include: map and navigation 91; software development and lifecycle management 92; virtual classroom education delivery 93; data analysis processing 94; a transaction 95; and an ordering and/or merging process 96.

Aspects of the present invention may be systems, methods, and/or computer program products at any possible level of integration of technical details. The computer program product may include a computer-readable storage medium (or media) having computer-readable program instructions thereon for causing a processor to perform aspects of the invention.

The computer readable storage medium may be a tangible device that can retain and store instructions for use by an instruction execution device. The computer readable storage medium may be, for example, but is not limited to, an electronic memory device, a magnetic memory device, an optical memory device, an electromagnetic memory device, a semiconductor memory device, or any suitable combination of the foregoing. A non-exhaustive list of more specific examples of the computer-readable storage medium includes the following: a portable computer diskette, a hard disk, a Random Access Memory (RAM), a read-only memory (ROM), an erasable programmable read-only memory (EPROM or flash memory), a Static Random Access Memory (SRAM), a portable compact disc read-only memory (CD-ROM), a Digital Versatile Disc (DVD), a memory stick, a floppy disk, a mechanical coding device (such as punch cards) or a raised structure in a recess having instructions recorded thereon), and any suitable combination of the foregoing. A computer-readable storage medium as used herein should not be interpreted as a transitory signal per se, such as a radio wave or other freely propagating electromagnetic wave, an electromagnetic wave propagating through a waveguide or other transmission medium (e.g., optical pulses through a fiber optic cable), or an electrical signal transmitted through a wire.

The computer-readable program instructions described herein may be downloaded from a computer-readable storage medium to a corresponding computing/processing device, or to an external computer or external storage device via a network (e.g., the internet, a local area network, a wide area network, and/or a wireless network). The network may include copper transmission cables, optical transmission fibers, wireless transmissions, routers, firewalls, switches, gateway computers and/or edge servers. The network adapter card or network interface in each computing/processing device receives computer-readable program instructions from the network and forwards these computer-readable program instructions for storage in a computer-readable storage medium within the corresponding computing/processing device.

The computer readable program instructions for carrying out operations of aspects of the present technology may be assembler instructions, Instruction Set Architecture (ISA) instructions, machine-related instructions, microcode, firmware instructions, state setting data, configuration data for an integrated circuit, or source code or object code written in any combination of one or more programming languages, including an object oriented Smalltalk, C + + or the like programming language, and procedural programming languages, such as the "C" programming language or similar programming languages. The computer-readable program instructions may execute entirely on the user's computer, partly on the user's computer, as a stand-alone software package, partly on the user's computer and partly on a remote computer or entirely on the remote computer or server. In the latter scenario, the remote computer may be connected to the user's computer through any type of network, including a Local Area Network (LAN) or a Wide Area Network (WAN), or the connection may be made to an external computer (for example, through the Internet using an Internet service provider). In some embodiments, an electronic circuit, including, for example, a programmable logic circuit, a Field Programmable Gate Array (FPGA), or a Programmable Logic Array (PLA), may personalize the electronic circuit by executing computer-readable program instructions using state information of the computer-readable program instructions in order to perform aspects of the present technique.

Aspects of the present technology are described herein with reference to flowchart illustrations and/or block diagrams of methods, apparatus (systems) and computer program products according to embodiments of the technology. It will be understood that each block of the flowchart illustrations and/or block diagrams, and combinations of blocks in the flowchart illustrations and/or block diagrams, can be implemented by computer-readable program instructions.

These computer-readable program instructions may be provided to a processor of a general purpose computer, special purpose computer, or other programmable data processing apparatus to produce a machine, such that the instructions, which execute via the processor of the computer or other programmable data processing apparatus, create means for implementing the functions/acts specified in the flowchart and/or block diagram block or blocks. These computer-readable program instructions may also be stored in a computer-readable storage medium that can direct a computer, a programmable data processing apparatus, and/or other devices to function in a particular manner, such that the computer-readable storage medium having the instructions stored therein comprise an article of manufacture including instructions which implement aspects of the function/act specified in the flowchart and/or block diagram block or blocks.

The computer-readable program instructions may also be loaded onto a computer, other programmable data processing apparatus, or other devices to cause a series of operational steps to be performed on the computer, other programmable apparatus or other devices to produce a computer implemented process such that the instructions which execute on the computer, other programmable apparatus or other devices implement the functions and acts specified in the flowchart and/or block diagram block or blocks.

The flowchart and block diagrams in the figures illustrate the architecture, functionality, and operation of possible implementations of systems, methods and computer program products according to various embodiments of the present technology. In this regard, each block in the flowchart or block diagrams may represent a module, segment, or portion of instructions, which comprises one or more executable instructions for implementing the specified logical function(s). In some alternative embodiments, the functions noted in the block may occur out of the order noted in the figures. For example, two blocks shown in succession may, in fact, be executed substantially concurrently, or the blocks may sometimes be executed in the reverse order, depending upon the functionality involved. It will also be noted that each block of the block diagrams and/or flowchart illustration, and combinations of blocks in the block diagrams and/or flowchart illustration, can be implemented by special purpose hardware-based systems which perform the specified functions or acts, or combinations of special purpose hardware and computer instructions.

In addition to the above, one or more aspects may be provided, promised, deployed, managed, serviced, etc. by a service provider who offers customer environment management. For example, a service provider can create, maintain, support, etc., computer code and/or computer infrastructure that performs one or more aspects for one or more customers. In return, the service provider may receive payment from the consumer, for example, according to a subscription and/or fee agreement. Additionally or alternatively, the service provider may receive payment from the sale of advertising content to one or more third parties.

In one aspect, an application for performing one or more embodiments may be deployed. As one example, deployment of an application includes providing a computer infrastructure operable to perform one or more embodiments.

As another aspect, a computing infrastructure may be deployed comprising integrating computer-readable code into a computing system, wherein the code in combination with the computing system is capable of performing one or more embodiments.

As yet another aspect, a process for integrating computing infrastructure can be provided that includes integrating computer readable code into a computer system. The computer system includes a computer-readable medium, wherein the computer medium includes one or more embodiments. The code in combination with the computer system is capable of performing one or more embodiments.

While various embodiments are described above, these are only examples. For example, other architectures of computing environments can be used to include and use one or more embodiments. Further, different instructions or operations may be used. In addition, different registers may be used and/or other types of indications (other than register numbers) may be specified. Many variations are possible.

Further, other types of computing environments may benefit and may be used. By way of example, data processing systems suitable for storing and/or executing program code are available that include at least two processors coupled directly or indirectly to memory elements through a system bus. The memory elements include, for instance, local memory employed during actual execution of the program code, bulk storage, and cache memories which provide temporary storage of at least some program code in order to reduce the number of times code must be retrieved from bulk storage during execution.

Input/output or I/O devices (including but not limited to keyboards, displays, pointing devices, DASD, magnetic tape, CDs, DVDs, thumb drives and other storage media, etc.) can be coupled to the system either directly or through intervening I/O controllers. Network adapters may also be coupled to the system to enable the data processing system to become coupled to other data processing systems or remote printers or storage devices through intervening private or public networks. Modems, cable modem and Ethernet cards are just a few of the available types of network adapters.

The terminology used herein is for the purpose of describing particular embodiments only and is not intended to be limiting. As used herein, the singular forms "a", "an" and "the" are intended to include the plural forms as well, unless the context clearly indicates otherwise. It will be further understood that the terms "comprises" and/or "comprising," when used in this specification, specify the presence of stated features, integers, steps, operations, elements, and/or components, but do not preclude the presence or addition of one or more other features, integers, steps, operations, elements, components, and/or groups thereof.

The corresponding structures, materials, acts, and equivalents of all means or step plus function elements, if any, in the claims below are intended to include any structure, material, or act for performing the function in combination with other claimed elements as specifically claimed. The description of one or more embodiments has been presented for purposes of illustration and description, but is not intended to be exhaustive or limited to the embodiments in the form disclosed. Many modifications and variations will be apparent to those of ordinary skill in the art. The embodiments were chosen and described in order to best explain various aspects and practical applications, and to enable others of ordinary skill in the art to understand the various embodiments with various modifications as are suited to the particular use contemplated.

Claims (20)

1. A computer program product for facilitating processing within a computing environment, the computer program product comprising:

a computer readable storage medium readable by a processing circuit and storing instructions for performing a method comprising:

obtaining an instruction to perform a sort operation, the instruction being a single architected machine instruction of an instruction set architecture; and

executing, by a general-purpose processor of the computing environment, the instructions, the executing comprising:

sorting the plurality of input lists to obtain one or more sorted output lists; and

providing the one or more sorted output lists as output.

2. The computer-program product of claim 1, wherein the instructions comprise: an operation code field including an operation code for specifying a list sort operation; and a field for specifying a location for storing the one or more ordered output lists.

3. The computer-program product of claim 2, wherein the instructions further comprise another field to specify another location to store one or more output list descriptions.

4. The computer program product of claim 3, wherein the one field is a register field, the register field specifying a register, the register including the address of the one location, and the other field is another register field, the other register field specifying another register, the other register including the address of the other location.

5. The computer program product of claim 1, wherein the instruction employs an implicit register to determine a function to be performed by the instruction.

6. The computer program product of claim 5, wherein the function is selected from a group of functions consisting of: a query available function, a fixed length record ordering function, and a variable length record ordering function.

7. The computer program product of claim 5, wherein the instruction employs another implicit register to locate a parameter block in memory used by the instruction, the parameter block including information used by the instruction depending on the function to be performed.

8. The computer program product of claim 7, wherein the function to be performed is a fixed length record ordering function or a fixed length record ordering function, and the parameter block includes information for locating the plurality of input lists and information to continue the ordering based on the ordering being interrupted.

9. The computer program product of claim 5, wherein the one implicit register further comprises an operation mode indicator to specify whether merging of the one or more ordered output lists is to be performed.

10. The computer-program product of claim 1, wherein the instructions comprise: an operation code field including an operation code specifying a list sort operation; a designated first register field comprising a first register comprising an address for storing the one or more sorted output lists; and a specified second register field comprising a second register comprising an address for storing one or more output list descriptions, and wherein the instruction employs a first implicit register to determine a function to be performed by the instruction and a second implicit register to locate a parameter block in memory used by the instruction.

11. A computer system for facilitating processing within a computing environment, the computer system comprising:

a memory; and

a general purpose processor coupled to the memory, wherein the computer system is configured to perform a method comprising:

obtaining an instruction to perform a sort operation, the instruction being a single architected machine instruction of an instruction set architecture; and

executing, by a general-purpose processor of the computing environment, the instructions, the executing comprising:

sorting the plurality of input lists to obtain one or more sorted output lists; and

providing the one or more sorted output lists as output.

12. The computer system of claim 11, wherein the instructions comprise: an operation code field including an operation code for specifying a list sort operation; and a field for specifying a location for storing the one or more ordered output lists.

13. The computer system of claim 12, wherein the instruction further comprises another field to specify another location to store one or more output list descriptions.

14. The computer system of claim 11, wherein said instruction employs an implicit register to determine a function to be performed by said instruction.

15. The computer system of claim 14, wherein the instruction employs another implicit register to locate a parameter block in memory used by the instruction, the parameter block including information used by the instruction depending on the function to be performed.

16. A computer-implemented method of facilitating processing within a computing environment, the computer-implemented method comprising:

obtaining an instruction to perform a sort operation, the instruction being a single architected machine instruction of an instruction set architecture; and

executing, by a general-purpose processor of the computing environment, the instructions, the executing comprising:

sorting the plurality of input lists to obtain one or more sorted output lists; and

providing the one or more sorted output lists as output.

17. The computer-implemented method of claim 16, wherein the instructions comprise: an operation code field including an operation code for specifying a list sort operation; and a field for specifying a location for storing the one or more ordered output lists.

18. The computer-implemented method of claim 17, wherein the instruction further comprises another field to specify another location to store one or more output list descriptions.

19. The computer-implemented method of claim 16, wherein the instruction employs an implicit register to determine a function to be performed by the instruction.

20. The computer-implemented method of claim 19 wherein the instruction employs another implicit register to locate a parameter block in memory used by the instruction, the parameter block including information used by the instruction depending on the function to be performed.