HK1170042B - Selectively enabling a host transfer interrupt - Google Patents

Description

Selectively enabling host delivery interrupts

Technical Field

Background

The non-volatile media storage system may receive many simultaneous commands from the host. In a particular host transfer protocol, a command with a unique command identification tag is sent to the media storage system. When a storage system receives a command from a host, the storage system typically allocates resources and signals the host to perform host transfers. After the host transfer is complete, the host transfer hardware of the storage system initiates an interrupt to the storage system controller that deallocates or frees resources and determines whether a new host transfer can begin. The processing of the interrupt may delay the controller in the storage system controller from performing other processing.

Disclosure of Invention

Drawings

Systems and methods that implement the various features of the present invention will now be described with reference to the drawings, in which:

fig. 1 shows a system overview of an embodiment of the invention.

FIG. 2 illustrates a flow diagram indicating operation of a storage controller in communication with transfer hardware according to one embodiment.

FIG. 3 illustrates a flow diagram indicating operation of a storage controller in communication with delivery hardware with reduced controller interrupts, according to one embodiment.

FIG. 4 shows a flow diagram depicting a process of determining whether to enable hardware delivery interrupts, according to one embodiment.

Detailed Description

While particular embodiments of the present invention have been described, these embodiments have been presented by way of example only, and are not intended to limit the scope of the invention. Indeed, the novel methods and systems described herein may be embodied in a variety of other forms. Furthermore, various omissions, substitutions and changes in the methods and systems described herein may be made without departing from the spirit of the inventions. It is intended that the appended claims and their equivalents cover such forms or modifications as would fall within the scope and spirit of the inventions.

Overview of the System

Embodiments of the present invention relate to systems and methods for reducing interrupts processed by a controller on a non-volatile storage system to improve data transfer performance of the storage system. Embodiments described herein reduce situations where an interrupt is generated when a data transfer to or from a host ("host transfer") is completed. In some embodiments, the non-volatile storage system receives a command with an identification tag from a host. In these embodiments, resources may be allocated for a predefined range of host transfers of identification tags and may be safely reused without interruption in certain situations, which reduces the need for host interrupts per host transfer.

Referring to FIG. 1, a system diagram of an embodiment of a non-volatile storage device 10 in communication with a host device 60 is shown. In the present embodiment, the nonvolatile memory device 10 includes a nonvolatile memory storage 20, a device controller 30, a command queue 50, an operation transfer storage 80, and a hardware transfer queue 90. The host device 60 includes a nonvolatile memory controller 70 in communication with the command queue 50 and the hardware transfer queue 90. The non-volatile memory storage 20 may include a solid-state memory array, a mechanically rotating magnetic disk array, a hybrid including solid-state and rotating magnetic disk arrays, or any other non-volatile memory storage type. When a host device sends a command to the nonvolatile memory device 10, the command is received in the command queue 50. In this embodiment, the interface between the host device 60 and the nonvolatile memory device 10 transmits a command including an identification tag. In certain interface standards, an identification tag may be used to allow multiple outstanding requests to be pending on a storage device. For example, the SATA interface standard may be configured for native command queuing, which allows up to 32 commands to be outstanding and enables the storage device to determine the order in which the commands are executed. Other identification tag criteria include tagged command queuing. As shown in FIG. 1, the same identification tag is associated with memory commands within the various queues shown in FIG. 1, and thus the identification tag may be used as a common reference.

In one embodiment, the command queue 50 receives commands from the nonvolatile memory controller 70. Commands may be stored in command queue 50 until processed by device controller 30. When a command is received from the command queue 50, the device controller may process the command and then prepare for host transfer. For read commands, the device controller 30 may access the non-volatile memory storage 20 before passing the read data to the host. For a write command, the device controller 30 may request a host transfer to retrieve data from the host to be written to the memory storage.

In one embodiment, the memory controller may transfer the request allocation buffer from the operation transfer memory 80 to the host. The host transfer request may then be placed in a host transfer queue 90, which may be executed by hardware to complete the host queue request to send data to or receive data from the host. If the host transfer queue is full, the device controller stores the excess host transfer requests in staging queue 40 in this embodiment.

Host transfer completion interrupt

FIG. 2 is a flow diagram illustrating a process of generating a host pass interrupt according to one embodiment. The top portion of FIG. 2 labeled 100 indicates portions of processing that may be performed on a storage device controller, such as device controller 30 depicted in FIG. 1. The bottom portion of fig. 2 labeled 110 indicates the portion of the processing that may be performed on the transfer hardware on the storage device.

At block 200, the controller receives a command ready for host transfer. At block 210, the controller checks whether the transfer queue is full and therefore unable to accept additional host transfer requests. If the host transfer queue is full, the controller may place the command in the staging queue, as indicated at block 220. The commands will remain in the staging queue until the transfer queue has an opening. Otherwise, if the transfer queue is not full, the command may be placed in the transfer queue at block 230. The transfer hardware may then perform a host transfer at block 240. After the command has been placed in the host transfer queue, the firmware in the controller may continue to complete other tasks while the host transfer is pending, including receiving and placing other commands in the transfer queue.

After the host transfer is complete, the transfer hardware generates an interrupt to indicate the completion of the transfer at block 250. When an interrupt is received, the controller 100 performs a context switch to resolve the interrupt at block 260. The controller 100 may perform other processing, such as memory management tasks, while the host transfer is complete. These processes are interrupted by the host passing completion of the interrupt. After the interrupt, the controller 100 releases the resources allocated to the transfer command (e.g., operates portions of buffer memory in the transfer memory) so that the resources are available for use by another transfer command at block 270. After freeing the resources, the controller 100 checks whether there are commands in the staging queue at block 280. If there are commands remaining in the staging queue, the controller may place the commands in the transfer queue by returning to block 230. If there are no commands in the staging queue, the process ends at block 290 and the controller waits for a new command before starting the process again.

Reducing host transfer interrupts

As discussed above, in the embodiment shown in FIG. 2, the delivery hardware generates an interrupt upon completion of each delivery. This creates a significant amount of time for the processor on the device controller to be interrupted from other management tasks. Embodiments of the present invention provide an alternative method of reducing the frequency of interrupts to a processor. Typically, the need to cause a processor interrupt arises from the need to free up resources allocated to the just completed pass-through command. By providing the system with sufficient buffer space in the operation transfer memory, the storage device can be configured such that the device controller does not require an interrupt when each host transfer to the controller is completed to manage the memory resources allocated to handle the host transfer. Various embodiments of the present invention take advantage of the fact that for an interface between a host and a storage device implementing a tagged command system (such as tagged command queuing or native command queuing), the maximum possible number of outstanding commands to the storage device is limited by the number of identification tags in the interface specification. Two such interfaces are serial ata (sata) and serial attached scsi (sas). Thus, providing sufficient memory resources on the storage device to fully identify the tag while providing host transfer resources may reduce the need to explicitly release these resources upon interruption. In one embodiment, specific memory resources in a buffer of the operation transfer memory are allocated to each restricted range of identification tags, and the resources are automatically re-used when a new command with the same identification tag is received. Although SATA and SAS are provided as examples, embodiments of the invention are not limited to storage devices implementing these interfaces and are generally applicable to any implementation using a tagged command system form.

To further illustrate this configuration used in various embodiments, a command with identification tag "5" that can be processed by the storage device controller is taken as an example. In this example, the memory device has assigned a buffer address for each identification tag number, and assigned a buffer address "E" for identification tag "5". In this arrangement, the device controller need not be interrupted to explicitly release the buffer address "E" when the host transfer is complete. The device controller understands that the next time a command with the same identification tag "5" is received, the previous command with the same identification tag "5" must have been completed due to the limited range of the identification tag. Thus, it is safe for the device controller to reuse the buffer address "E" for new commands, without relying on interrupts to notify it that the host transfer is complete.

Referring to FIG. 3, a flow diagram is provided that illustrates a process for reducing the number of interrupts provided to a controller, according to one embodiment. As with FIG. 2, the top portion of FIG. 3 labeled 100 indicates portions of the processing that may be performed on a storage device controller (such as device controller 30 depicted in FIG. 1). The bottom portion of fig. 3 labeled 110 indicates the portion of the processing that may be performed on the transfer hardware on the storage device. In the embodiment shown in FIG. 3, after placing the command in the transfer queue at block 330, the controller determines whether to enable interrupts at block 340. The decision whether to enable interrupts is discussed in further detail below with reference to FIG. 4. As described further below, enabling or disabling an interrupt refers to whether the controller is responsive to passing a hardware generated interrupt. In the present embodiment, whether the controller 100 responds to interrupts generated by the delivery hardware 110 is controlled by masking or unmasking the interrupt bit(s) from the delivery hardware 110.

If the controller determines that an interrupt is necessary at block 340, the controller does not mask the interrupt bit(s) at block 350, and the controller sets an "unmasked" state for a mask state check at block 370. If it is determined at block 340 that no interrupts are needed, the interrupt bit(s) are masked at block 360 and a "masked" state is set for a mask state check at block 370. If the interrupt bit(s) are masked, the controller continues with other tasks and is not interrupted when the delivery hardware generates an interrupt. For example, after masking the interrupt bit(s) at block 360, the controller may then check whether there are any commands in the staging queue at block 400. In another embodiment, the bits may be masked/unmasked to indicate enable/disable according to different logic. In other further embodiments, the bits are not masked, the controller may instead use other mechanisms (e.g., setting a particular value in hardware or memory) to indicate that interrupts are enabled or disabled.

In this embodiment, when the transfer hardware 110 performs a host transfer at block 420, the transfer hardware 110 proceeds to generate an interrupt 430 as in FIG. 2. The interrupt now passes the mask status check at block 370 before the controller responds to the interrupt. If at the mask status check 370 it is determined that the interrupt bit(s) associated with the interrupt have been masked, then the controller takes no further action (as shown at block 410) and the controller continues with other processing. If the mask status check determines that the generated interrupt is associated with unmasked interrupt bit(s) at block 370, the interrupt is processed by the controller. The controller then generates a context switch at block 380 in one embodiment and proceeds to blocks 390 and 400 as described above with respect to fig. 2.

In other embodiments, a number of alternative configurations may be used to reduce the number of hardware interrupts handled by the controller 100. Although the embodiment of FIG. 3 shows interrupts always being generated by the pass hardware and selectively handled by the controller, other embodiments may allow the controller to stop generating interrupts on the pass hardware side. In some implementations, hardware interrupts may be enabled or disabled on an individual host transfer basis, but in other implementations, hardware interrupts may be enabled or disabled on a batch of host transfers. Those skilled in the art will appreciate that other methods of selectively enabling hardware interrupts may be used in accordance with the general configuration described herein to reduce controller interrupts when host transfers are complete.

In one embodiment, resources may have to be established for each identification tag before the command shown in FIG. 3 is processed. This may be accomplished, for example, by allocating a particular memory resource (e.g., in a buffer of the operation transfer memory) for each identification tag at device power-up. For example, each identification tag may be provided with a dedicated portion of the buffer memory. Alternatively, the controller may be configured to alternate between modes of operation with and without implementing the selective interrupt scheme. The selective interruption scheme may be activated after the total interruption scheme has allocated resources for each identification tag.

Conditions for inhibiting host transfer interrupts

FIG. 4 is a flow diagram that illustrates a process that depicts determining whether to enable host delivery of interrupts based on certain conditions, according to an embodiment. This process may be performed, for example, as part of the determination made in block 340 of fig. 3. As shown in the embodiment of FIG. 4, a new command is received by the process, which determines whether to enable the host to pass interrupts, at block 500. At block 510, a determination is made whether the host transfer is associated with a read command. In one embodiment, a host transfer interrupt may be unnecessary for a read command because data previously read from the media is transferred to the host when the read command host transfer is performed. Upon completion of the transfer, the controller requires no further action to complete the read command. Conversely, for write commands, in certain embodiments, the host passes the data that the host has requested to be collected from the host for writing to the media storage. The controller requires additional action to effect storage of the data after it is received. The host transfer complete interrupt may trigger a write command data transfer to the storage medium. Thus, if the command is not a read command, the host transfer interrupt is enabled at block 540. If the host transfer command is a read command, processing proceeds to block 520.

At block 520, the process in one embodiment determines whether the read command is an oversized read command. In an example embodiment, a read command that is larger than the amount of data that can be transferred in a single host transfer request is considered an oversized read command. For such an oversized read command, the controller may need to be interrupted when the host transfer is complete to generate another host transfer that includes the remaining read data. Thus, for an oversized read command, the host transfer interrupt may be enabled at block 540. For a normal size read command, processing continues to block 530.

At block 530, the process determines whether the addition of this command will fill the host transfer queue in one embodiment. If the host transfer queue is to be full, no additional transfers may be added to the queue after the current command is added. Thus, additional transfers may be stored on the controller waiting in the staging queue for slots in the host transfer queue. An interrupt may be generated in this case to signal to the controller that a slot becomes available when the host transfer is complete. According to this embodiment, the host transfer interrupt may be enabled at block 540 when the host transfer queue will become full after adding the incoming command. When the host transfer queue will not become full by adding an incoming command, host transfer interrupts will be disabled, as indicated at block 550.

The conditions shown in fig. 4 may be varied in other embodiments of the invention depending on the implementation details of the controller and the interface utilized. As an example, a particular data transfer interface may not allow the use of an oversized read command, in which case checking for the oversized command would not be necessary and the controller would disable interrupts for all read commands if certain other conditions are met. In other implementations, the write command host transfer may not require an interrupt (and thus be disabled) if the write data is transferred directly to the media without any necessary controller action. As a further example, the host transfer queue may be of sufficient depth that staging the queue is unnecessary or otherwise unable to become unable to accept additional requests. In this case, the check performed in block 530 is not required. Thus, in various embodiments, the types of checks performed in the determination process of FIG. 4 may be performed differently and/or in a different order than that depicted.

Conclusion

The features and attributes of the specific embodiments disclosed above can be combined in different ways to form additional embodiments, all of which fall within the scope of the present disclosure. While the present disclosure provides specific embodiments and applications, other embodiments will be apparent to those skilled in the art, including embodiments that do not provide all of the features and advantages set forth herein, and which are within the scope of the present disclosure. Accordingly, the scope of the present disclosure is intended to be defined only by reference to the appended claims.

Claims (18)

1. A non-volatile storage system capable of reducing interrupt overhead, the non-volatile storage system comprising:

an interface configured to receive commands from a host device, the commands including identification tags selected from a finite set of identification tags, each identification tag unique to an outstanding command, the interface additionally configured to schedule host data transfers using a host communication thread configured to generate an interrupt upon completion of a host transfer; and

a processor configured to:

managing communication with the host device through the interface,

determining whether to place the command in a first queue to be executed based on an available capacity of the first queue,

placing the command in a second queue if it is determined that the first queue is full, an

After placing the command in the first queue, selectively inhibiting generation of an interrupt by the interface upon completion of a host transfer, the interrupt indicating completion of a data transfer to or from the host device, the selectively inhibiting at least partially based on one of a command type, availability of interface resources to accept additional host transfers, and a command size, thereby the selectively inhibiting reducing overhead associated with executing the command.

2. The non-volatile storage system of claim 1, wherein the processor selectively inhibits interrupts from being generated for read commands.

3. The non-volatile storage system of claim 1, wherein the non-volatile storage system comprises a solid-state non-volatile memory array.

4. The non-volatile storage system of claim 1, wherein the identification tag comprises one of a tagged command queuing tag and a native command queuing tag.

5. The non-volatile storage system of claim 1, wherein the interface communicates with the host device using a serial ATA (SATA) interface.

6. The non-volatile storage system of claim 1, wherein the interface communicates with the host device using a serial attached SCSI interface (SAS) interface.

7. The non-volatile storage system of claim 1, wherein the identification tag is assigned by a particular protocol.

8. The non-volatile storage system of claim 1, wherein the processor is further configured to respond to the interrupt by freeing resources allocated to commands for host data transfer completion.

9. The non-volatile storage system of claim 8, wherein the processor is further configured to reuse resources allocated to the command when the interrupt is selectively disabled.

10. The non-volatile storage system of claim 9, wherein the resource is reused by another command that includes an identification tag that is the same as an identification tag included by the command, the other command being stored in the second queue and passed to the first queue after the release.

11. The non-volatile storage system of claim 1, wherein the interface generated interrupt is configurably generated upon completion of each host transfer.

12. The non-volatile storage system of claim 1, wherein the interface generated interrupt is configurably generated upon completion of a batch of host transfers.

13. A method of host transfer request processing, the method comprising:

by a non-volatile storage device in communication with a host system:

receiving a host transfer request from the host system, the host transfer request associated with identification tags selected from a finite set of identification tags, each identification tag unique to an outstanding command;

storing the host transfer request in a queue of the non-volatile storage device;

executing the host transfer request using a host interface; and

after receiving and queuing the host transfer request, determining whether to interrupt a processor of a non-volatile storage device to indicate completion of a data transfer to or from the host system upon completion of a host transfer request, the determining whether to interrupt the processor based at least in part on at least one of: the allocated resources and interface resources associated with the host transfer request accept availability of additional host transfer requests.

14. The method of host transfer request processing of claim 13, further comprising allocating resources for use of a host transfer request, the allocated resources being associated with each identification tag of the finite set of identification tags, wherein the step of allocating is performed prior to the step of receiving.

15. A method performed by a storage subsystem implementing native command queuing, the method comprising:

receiving a tagged read command from a host system and storing the tagged read command in a queue of the storage subsystem;

executing the tagged read command from the queue, wherein executing the tagged read command comprises passing data stored by the storage subsystem to the host system; and

after storing the tagged read command in the queue, determining whether to execute interrupt processing associated with the tagged read command based at least in part on whether any other commands are stored in the queue, wherein the interrupt processing indicates completion of a data transfer to or from the host system.

16. The method of claim 15, wherein the method comprises disabling the interrupt processing in response to determining that no other commands are stored in the queue, thereby avoiding overhead associated with the interrupt processing.

17. The method of claim 15, wherein the storage subsystem receives and executes the tagged read command according to a SATA interface.

18. The method of claim 15, wherein the storage subsystem receives and executes the tagged read command in accordance with a SAS interface.