HK1168672A1 - 具有與業務類別關聯的端口的多端口存儲器控制器 - Google Patents

具有與業務類別關聯的端口的多端口存儲器控制器

Info

Publication number
HK1168672A1
HK1168672A1 HK12109346.8A HK12109346A HK1168672A1 HK 1168672 A1 HK1168672 A1 HK 1168672A1 HK 12109346 A HK12109346 A HK 12109346A HK 1168672 A1 HK1168672 A1 HK 1168672A1
Authority
HK
Hong Kong
Prior art keywords
memory controller
traffic classes
ports associated
ported memory
ported
Prior art date
Application number
HK12109346.8A
Other languages
English (en)
Inventor
Sukalpa Biswas
Hao Chen
Ruchi Wadhawan
Original Assignee
Apple Inc
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Priority claimed from US12/883,878 external-priority patent/US8631213B2/en
Priority claimed from US12/883,864 external-priority patent/US8314807B2/en
Priority claimed from US12/883,888 external-priority patent/US8510521B2/en
Priority claimed from US12/883,848 external-priority patent/US20120072677A1/en
Application filed by Apple Inc filed Critical Apple Inc
Publication of HK1168672A1 publication Critical patent/HK1168672A1/zh

Links

Classifications

    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F13/00—Interconnection of, or transfer of information or other signals between, memories, input/output devices or central processing units
    • G06F13/14—Handling requests for interconnection or transfer
    • G06F13/16—Handling requests for interconnection or transfer for access to memory bus
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F13/00—Interconnection of, or transfer of information or other signals between, memories, input/output devices or central processing units
    • G06F13/14—Handling requests for interconnection or transfer
    • G06F13/16—Handling requests for interconnection or transfer for access to memory bus
    • G06F13/1605—Handling requests for interconnection or transfer for access to memory bus based on arbitration
    • G06F13/1642—Handling requests for interconnection or transfer for access to memory bus based on arbitration with request queuing
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F13/00—Interconnection of, or transfer of information or other signals between, memories, input/output devices or central processing units
    • G06F13/14—Handling requests for interconnection or transfer
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F13/00—Interconnection of, or transfer of information or other signals between, memories, input/output devices or central processing units
    • G06F13/14—Handling requests for interconnection or transfer
    • G06F13/16—Handling requests for interconnection or transfer for access to memory bus
    • G06F13/1605—Handling requests for interconnection or transfer for access to memory bus based on arbitration
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F13/00—Interconnection of, or transfer of information or other signals between, memories, input/output devices or central processing units
    • G06F13/14—Handling requests for interconnection or transfer
    • G06F13/16—Handling requests for interconnection or transfer for access to memory bus
    • G06F13/1605—Handling requests for interconnection or transfer for access to memory bus based on arbitration
    • G06F13/161—Handling requests for interconnection or transfer for access to memory bus based on arbitration with latency improvement
    • G06F13/1626—Handling requests for interconnection or transfer for access to memory bus based on arbitration with latency improvement by reordering requests
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F13/00—Interconnection of, or transfer of information or other signals between, memories, input/output devices or central processing units
    • G06F13/14—Handling requests for interconnection or transfer
    • G06F13/16—Handling requests for interconnection or transfer for access to memory bus
    • G06F13/1668—Details of memory controller
    • G06F13/1689—Synchronisation and timing concerns
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C7/00—Arrangements for writing information into, or reading information out from, a digital store
    • G11C7/10—Input/output [I/O] data interface arrangements, e.g. I/O data control circuits, I/O data buffers

Landscapes

  • Engineering & Computer Science (AREA)
  • Theoretical Computer Science (AREA)
  • General Engineering & Computer Science (AREA)
  • General Physics & Mathematics (AREA)
  • Physics & Mathematics (AREA)
  • Memory System (AREA)
  • Data Exchanges In Wide-Area Networks (AREA)
  • Logic Circuits (AREA)
  • Transceivers (AREA)
  • Memory System Of A Hierarchy Structure (AREA)
  • Transmitters (AREA)
  • Multi Processors (AREA)
  • Dram (AREA)
HK12109346.8A 2010-09-16 2012-09-21 具有與業務類別關聯的端口的多端口存儲器控制器 HK1168672A1 (zh)

Applications Claiming Priority (5)

Application Number Priority Date Filing Date Title
US12/883,878 US8631213B2 (en) 2010-09-16 2010-09-16 Dynamic QoS upgrading
US12/883,864 US8314807B2 (en) 2010-09-16 2010-09-16 Memory controller with QoS-aware scheduling
US12/883,888 US8510521B2 (en) 2010-09-16 2010-09-16 Reordering in the memory controller
US12/883,848 US20120072677A1 (en) 2010-09-16 2010-09-16 Multi-Ported Memory Controller with Ports Associated with Traffic Classes
PCT/US2011/049940 WO2012036905A1 (en) 2010-09-16 2011-08-31 Multi-ported memory controller with ports associated with traffic classes

Publications (1)

Publication Number Publication Date
HK1168672A1 true HK1168672A1 (zh) 2013-01-04

Family

ID=44908227

Family Applications (2)

Application Number Title Priority Date Filing Date
HK12108647.6A HK1168159A1 (en) 2010-09-16 2012-09-04 Multi-ported memory controller with ports associated with traffic classes
HK12109346.8A HK1168672A1 (zh) 2010-09-16 2012-09-21 具有與業務類別關聯的端口的多端口存儲器控制器

Family Applications Before (1)

Application Number Title Priority Date Filing Date
HK12108647.6A HK1168159A1 (en) 2010-09-16 2012-09-04 Multi-ported memory controller with ports associated with traffic classes

Country Status (13)

Country Link
EP (1) EP2431884B1 (zh)
JP (1) JP5610636B2 (zh)
KR (1) KR101270848B1 (zh)
CN (1) CN102402490B (zh)
AU (1) AU2011302452B2 (zh)
BR (1) BR112013006329B1 (zh)
GB (1) GB2483763B (zh)
HK (2) HK1168159A1 (zh)
MX (1) MX2013002773A (zh)
NL (1) NL2007411C2 (zh)
RU (1) RU2556443C2 (zh)
TW (1) TWI465903B (zh)
WO (1) WO2012036905A1 (zh)

Families Citing this family (18)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
KR101665611B1 (ko) * 2012-05-08 2016-10-12 마벨 월드 트레이드 리미티드 컴퓨터 시스템 및 메모리 관리의 방법
CN102681946B (zh) * 2012-05-11 2015-03-11 龙芯中科技术有限公司 内存访问方法和装置
KR20160127168A (ko) * 2013-03-15 2016-11-02 인텔 코포레이션 메모리 시스템
CN104156328B (zh) * 2013-05-15 2019-02-05 中兴通讯股份有限公司 一种识别操作系统类型的方法及usb设备
KR102114453B1 (ko) * 2013-07-19 2020-06-05 삼성전자주식회사 모바일 장치 및 그것의 제어 방법
WO2015067295A1 (en) 2013-11-05 2015-05-14 Huawei Technologies Co., Ltd. Method and arrangement for controlling requests to a shared electronic resource
US9563369B2 (en) 2014-04-14 2017-02-07 Microsoft Technology Licensing, Llc Fine-grained bandwidth provisioning in a memory controller
US10163508B2 (en) 2016-02-26 2018-12-25 Intel Corporation Supporting multiple memory types in a memory slot
US10222853B2 (en) 2016-03-03 2019-03-05 Qualcomm Incorporated Power saving techniques for memory systems by consolidating data in data lanes of a memory bus
US11221971B2 (en) 2016-04-08 2022-01-11 Qualcomm Incorporated QoS-class based servicing of requests for a shared resource
US10037150B2 (en) * 2016-07-15 2018-07-31 Advanced Micro Devices, Inc. Memory controller with virtual controller mode
EP3270295A1 (en) * 2016-07-15 2018-01-17 Advanced Micro Devices, Inc. Memory controller with virtual controller mode
TWI587145B (zh) * 2016-12-08 2017-06-11 群聯電子股份有限公司 通道切換裝置、記憶體儲存裝置及通道切換方法
US11709624B2 (en) * 2018-02-15 2023-07-25 Xilinx, Inc. System-on-chip having multiple circuits and memory controller in separate and independent power domains
US11237893B2 (en) * 2019-06-26 2022-02-01 Western Digital Technologies, Inc. Use of error correction-based metric for identifying poorly performing data storage devices
CN116584075A (zh) * 2020-10-26 2023-08-11 谷歌有限责任公司 调节存储器子系统中的信用分配
CN112597080B (zh) * 2020-12-29 2022-10-21 联芸科技(杭州)股份有限公司 读请求控制装置及方法以及存储器控制器
CN115329016B (zh) * 2022-10-14 2023-04-25 深圳迅策科技有限公司 一种金融资产交易数据处理方法、系统及可读介质

Family Cites Families (19)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
IL116708A (en) * 1996-01-08 2000-12-06 Smart Link Ltd Real-time task manager for a personal computer
US6859438B2 (en) * 1998-02-03 2005-02-22 Extreme Networks, Inc. Policy based quality of service
US6101613A (en) * 1998-07-06 2000-08-08 Intel Corporation Architecture providing isochronous access to memory in a system
US6651128B1 (en) * 2000-02-10 2003-11-18 Advanced Micro Devices, Inc. Systems and methods for arbitrating between asynchronous and isochronous data for access to data transport resources
TW513635B (en) * 2000-11-24 2002-12-11 Ibm Method and structure for variable-length frame support in a shared memory switch
US7606744B1 (en) * 2001-02-16 2009-10-20 Financial Systems Technology (Intellectual Property) Pty. Ltd. System and method for real-time pricing with volume discounting
US7054968B2 (en) * 2003-09-16 2006-05-30 Denali Software, Inc. Method and apparatus for multi-port memory controller
US20050138251A1 (en) * 2003-12-18 2005-06-23 Fanning Blaise B. Arbitration of asynchronous and isochronous requests
US7500045B2 (en) * 2005-03-23 2009-03-03 Qualcomm Incorporated Minimizing memory barriers when enforcing strongly-ordered requests in a weakly-ordered processing system
JP2008541217A (ja) * 2005-05-04 2008-11-20 エヌエックスピー ビー ヴィ メモリーコントローラ、メモリーアクセスの制御方法、及びメモリーコントローラを具えたシステム
KR100784385B1 (ko) * 2005-08-10 2007-12-11 삼성전자주식회사 공유 자원에 대한 접근 요청을 중재하는 시스템 및 방법
GB2445713B (en) * 2005-12-22 2010-11-10 Advanced Risc Mach Ltd Interconnect
CN100581172C (zh) * 2006-04-19 2010-01-13 杭州华三通信技术有限公司 一种对目的磁盘进行访问的方法和扩展磁盘容量的系统
US20080077720A1 (en) * 2006-09-27 2008-03-27 Blaise Fanning Isochronous memory access with variable channel priorities and timers
CN101026556B (zh) * 2007-01-10 2010-04-21 华为技术有限公司 一种支持服务质量的仲裁方法及装置
US9292436B2 (en) * 2007-06-25 2016-03-22 Sonics, Inc. Various methods and apparatus to support transactions whose data address sequence within that transaction crosses an interleaved channel address boundary
US7908440B2 (en) * 2007-08-09 2011-03-15 Intel Corporation Simultaneous personal sensing and data storage
US8209439B2 (en) * 2008-08-25 2012-06-26 Sandisk Il Ltd. Managing multiple concurrent operations with various priority levels in a local storage device
CN101419579B (zh) * 2008-12-10 2011-11-16 中国科学院计算技术研究所 一种在动态随机存储器上提供服务质量的装置和方法

Also Published As

Publication number Publication date
JP5610636B2 (ja) 2014-10-22
KR20120029366A (ko) 2012-03-26
WO2012036905A1 (en) 2012-03-22
NL2007411A (en) 2012-03-19
GB201115481D0 (en) 2011-10-26
EP2431884B1 (en) 2015-03-11
AU2011302452A1 (en) 2013-03-28
JP2012074042A (ja) 2012-04-12
BR112013006329A2 (pt) 2016-06-21
GB2483763B (en) 2013-01-09
TW201216056A (en) 2012-04-16
MX2013002773A (es) 2013-04-05
KR101270848B1 (ko) 2013-06-05
CN102402490B (zh) 2015-12-02
BR112013006329B1 (pt) 2020-12-01
RU2013117127A (ru) 2014-10-27
HK1168159A1 (en) 2012-12-21
AU2011302452B2 (en) 2014-09-04
GB2483763A (en) 2012-03-21
TWI465903B (zh) 2014-12-21
RU2556443C2 (ru) 2015-07-10
EP2431884A1 (en) 2012-03-21
NL2007411C2 (en) 2012-05-09
CN102402490A (zh) 2012-04-04

Similar Documents

Publication Publication Date Title
GB2483763B (en) Multi-ported memory controller with ports associated with traffic classes
EP2795621A4 (en) HARD DRIVE STORAGE SYSTEM
GB2513551B (en) High-speed memory system
IL223732A (en) Memory access control
EP2727147A4 (en) MEMORY CELL STRUCTURES
EP2891183A4 (en) MEMORY MATRIX HAVING CONNECTIONS THROUGH CONTROL DOORS
EP2742416A4 (en) JOURNALIZING LIFE AND SHARING MEMORY
HUE050418T2 (hu) Több utasításfolyamot használó memóriarendszer
EP2577668A4 (en) MEMORY ARRAYS
EP2612247A4 (en) MULTILAYER OPERATION OF A NON-VOLATILE MEMORY ON A STRIP BASE
EP2425609A4 (en) SHARING IN SERVICE
EP2737524A4 (en) VERTICAL STORAGE CELL
EP2586058A4 (en) MEMORY DEVICE
GB2485780B (en) Port
EP2727114A4 (en) DECALABLE MEMORY
EP2689423A4 (en) MEMORY WITH RESISTANCE CHANGE
EP2793346A4 (en) DEVICE FOR CONTROLLING CELL CONNECTION
GB201111916D0 (en) Single poly non-volatile memory cells
EP2686882A4 (en) STORAGE CELL WITH STRUCTURE OF A CLOSED CURVE
EP2786520B8 (en) Memory
GB201015349D0 (en) Memory device
PL2560497T3 (pl) Wyrównujący obrotowy blok
EP2564578A4 (en) CONNECTION COMBINATION
EP2526477A4 (en) MEMORY CONTROL
EP2672389A4 (en) MEMORY CONTROLLER

Legal Events

Date Code Title Description
PC Patent ceased (i.e. patent has lapsed due to the failure to pay the renewal fee)

Effective date: 20210905