HK112794A - Conditional execution speed-up on synchronizing instructions - Google Patents

Conditional execution speed-up on synchronizing instructions

Info

Publication number
HK112794A
HK112794A HK112794A HK112794A HK112794A HK 112794 A HK112794 A HK 112794A HK 112794 A HK112794 A HK 112794A HK 112794 A HK112794 A HK 112794A HK 112794 A HK112794 A HK 112794A
Authority
HK
Hong Kong
Prior art keywords
execution speed
conditional execution
synchronizing instructions
synchronizing
instructions
Prior art date
Application number
HK112794A
Inventor
Beatrice P Fu
Benny Eitan
Original Assignee
Intel Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Intel Corp filed Critical Intel Corp
Publication of HK112794A publication Critical patent/HK112794A/en

Links

Classifications

    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F9/00—Arrangements for program control, e.g. control units
    • G06F9/06—Arrangements for program control, e.g. control units using stored programs, i.e. using an internal store of processing equipment to receive or retain programs
    • G06F9/30—Arrangements for executing machine instructions, e.g. instruction decode
    • G06F9/38—Concurrent instruction execution, e.g. pipeline or look ahead
    • G06F9/3877—Concurrent instruction execution, e.g. pipeline or look ahead using a slave processor, e.g. coprocessor
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F9/00—Arrangements for program control, e.g. control units
    • G06F9/06—Arrangements for program control, e.g. control units using stored programs, i.e. using an internal store of processing equipment to receive or retain programs
    • G06F9/30—Arrangements for executing machine instructions, e.g. instruction decode
    • G06F9/30003—Arrangements for executing specific machine instructions
    • G06F9/30076—Arrangements for executing specific machine instructions to perform miscellaneous control operations, e.g. NOP
    • G06F9/30087—Synchronisation or serialisation instructions

Landscapes

  • Engineering & Computer Science (AREA)
  • Software Systems (AREA)
  • Theoretical Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • General Engineering & Computer Science (AREA)
  • General Physics & Mathematics (AREA)
  • Advance Control (AREA)
  • Executing Machine-Instructions (AREA)
  • Multi Processors (AREA)
HK112794A 1989-04-07 1994-10-20 Conditional execution speed-up on synchronizing instructions HK112794A (en)

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
US33520389A 1989-04-07 1989-04-07

Publications (1)

Publication Number Publication Date
HK112794A true HK112794A (en) 1994-10-27

Family

ID=23310718

Family Applications (1)

Application Number Title Priority Date Filing Date
HK112794A HK112794A (en) 1989-04-07 1994-10-20 Conditional execution speed-up on synchronizing instructions

Country Status (5)

Country Link
JP (1) JPH02287857A (en)
DE (1) DE4010896C2 (en)
GB (1) GB2230119B (en)
HK (1) HK112794A (en)
IL (1) IL93964A (en)

Families Citing this family (6)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP4783527B2 (en) * 2001-01-31 2011-09-28 株式会社ガイア・システム・ソリューション Data processing system, data processing apparatus, and control method thereof
JP4865960B2 (en) 2001-06-25 2012-02-01 株式会社ガイア・システム・ソリューション Data processing apparatus and control method thereof
US7107478B2 (en) 2002-12-05 2006-09-12 Connex Technology, Inc. Data processing system having a Cartesian Controller
US7383421B2 (en) 2002-12-05 2008-06-03 Brightscale, Inc. Cellular engine for a data processing system
US6993674B2 (en) 2001-12-27 2006-01-31 Pacific Design, Inc. System LSI architecture and method for controlling the clock of a data processing system through the use of instructions
US9304940B2 (en) * 2013-03-15 2016-04-05 Intel Corporation Processors, methods, and systems to relax synchronization of accesses to shared memory

Family Cites Families (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS5245232A (en) * 1975-10-08 1977-04-09 Hitachi Ltd Micro program modification circuit
US4439828A (en) * 1981-07-27 1984-03-27 International Business Machines Corp. Instruction substitution mechanism in an instruction handling unit of a data processing system
US4791557A (en) * 1985-07-31 1988-12-13 Wang Laboratories, Inc. Apparatus and method for monitoring and controlling the prefetching of instructions by an information processing system
US4763294A (en) * 1985-12-19 1988-08-09 Wang Laboratories, Inc. Method and apparatus for floating point operations

Also Published As

Publication number Publication date
GB2230119B (en) 1993-04-21
DE4010896C2 (en) 1998-07-02
IL93964A (en) 1993-07-08
IL93964A0 (en) 1990-12-23
JPH02287857A (en) 1990-11-27
GB9003483D0 (en) 1990-04-11
GB2230119A (en) 1990-10-10
DE4010896A1 (en) 1990-10-11

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Legal Events

Date Code Title Description
PF Patent in force
PE Patent expired

Effective date: 20100214