HK1074501A1 - Processor cache memory as ram for execution of boot code - Google Patents

Processor cache memory as ram for execution of boot code

Info

Publication number
HK1074501A1
HK1074501A1 HK05106116A HK05106116A HK1074501A1 HK 1074501 A1 HK1074501 A1 HK 1074501A1 HK 05106116 A HK05106116 A HK 05106116A HK 05106116 A HK05106116 A HK 05106116A HK 1074501 A1 HK1074501 A1 HK 1074501A1
Authority
HK
Hong Kong
Prior art keywords
ram
execution
cache memory
boot code
processor cache
Prior art date
Application number
HK05106116A
Other languages
English (en)
Inventor
Sham Datta
Vincent Zimmer
Kushagra Vaid
William A Stevens
Amy Santoni
Original Assignee
Intel Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Intel Corp filed Critical Intel Corp
Publication of HK1074501A1 publication Critical patent/HK1074501A1/xx

Links

Classifications

    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F12/00—Accessing, addressing or allocating within memory systems or architectures
    • G06F12/02—Addressing or allocation; Relocation
    • G06F12/08—Addressing or allocation; Relocation in hierarchically structured memory systems, e.g. virtual memory systems
    • G06F12/0802—Addressing of a memory level in which the access to the desired data or data block requires associative addressing means, e.g. caches
    • G06F12/0844—Multiple simultaneous or quasi-simultaneous cache accessing
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F12/00—Accessing, addressing or allocating within memory systems or architectures
    • G06F12/02—Addressing or allocation; Relocation
    • G06F12/08—Addressing or allocation; Relocation in hierarchically structured memory systems, e.g. virtual memory systems
    • G06F12/0802—Addressing of a memory level in which the access to the desired data or data block requires associative addressing means, e.g. caches
    • G06F12/0862—Addressing of a memory level in which the access to the desired data or data block requires associative addressing means, e.g. caches with prefetch
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F12/00—Accessing, addressing or allocating within memory systems or architectures
    • G06F12/02—Addressing or allocation; Relocation
    • G06F12/08—Addressing or allocation; Relocation in hierarchically structured memory systems, e.g. virtual memory systems
    • G06F12/12—Replacement control
    • G06F12/121—Replacement control using replacement algorithms
    • G06F12/126—Replacement control using replacement algorithms with special data handling, e.g. priority of data or instructions, handling errors or pinning
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F9/00—Arrangements for program control, e.g. control units
    • G06F9/06—Arrangements for program control, e.g. control units using stored programs, i.e. using an internal store of processing equipment to receive or retain programs
    • G06F9/44—Arrangements for executing specific programs
    • G06F9/4401—Bootstrapping
    • G06F9/4403—Processor initialisation
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F2212/00—Indexing scheme relating to accessing, addressing or allocation within memory systems or architectures
    • G06F2212/25—Using a specific main memory architecture
    • G06F2212/251—Local memory within processor subsystem
    • G06F2212/2515—Local memory within processor subsystem being configurable for different purposes, e.g. as cache or non-cache memory

Landscapes

  • Engineering & Computer Science (AREA)
  • Theoretical Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • General Engineering & Computer Science (AREA)
  • General Physics & Mathematics (AREA)
  • Software Systems (AREA)
  • Computer Security & Cryptography (AREA)
  • Memory System Of A Hierarchy Structure (AREA)
  • Storage Device Security (AREA)
HK05106116A 2002-11-15 2005-07-19 Processor cache memory as ram for execution of boot code HK1074501A1 (en)

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
US10/295,406 US7254676B2 (en) 2002-11-15 2002-11-15 Processor cache memory as RAM for execution of boot code
PCT/US2003/034808 WO2004046920A2 (en) 2002-11-15 2003-10-30 Processor cache memory as ram for execution of boot code

Publications (1)

Publication Number Publication Date
HK1074501A1 true HK1074501A1 (en) 2005-11-11

Family

ID=32297190

Family Applications (1)

Application Number Title Priority Date Filing Date
HK05106116A HK1074501A1 (en) 2002-11-15 2005-07-19 Processor cache memory as ram for execution of boot code

Country Status (9)

Country Link
US (1) US7254676B2 (xx)
JP (1) JP4220469B2 (xx)
CN (1) CN1894662B (xx)
AU (1) AU2003287426A1 (xx)
DE (1) DE10393727T5 (xx)
GB (1) GB2409747B (xx)
HK (1) HK1074501A1 (xx)
TW (1) TWI242746B (xx)
WO (1) WO2004046920A2 (xx)

Families Citing this family (47)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US20040103272A1 (en) * 2002-11-27 2004-05-27 Zimmer Vincent J. Using a processor cache as RAM during platform initialization
US20040128493A1 (en) * 2002-12-27 2004-07-01 Zimmer Vincent J. Methods and apparatus for providing a firmware defined radio
US20040162978A1 (en) * 2003-02-17 2004-08-19 Reasor Jason W. Firmware developer user interface
US6880047B2 (en) * 2003-03-28 2005-04-12 Emulex Design & Manufacturing Corporation Local emulation of data RAM utilizing write-through cache hardware within a CPU module
US7058735B2 (en) * 2003-06-02 2006-06-06 Emulex Design & Manufacturing Corporation Method and apparatus for local and distributed data memory access (“DMA”) control
US7149890B2 (en) * 2003-11-21 2006-12-12 Intel Corporation Initializing system memory
TWI259358B (en) * 2004-04-16 2006-08-01 Quanta Comp Inc A system and a method for decoding port data
US8145870B2 (en) * 2004-12-07 2012-03-27 International Business Machines Corporation System, method and computer program product for application-level cache-mapping awareness and reallocation
TWI280487B (en) * 2004-12-15 2007-05-01 Via Tech Inc Power-on method for computer system with hyper-threading processor
JP4597032B2 (ja) * 2005-10-24 2010-12-15 株式会社ソニー・コンピュータエンタテインメント コンピュータシステム、それにおける基本プログラムの起動方法、及びローダプログラム
US8352718B1 (en) * 2005-11-29 2013-01-08 American Megatrends, Inc. Method, system, and computer-readable medium for expediting initialization of computing systems
CN100504779C (zh) * 2006-06-30 2009-06-24 联想(北京)有限公司 一种加速bios运行的方法
JP2008046685A (ja) * 2006-08-10 2008-02-28 Fujitsu Ltd 二重化システム及び系切り換え方法
US7673126B2 (en) * 2006-09-19 2010-03-02 Intel Corporation Methods and apparatus to self-initialize a processor
EP2078263B1 (en) * 2006-10-31 2019-06-12 Semiconductor Energy Laboratory Co, Ltd. Semiconductor device
WO2008070191A2 (en) * 2006-12-06 2008-06-12 Fusion Multisystems, Inc. (Dba Fusion-Io) Apparatus, system, and method for a reconfigurable baseboard management controller
US7627718B2 (en) 2006-12-13 2009-12-01 Intel Corporation Frozen ring cache
US7987348B2 (en) * 2007-03-30 2011-07-26 Intel Corporation Instant on video
US20080270827A1 (en) * 2007-04-26 2008-10-30 International Business Machines Corporation Recovering diagnostic data after out-of-band data capture failure
US7818560B2 (en) * 2007-09-21 2010-10-19 Intel Corporation System information synchronization in a links-based multi-processor system
US8103862B2 (en) * 2008-06-25 2012-01-24 Dell Products L.P. Self test initialization
US8296553B2 (en) * 2008-11-19 2012-10-23 Intel Corporation Method and system to enable fast platform restart
US8589629B2 (en) * 2009-03-27 2013-11-19 Advanced Micro Devices, Inc. Method for way allocation and way locking in a cache
US20110179311A1 (en) * 2009-12-31 2011-07-21 Nachimuthu Murugasamy K Injecting error and/or migrating memory in a computing system
US20110161592A1 (en) * 2009-12-31 2011-06-30 Nachimuthu Murugasamy K Dynamic system reconfiguration
CN102479094A (zh) 2010-11-30 2012-05-30 英业达股份有限公司 可携式通讯装置运作方法
WO2013095387A1 (en) 2011-12-20 2013-06-27 Intel Corporation Secure replay protected storage
US9411748B2 (en) 2011-12-20 2016-08-09 Intel Corporation Secure replay protected storage
CN104115125B (zh) 2011-12-29 2017-12-01 英特尔公司 安全的错误处理
CN103324492A (zh) * 2012-03-20 2013-09-25 鸿富锦精密工业（深圳）有限公司 基本输入输出系统固件升级方法及电子装置
US8904227B2 (en) 2012-07-30 2014-12-02 Oracle International Corporation Cache self-testing technique to reduce cache test time
US9104558B2 (en) 2013-03-28 2015-08-11 Lenovo Enterprise Solutions (Singapore) Pte. Ltd. Preventing out-of-space errors for legacy option ROM in a computing system
JP2015191606A (ja) 2014-03-28 2015-11-02 富士通株式会社 情報処理装置、情報処理装置の制御方法及び情報処理装置の制御プログラム
CN104112098B (zh) * 2014-07-17 2017-09-22 中国人民解放军国防科学技术大学 操作系统中的内核模块加载控制方法
EP3291087A1 (en) * 2016-09-01 2018-03-07 Nxp B.V. Apparatus and associated method for authenticating firmware
US10175992B2 (en) * 2016-10-01 2019-01-08 Intel Corporation Systems and methods for enhancing BIOS performance by alleviating code-size limitations
CN107832238B (zh) * 2017-10-09 2021-08-31 江苏航天龙梦信息技术有限公司 一种基于龙芯处理器平台的高速缓存作内存的方法
US11468170B2 (en) 2018-12-07 2022-10-11 Intel Corporation Techniques for processor boot-up
US11550664B2 (en) * 2019-04-08 2023-01-10 Dell Products L.P. Early boot event logging system
US11144456B2 (en) * 2019-05-24 2021-10-12 Texas Instmments Incorporated Hardware coherence signaling protocol
EP3901768A1 (en) * 2020-04-20 2021-10-27 INTEL Corporation Methods, systems, and apparatuses for a multiprocessor boot flow for a faster boot process
US11941409B2 (en) 2020-04-20 2024-03-26 Intel Corporation Methods, systems, and apparatuses for a multiprocessor boot flow for a faster boot process
US11768691B2 (en) * 2020-09-18 2023-09-26 Intel Corporation Boot process for early display initialization and visualization
US11893251B2 (en) 2021-08-31 2024-02-06 Apple Inc. Allocation of a buffer located in system memory into a cache memory
US11704245B2 (en) 2021-08-31 2023-07-18 Apple Inc. Dynamic allocation of cache memory as RAM
DE112022003363T5 (de) * 2021-08-31 2024-04-11 Apple Inc. Dynamische zuweisung von cache-speicher als ram
US11635968B2 (en) 2021-09-15 2023-04-25 International Business Machines Corporation Using idle caches as a backing store for boot code

Family Cites Families (10)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5155833A (en) * 1987-05-11 1992-10-13 At&T Bell Laboratories Multi-purpose cache memory selectively addressable either as a boot memory or as a cache memory
US5809531A (en) * 1992-09-21 1998-09-15 Intel Corporation Computer system for executing programs using an internal cache without accessing external RAM
US6044478A (en) 1997-05-30 2000-03-28 National Semiconductor Corporation Cache with finely granular locked-down regions
US6363437B1 (en) * 1999-01-07 2002-03-26 Telefonaktiebolaget Lm Ericsson (Publ) Plug and play I2C slave
US6463509B1 (en) 1999-01-26 2002-10-08 Motive Power, Inc. Preloading data in a cache memory according to user-specified preload criteria
US6606686B1 (en) * 1999-07-15 2003-08-12 Texas Instruments Incorporated Unified memory system architecture including cache and directly addressable static random access memory
EP1098249A1 (en) 1999-11-05 2001-05-09 Emc Corporation Segmenting cache to provide varying service levels
US6195749B1 (en) * 2000-02-10 2001-02-27 Advanced Micro Devices, Inc. Computer system including a memory access controller for using non-system memory storage resources during system boot time
US6842857B2 (en) * 2001-04-12 2005-01-11 International Business Machines Corporation Method and apparatus to concurrently boot multiple processors in a non-uniform-memory-access machine
US20020184352A1 (en) * 2001-05-17 2002-12-05 Sunit Jain Firmware common operations and reset environment

Also Published As

Publication number Publication date
WO2004046920A2 (en) 2004-06-03
AU2003287426A1 (en) 2004-06-15
JP4220469B2 (ja) 2009-02-04
JP2006515940A (ja) 2006-06-08
CN1894662A (zh) 2007-01-10
GB0506998D0 (en) 2005-05-11
TWI242746B (en) 2005-11-01
GB2409747B (en) 2006-09-20
DE10393727T5 (de) 2006-09-28
US20040098575A1 (en) 2004-05-20
TW200424939A (en) 2004-11-16
GB2409747A (en) 2005-07-06
WO2004046920A3 (en) 2006-04-06
CN1894662B (zh) 2010-05-26
US7254676B2 (en) 2007-08-07
AU2003287426A8 (en) 2004-06-15

Similar Documents

Publication Publication Date Title
GB2409747B (en) Processor cache memory as ram for execution of boot code
AU2003251093A8 (en) Instruction cache way prediction for jump targets
EG23964A (en) Brethable waterproof sole for shoes
HK1099493A1 (en) Footwear sole
GB2383938B (en) Shoe
GB0224941D0 (en) Controlled access to software
DE10262037B4 (de) Achsmanschette
AU152654S (en) Footwear insole
GB2389771B (en) Heel grounder
AU2003261332A8 (en) Sport boot
GB0213683D0 (en) Processor
GB0325608D0 (en) Method of determining code to download for runtime configuration
FR2838613B1 (fr) Semelage de chaussure
AU150503S (en) Shoe deodoriser
GB0223478D0 (en) Shoe
SE0203023L (sv) Zonterapeutisk inläggssula
GB2395104B (en) improvements relating to ventilated shoes
TW536948U (en) Structural design for improving shoe instep
TW509003U (en) Improved structure of boots
TW554670U (en) An improved structure of shoes
AU2003260517A8 (en) Part for footwear
TW521586U (en) Improvement of buffer structure for shoe sole
GB0224008D0 (en) Processor architectures
AU151332S (en) Shoe insole
TW567753U (en) Improved structure of shoe sole

Legal Events

Date Code Title Description
PC Patent ceased (i.e. patent has lapsed due to the failure to pay the renewal fee)

Effective date: 20101030