HK1030817A1 - Method and apparatus for controlling data transferbetween a synchronous dram-type memory and a syst em bus. - Google Patents

Method and apparatus for controlling data transferbetween a synchronous dram-type memory and a syst em bus.

Info

Publication number
HK1030817A1
HK1030817A1 HK00108255A HK00108255A HK1030817A1 HK 1030817 A1 HK1030817 A1 HK 1030817A1 HK 00108255 A HK00108255 A HK 00108255A HK 00108255 A HK00108255 A HK 00108255A HK 1030817 A1 HK1030817 A1 HK 1030817A1
Authority
HK
Hong Kong
Prior art keywords
transferbetween
syst
bus
type memory
synchronous dram
Prior art date
Application number
HK00108255A
Other languages
English (en)
Inventor
James M Dodd
Richard Malinowski
Original Assignee
Intel Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Intel Corp filed Critical Intel Corp
Publication of HK1030817A1 publication Critical patent/HK1030817A1/xx

Links

Classifications

    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F13/00—Interconnection of, or transfer of information or other signals between, memories, input/output devices or central processing units
    • G06F13/14—Handling requests for interconnection or transfer
    • G06F13/16—Handling requests for interconnection or transfer for access to memory bus
    • G06F13/1605—Handling requests for interconnection or transfer for access to memory bus based on arbitration
    • G06F13/161—Handling requests for interconnection or transfer for access to memory bus based on arbitration with latency improvement
    • G06F13/1626—Handling requests for interconnection or transfer for access to memory bus based on arbitration with latency improvement by reordering requests
    • G06F13/1631—Handling requests for interconnection or transfer for access to memory bus based on arbitration with latency improvement by reordering requests through address comparison
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F13/00—Interconnection of, or transfer of information or other signals between, memories, input/output devices or central processing units
    • G06F13/14—Handling requests for interconnection or transfer
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F1/00—Details not covered by groups G06F3/00 - G06F13/00 and G06F21/00

Landscapes

  • Engineering & Computer Science (AREA)
  • Theoretical Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • General Engineering & Computer Science (AREA)
  • General Physics & Mathematics (AREA)
  • Dram (AREA)
  • Memory System Of A Hierarchy Structure (AREA)
HK00108255A 1997-01-02 2000-12-20 Method and apparatus for controlling data transferbetween a synchronous dram-type memory and a syst em bus. HK1030817A1 (en)

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
US08/735,433 US6148380A (en) 1997-01-02 1997-01-02 Method and apparatus for controlling data transfer between a synchronous DRAM-type memory and a system bus
PCT/US1997/021589 WO1998029794A1 (en) 1997-01-02 1997-11-20 Method and apparatus for controlling data transfer between a synchronous dram-type memory and a system bus

Publications (1)

Publication Number Publication Date
HK1030817A1 true HK1030817A1 (en) 2001-05-18

Family

ID=24955784

Family Applications (1)

Application Number Title Priority Date Filing Date
HK00108255A HK1030817A1 (en) 1997-01-02 2000-12-20 Method and apparatus for controlling data transferbetween a synchronous dram-type memory and a syst em bus.

Country Status (8)

Country Link
US (1) US6148380A (xx)
EP (1) EP1012687B1 (xx)
KR (1) KR100297895B1 (xx)
AU (1) AU7892798A (xx)
DE (1) DE69732377T2 (xx)
HK (1) HK1030817A1 (xx)
TW (1) TW377419B (xx)
WO (1) WO1998029794A1 (xx)

Families Citing this family (10)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US7047391B2 (en) * 1998-09-14 2006-05-16 The Massachusetts Institute Of Technology System and method for re-ordering memory references for access to memory
US6915394B1 (en) 1999-09-29 2005-07-05 Emc Corporation Microprocessor interface
US6581137B1 (en) 1999-09-29 2003-06-17 Emc Corporation Data storage system
US6836818B1 (en) * 1999-09-29 2004-12-28 Emc Corporation Central processing unit
DE10027205A1 (de) * 2000-05-31 2002-01-03 Fujitsu Siemens Computers Gmbh Datenverarbeitungsanordnung mit einem Systembus, einem Speicherinterface, einem Speicherbus und einem Speicher, sowie ein Verfahren zu ihrem Betrieb
US6766385B2 (en) 2002-01-07 2004-07-20 Intel Corporation Device and method for maximizing performance on a memory interface with a variable number of channels
US6799257B2 (en) * 2002-02-21 2004-09-28 Intel Corporation Method and apparatus to control memory accesses
US20040176759A1 (en) * 2003-03-07 2004-09-09 Subashini Krishnamurthy Radiopaque electrical needle
US20040078558A1 (en) * 2002-03-25 2004-04-22 Sprangle Eric A. Method and apparatus to process instructions in a processor
US20040030349A1 (en) * 2002-08-08 2004-02-12 Mikhail Boukhny Liquefaction handpiece tip

Family Cites Families (14)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5530944A (en) * 1991-02-27 1996-06-25 Vlsi Technology, Inc. Intelligent programmable dram interface timing controller
US5353429A (en) * 1991-03-18 1994-10-04 Apple Computer, Inc. Cache memory systems that accesses main memory without wait states during cache misses, using a state machine and address latch in the memory controller
US5253214A (en) * 1991-09-27 1993-10-12 Eastman Kodak Company High-performance memory controller with application-programmable optimization
US5572722A (en) * 1992-05-28 1996-11-05 Texas Instruments Incorporated Time skewing arrangement for operating random access memory in synchronism with a data processor
CA2118662C (en) * 1993-03-22 1999-07-13 Paul A. Santeler Memory controller having all dram address and control signals provided synchronously from a single device
US5627985A (en) * 1994-01-04 1997-05-06 Intel Corporation Speculative and committed resource files in an out-of-order processor
US5513135A (en) * 1994-12-02 1996-04-30 International Business Machines Corporation Synchronous memory packaged in single/dual in-line memory module and method of fabrication
US5490114A (en) * 1994-12-22 1996-02-06 International Business Machines Corporation High performance extended data out
WO1996020482A1 (en) * 1994-12-23 1996-07-04 Micron Technology, Inc. Burst edo memory device
US5630096A (en) * 1995-05-10 1997-05-13 Microunity Systems Engineering, Inc. Controller for a synchronous DRAM that maximizes throughput by allowing memory requests and commands to be issued out of order
US5655105A (en) * 1995-06-30 1997-08-05 Micron Technology, Inc. Method and apparatus for multiple latency synchronous pipelined dynamic random access memory
US5603010A (en) * 1995-12-28 1997-02-11 Intel Corporation Performing speculative system memory reads prior to decoding device code
US5926828A (en) * 1996-02-09 1999-07-20 Intel Corporation Method and apparatus for controlling data transfer between a synchronous DRAM-type memory and a system bus
US5587961A (en) * 1996-02-16 1996-12-24 Micron Technology, Inc. Synchronous memory allowing early read command in write to read transitions

Also Published As

Publication number Publication date
WO1998029794A1 (en) 1998-07-09
EP1012687A4 (en) 2002-05-15
DE69732377D1 (de) 2005-03-03
US6148380A (en) 2000-11-14
TW377419B (en) 1999-12-21
EP1012687B1 (en) 2005-01-26
KR100297895B1 (ko) 2001-11-03
AU7892798A (en) 1998-07-31
EP1012687A1 (en) 2000-06-28
DE69732377T2 (de) 2005-12-22
KR20000069848A (ko) 2000-11-25

Similar Documents

Publication Publication Date Title
HK1035255A1 (en) Method and apparatus for a serial access memory.
IL138661A (en) Device, system and method for data access control
GB2331382B (en) Electronic data storage apparatus, system, and method
HUP0004750A3 (en) Method and arrangement for controlled data transfer between memory and peripheral device
GB2344670B (en) System, apparatus and method for controlling access
AU9079398A (en) Method for allocating memory in a multiprocessor data processing system
AU2618300A (en) Shared memory apparatus and method for multiprocessor systems
AU7337200A (en) Method and system for controlling data in a computer system
HUP0002656A3 (en) Method, system and device of controlling the state of a system bus
AU9604698A (en) Method and apparatus for two step memory write operations
AU1729100A (en) Method and apparatus for memory control circuit
IL147736A0 (en) Method and system for organizing data
AU9505298A (en) System and method for data bus interface
HK1031442A1 (en) Method and apparatus for switching between source-synchronous and common clock data transfer modes in a multiple agent processing system.
AU2003275241A8 (en) Method and system for using a memory card protocol inside a bus protocol
GB2357866B (en) Method, apparatus and computer software for memory management
SG70636A1 (en) Machine data acquistion system and method
GB9711716D0 (en) Data processing system using active tokens and method for controlling such a system
AU5216899A (en) Method and apparatus for stopping a bus clock while there are no activities present on a bus
GB9928964D0 (en) Method and system for optimising a data carousel
AU2391500A (en) Method and system for memory allocation in a multiprocessing environment
AU5990098A (en) Method and arrangement for setting data transfer parameters in a data transfer system
HK1030817A1 (en) Method and apparatus for controlling data transferbetween a synchronous dram-type memory and a syst em bus.
GB2326315B (en) Distributed data processing system and method for controlling such a system
EP1131940A4 (en) DATA ACCESS SYSTEM AND METHOD

Legal Events

Date Code Title Description
PC Patent ceased (i.e. patent has lapsed due to the failure to pay the renewal fee)

Effective date: 20151120