HK1022970A1 - Cache coherency protocol including a hovering (h) state having a precise mode and an imprecise mode - Google Patents

Cache coherency protocol including a hovering (h) state having a precise mode and an imprecise mode

Info

Publication number
HK1022970A1
HK1022970A1 HK00101984A HK00101984A HK1022970A1 HK 1022970 A1 HK1022970 A1 HK 1022970A1 HK 00101984 A HK00101984 A HK 00101984A HK 00101984 A HK00101984 A HK 00101984A HK 1022970 A1 HK1022970 A1 HK 1022970A1
Authority
HK
Hong Kong
Prior art keywords
mode
hovering
state
imprecise
cache coherency
Prior art date
Application number
HK00101984A
Other languages
English (en)
Inventor
Ravi Kumar Arimilli
John Steven Dodson
Jerry Don Lewis
Original Assignee
Ibm
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Ibm filed Critical Ibm
Publication of HK1022970A1 publication Critical patent/HK1022970A1/xx

Links

Classifications

    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F12/00—Accessing, addressing or allocating within memory systems or architectures
    • G06F12/02—Addressing or allocation; Relocation
    • G06F12/08—Addressing or allocation; Relocation in hierarchically structured memory systems, e.g. virtual memory systems
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F12/00—Accessing, addressing or allocating within memory systems or architectures
    • G06F12/02—Addressing or allocation; Relocation
    • G06F12/08—Addressing or allocation; Relocation in hierarchically structured memory systems, e.g. virtual memory systems
    • G06F12/0802—Addressing of a memory level in which the access to the desired data or data block requires associative addressing means, e.g. caches
    • G06F12/0806—Multiuser, multiprocessor or multiprocessing cache systems
    • G06F12/0815—Cache consistency protocols
    • G06F12/0831—Cache consistency protocols using a bus scheme, e.g. with bus monitoring or watching means
    • G06F12/0833—Cache consistency protocols using a bus scheme, e.g. with bus monitoring or watching means in combination with broadcast means (e.g. for invalidation or updating)

Landscapes

  • Engineering & Computer Science (AREA)
  • Theoretical Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • General Engineering & Computer Science (AREA)
  • General Physics & Mathematics (AREA)
  • Memory System Of A Hierarchy Structure (AREA)
HK00101984A 1998-02-17 2000-03-31 Cache coherency protocol including a hovering (h) state having a precise mode and an imprecise mode HK1022970A1 (en)

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
US09/024,612 US6263407B1 (en) 1998-02-17 1998-02-17 Cache coherency protocol including a hovering (H) state having a precise mode and an imprecise mode

Publications (1)

Publication Number Publication Date
HK1022970A1 true HK1022970A1 (en) 2000-08-25

Family

ID=21821494

Family Applications (1)

Application Number Title Priority Date Filing Date
HK00101984A HK1022970A1 (en) 1998-02-17 2000-03-31 Cache coherency protocol including a hovering (h) state having a precise mode and an imprecise mode

Country Status (10)

Country Link
US (1) US6263407B1 (ja)
EP (1) EP0936554B1 (ja)
JP (1) JP3277171B2 (ja)
KR (1) KR100330934B1 (ja)
CN (1) CN1131481C (ja)
DE (1) DE69900611T2 (ja)
HK (1) HK1022970A1 (ja)
ID (1) ID22046A (ja)
MY (1) MY122483A (ja)
TW (1) TW426824B (ja)

Families Citing this family (20)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2000330965A (ja) * 1999-03-17 2000-11-30 Hitachi Ltd マルチプロセッサシステム及びそのメモリアクセストランザクションの転送方法
US6345342B1 (en) * 1999-11-09 2002-02-05 International Business Machines Corporation Cache coherency protocol employing a read operation including a programmable flag to indicate deallocation of an intervened cache line
US6345344B1 (en) * 1999-11-09 2002-02-05 International Business Machines Corporation Cache allocation mechanism for modified-unsolicited cache state that modifies victimization priority bits
US6345343B1 (en) * 1999-11-09 2002-02-05 International Business Machines Corporation Multiprocessor system bus protocol with command and snoop responses for modified-unsolicited cache state
US6374333B1 (en) * 1999-11-09 2002-04-16 International Business Machines Corporation Cache coherency protocol in which a load instruction hint bit is employed to indicate deallocation of a modified cache line supplied by intervention
US6349369B1 (en) * 1999-11-09 2002-02-19 International Business Machines Corporation Protocol for transferring modified-unsolicited state during data intervention
US6925634B2 (en) * 2001-01-24 2005-08-02 Texas Instruments Incorporated Method for maintaining cache coherency in software in a shared memory system
US7194586B2 (en) * 2002-09-20 2007-03-20 International Business Machines Corporation Method and apparatus for implementing cache state as history of read/write shared data
US7225299B1 (en) 2003-07-16 2007-05-29 Transmeta Corporation Supporting speculative modification in a data cache
US7496715B1 (en) * 2003-07-16 2009-02-24 Unisys Corporation Programmable cache management system and method
KR100515059B1 (ko) * 2003-07-22 2005-09-14 삼성전자주식회사 멀티프로세서 시스템 및 멀티프로세서 시스템의 캐쉬일관성 유지 방법
US9727468B2 (en) 2004-09-09 2017-08-08 Intel Corporation Resolving multi-core shared cache access conflicts
US7376798B1 (en) 2005-04-07 2008-05-20 Transmeta Corporation Memory management methods and systems that support cache consistency
JP4784928B2 (ja) * 2005-08-24 2011-10-05 株式会社リコー 情報処理装置、情報処理システム、情報処理方法、及び、情報処理プログラムとその記録媒体
US8327075B2 (en) * 2005-12-08 2012-12-04 International Business Machines Corporation Methods and apparatus for handling a cache miss
US7571286B2 (en) * 2006-08-24 2009-08-04 International Business Machines Corporation Reduced memory traffic via detection and tracking of temporally silent stores
US8874855B2 (en) 2009-12-28 2014-10-28 Empire Technology Development Llc Directory-based coherence caching
CN102122256B (zh) * 2011-03-28 2013-01-09 中国人民解放军国防科学技术大学 一种用于进程间通信的管道式通信方法及系统
US20170255569A1 (en) * 2016-03-01 2017-09-07 Qualcomm Incorporated Write-allocation for a cache based on execute permissions
CN108805276B (zh) * 2017-06-16 2020-09-22 上海兆芯集成电路有限公司 处理器、用于操作处理器的方法和计算机可用介质

Family Cites Families (24)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US4755930A (en) 1985-06-27 1988-07-05 Encore Computer Corporation Hierarchical cache memory system and method
DE68917326T2 (de) 1988-01-20 1995-03-02 Advanced Micro Devices Inc Organisation eines integrierten Cachespeichers zur flexiblen Anwendung zur Unterstützung von Multiprozessor-Operationen.
JPH0680499B2 (ja) 1989-01-13 1994-10-12 インターナショナル・ビジネス・マシーンズ・コーポレーション マルチプロセッサ・システムのキャッシュ制御システムおよび方法
US5119485A (en) * 1989-05-15 1992-06-02 Motorola, Inc. Method for data bus snooping in a data processing system by selective concurrent read and invalidate cache operation
US5287484A (en) 1989-06-21 1994-02-15 Hitachi, Ltd. Multi-processor system for invalidating hierarchical cache
JPH061463B2 (ja) 1990-01-16 1994-01-05 インターナショナル・ビジネス・マシーンズ・コーポレーション マルチプロセッサ・システムおよびそのプライベート・キャッシュ制御方法
JP2820752B2 (ja) 1990-01-19 1998-11-05 日本電信電話株式会社 密結合マルチプロセッサシステムにおけるキャッシュメモリ一致制御方法
JPH0625984B2 (ja) 1990-02-20 1994-04-06 インターナシヨナル・ビジネス・マシーンズ・コーポレーシヨン マルチプロセツサ・システム
CA2051209C (en) 1990-11-30 1996-05-07 Pradeep S. Sindhu Consistency protocols for shared memory multiprocessors
US5282272A (en) 1990-12-21 1994-01-25 Intel Corporation Interrupt distribution scheme for a computer bus
EP0553743A1 (en) 1992-01-31 1993-08-04 Motorola, Inc. A cache controller
US5319766A (en) * 1992-04-24 1994-06-07 Digital Equipment Corporation Duplicate tag store for a processor having primary and backup cache memories in a multiprocessor computer system
JPH06110844A (ja) 1992-08-11 1994-04-22 Toshiba Corp 分散共有メモリ型マルチプロセッサシステム
JP3013631B2 (ja) 1992-09-28 2000-02-28 日本電気株式会社 キャッシュメモリ同期方法
US5522057A (en) 1993-10-25 1996-05-28 Intel Corporation Hybrid write back/write through cache having a streamlined four state cache coherency protocol for uniprocessor computer systems
US5671391A (en) 1994-01-10 1997-09-23 Ncr Corporation Coherent copyback protocol for multi-level cache memory systems
US5588131A (en) 1994-03-09 1996-12-24 Sun Microsystems, Inc. System and method for a snooping and snarfing cache in a multiprocessor computer system
US5666509A (en) 1994-03-24 1997-09-09 Motorola, Inc. Data processing system for performing either a precise memory access or an imprecise memory access based upon a logical address value and method thereof
EP0681240B1 (en) 1994-05-03 2001-01-10 Hewlett-Packard Company Duplicate cache tag memory system
CA2148186A1 (en) 1994-05-04 1995-11-05 Michael T. Jackson Processor board having a second level writeback cache system and a third level writethrough cache system which stores exclusive state information for use in a multiprocessor computer system
US5551001A (en) * 1994-06-29 1996-08-27 Exponential Technology, Inc. Master-slave cache system for instruction and data cache memories
US6038644A (en) 1996-03-19 2000-03-14 Hitachi, Ltd. Multiprocessor system with partial broadcast capability of a cache coherent processing request
US5900016A (en) 1997-04-02 1999-05-04 Opti Inc. System for using a cache memory with a write-back architecture
US6049849A (en) * 1997-04-14 2000-04-11 International Business Machines Corporation Imprecise method and system for selecting an alternative cache entry for replacement in response to a conflict between cache operation requests

Also Published As

Publication number Publication date
US6263407B1 (en) 2001-07-17
EP0936554B1 (en) 2001-12-19
CN1231444A (zh) 1999-10-13
JP3277171B2 (ja) 2002-04-22
DE69900611T2 (de) 2002-08-22
JPH11328025A (ja) 1999-11-30
CN1131481C (zh) 2003-12-17
EP0936554A3 (en) 2000-01-26
EP0936554A2 (en) 1999-08-18
DE69900611D1 (de) 2002-01-31
ID22046A (id) 1999-08-26
MY122483A (en) 2006-04-29
KR19990072595A (ko) 1999-09-27
KR100330934B1 (ko) 2002-04-01
TW426824B (en) 2001-03-21

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Legal Events

Date Code Title Description
PF Patent in force
PC Patent ceased (i.e. patent has lapsed due to the failure to pay the renewal fee)

Effective date: 20100115