HK1018564B - Inverse transport processor with memory address circuitry - Google Patents

Description

Reverse transport processor with memory address circuitry

The invention relates to an apparatus for processing program component data packets from a packetized video signal and extracting corresponding significant portions of different program signal components. It includes means for addressing the transfer buffer and the concept of using a common transfer buffer.

It is known, for example from us 5,168,356 and us 5,289,276, that it is advantageous to provide error protection/correction measures for individual packets to transmit the compressed video signal in the packets. The system of the above-mentioned patent transmits and processes a single television program from each transmission channel even if there are multiple program components. These systems employ an inverse transport processor to extract the video signal components of each program for further processing to condition the video components for playback. Patent No. 5,289,276 discusses only the process of processing video signal components. The' 5,168,356 patent describes an inverse transport processor that uses a simple demultiplexer to separate other program components based on packet header data to identify individual signal components. The separated video signal components are supplied to a buffer memory, while the remaining signal components are supplied directly to their respective processing circuits.

It is known from us patent No. 5,233,654 to transmit codes with a television signal in order to provide interactive programming. This code typically operates on or is executed by a computer associated with the television receiver.

In applications where most of the program components are compressed, some buffering is required between the transmission channel and most of the corresponding component processing (decompression) means, thus requiring most, if not all, of the components to be sent to the buffer memory. The data rates of the different program components may vary greatly from component to component and from component to component. It is therefore preferable to buffer each component separately. In summary, buffering memory is not meaningless for buffering compressed program component data and processing interactive programs. In fact, it can affect the cost of the receiver system.

If the back transport processor is present in a box, for example, in the upper part of the device, the size of the memory and the management circuitry will be kept to a minimum, so that the costs for the consumer are as low as possible. It is therefore economically desirable to employ the same memory and memory management circuitry for program component buffering, processor housekeeping, and interworking functions.

The present invention is a reverse transport processor system for a receiver of TDM packet signals. The system includes means for selectively extracting desired significant portions of the program component data and passing the data to the general purpose buffer memory data input. A microprocessor generates data which is also applied to the general purpose buffer memory data input ports. The respective component valid portions and microprocessor-generated data are stored in respective blocks of the general purpose buffer memory in accordance with associated memory addresses applied to the memory address input ports by the address multiplexer selector.

In a particular embodiment, the active portions of the program packets for each program component are multiplexed to the memory data input port and directly to the selected region of the Random Access Memory (RAM) according to a plurality of start and end pointers. The start and end pointers are stored in a first plurality of registers, one for each program component. Addresses are generated in portions by a plurality of read pointer registers that are multiplexed by successively adding 1 to the pointers of the respective program components using an adder. The start pointers are associated with read pointers to memory addresses that are scrolled from the indicated memory blocks selectively assigned to the respective program components.

In a second embodiment, a decryption means is included for decrypting the valid portion of data based on a packet-specific decryption key.

In a third embodiment, a detector is included for detecting valid portions including naming data. The valid part, which contains the naming data, goes directly via the universal buffer memory to a smart card (smart card) which generates the packet-specific decryption key.

The data output from the memory is supplied to a bus interconnecting the individual program component processors. Memory access is arbitrary for read and write functions, based on data requests from individual program component processors and data write requests from component valid portion sources, so that incoming program data is not lost and all component processors are operational.

The present invention will be described with reference to the accompanying drawings. In the drawings:

figure 1 is a diagrammatic representation of a time division multiplexed switch selected packet television signal.

Fig. 2 is a diagram illustrating individual signal packets.

Fig. 3 is a block diagram of a receiver for selecting and processing a multiplexed component signal packet embodying the present invention.

FIG. 4 is a block diagram of an exemplary memory management circuit that may implement element 17 of FIG. 3.

Fig. 5 is a diagram illustrating the configuration of the memory address of the service channel data.

Fig. 6 is a diagram illustrating a structure of a memory address of the supplementary packet data.

FIG. 7 is a block diagram illustrating circuitry to generate a secondary packet memory address.

FIG. 8 is a block diagram of another register circuit for incrementing a memory address.

FIG. 9 is a flow chart of the operation of the memory address control.

Fig. 10 is a block diagram of a conditional access filter/start code detector.

Fig. 1 shows a signal stream consisting of a series of blocks representing signal packets, which are components of a plurality of different television or interactive television programs. It is assumed that these program components are composed of compressed data, and thus the amount of video data of each image is variable. The length of the pack is fixed. The packets with subscripted letters represent the components of a single program. For example, Vi, Ai, Di represent video, audio, and data packets, packets represented by V1, a1, D1 represent video, audio, and data components of program 1, and V3, a31, a32, D3 represent video, audio 1, audio 2, and data components of program 3. The data packets Di may comprise, for example, control data for initiating an action in the receiver, or they may comprise executable code constituting an application program for execution by, for example, a microprocessor located in or associated with the receiver.

In the above row of packet strings, the components of a particular program are grouped together. However, it is not necessary to group packets of the same program as represented by the entire packet string. The order of occurrence of the various components need not be in any particular order.

As shown in fig. 2, the structure of each packet includes a prefix and a valid portion. The prefix of this example comprises two 8-bit bytes, consisting of five fields, four of which (P, BB, CF, CS) are 1-bit fields and the other (SCID) is a 12-bit field. The SCID field is a signal component identifier. The field CF includes a flag indicating whether the valid portion of the packet is encrypted, and the field CS includes a flag indicating which of two alternate decryption keys is used to decrypt the encrypted packet. The prefix of each packet is packet aligned so that the location of the respective fields can be easily identified.

Header in each active part, the header includes a continuity count, CC, modulo 16, and a TOGGLE flag bit indicating a particular program component. The continuous counting is simply to count the continuous packets of the same program component continuously. The TOGGLE flag bit is a one bit signal that, for a video component, changes the logic level or trigger in the packet that determines the start of a new picture (frame), i.e., the packet that includes a picture layer header.

Fig. 3 illustrates, in block diagram form, a portion of a digital television signal receiver including an inverse transport processor assembly. The signal is detected by an antenna 10 and applied to a tuning detector 11 which takes the received signal in a particular frequency band and provides a baseband compressed signal in binary format. The frequency bands are selected by the user in a conventional manner by means of the microprocessor 19. Nominally, the broadcast digital signal will be error coded, for example using Reed-Solomon Forward Error Correction (FEC) coding. So that the baseband signal will be sent to the FEC decoder 12. The FEC decoder 12 synchronizes the received video signal and provides a stream of signal packets of the type shown in figure 1. The FEC12 may provide packets at regular intervals or as needed, for example, by the memory controller 17. In either case of the packet framing or synchronization signal being provided by the FEC circuit, the signal indicates the time at which the corresponding packet information is transmitted from the FEC 12.

The detected frequency band may comprise a plurality of time-multiplexed programs in the form of packets. To be useful, only packets from a single program should enter other circuit components. In this example, it is assumed that the user does not know which package to select. This information is included in the program guide, which is itself a program comprising data that will relate the program signal components through the SCID to each other, and may include information relating to, for example, subscriber naming. The program guide is a list of the SCIDs of each program for the audio, video, and data components of the respective program. The program guide (package D4 in fig. 1) is assigned a fixed SCID. When the receiver is powered on, the microprocessor 19 is programmed to load the SCID associated with the program guide into one of a set of similarly programmable SCID registers 13. The SCID field of the prefix portion of each detected signal packet from FEC12 is successively loaded into another SCID register 14. The programmable register and the receive SCID register are connected to respective inputs of a comparator circuit 15 and the received SCID is compared with the program guide SCID. If the SCID of a packet matches the program guide SCID, the comparator 15 causes the memory controller 17 to satisfy the condition and to place that packet into a predetermined location in memory 18 for use by the microprocessor. If the received SCID does not coincide with the program guide SCID, the corresponding packet is simply dropped.

The microprocessor waits for programming commands issued by the user via the interface 20, which interface 20 is shown as a computer keyboard, but could also be a conventional remote control and receiver front panel switch. The user may request to see the program provided on channel 4 (in the native language of the analog television system). Microprocessor 19 is programmed to scan the program guide directory of the individual SCIDs of the channel 4 program components loaded into memory 18 and load these SCIDs into the respective other ones of the programmable registers of the memory location of register 13, register 13 being associated with the corresponding component signal processing path.

The received audio, video or data program component packets of the desired program must ultimately be passed to respective audio 23, video 22 and ancillary data 21(24) signal processors. Data is received at a relatively constant rate, but the signal processor nominally needs to input data in bursts (e.g., of various types depending on decompression). The exemplary system of fig. 3 first routes each packet to a predetermined location in memory 18. The respective processors 21-24 then request the component packets from the memory 18. Routing the components through the memory provides a means of buffering or adjusting the required signal data rate.

The audio, video and data packets are packed into respective predetermined memory locations so that the buffered signal processor has access to the component data. To fit the valid portion of each component packet into the appropriate memory areas, corresponding SCID comparators are associated with these memory areas. This association may be implemented in the memory controller 17 by hard wiring, or the association may be programmable. If the former, then specific ones of the programmable registers 13 are always allocated to audio, video and data SCIDs, respectively. If the latter, the audio, video and data SCIDs can be loaded into any of the programmable registers 13 and the appropriate associations will be programmed in the memory controller 17 when the respective SCIDs are loaded into the programmable registers.

In the steady state, after the program SCIDs have been stored in programmable register 13, the SCIDs of the received signal packets are compared to all SCIDs in the programmable SCID register. If any of the stored audio, video or data SCIDs are consistent, the corresponding packet valid portion will be stored in the audio, video or data memory area or block, respectively.

Each signal packet is sent from FEC12 to memory controller 17 via signal decryptor 16. Only the active part of the signal is encrypted and the header of the packet is passed unchanged by the decryptor. Whether a packet is decrypted is determined by the CF tag in the packet prefix, and how it is decrypted is determined by the CS tag. If the SCIDs of a corresponding packet do not match, the decryptor may simply be disabled from passing any data. In addition, if the SCIDs of a packet do not match, the decryptor may be allowed to decrypt according to its last setting, and memory write control may be disabled to roll out the corresponding packet.

The decryptor is programmed with a decryption key provided by the smart card device 31. The smart card generates the appropriate decryption key in response to naming information included in a particular program guide package. The system of the example comprises two levels of encryption or program access, naming control messages ECM and naming management messages EMM. Program naming control and management information is regularly transmitted in packets that are identified by specific SCIDs included in the packet information stream containing the program guide. The smart card uses the ECM information included in these packets to generate a decryption key for use by the decryptor. The EMM information included in these packets is used by the user-specific smart card to determine the program content to which the user is entitled. The EMM naming information in these packets may be region-specific, or group-specific or user-specific. For example, the system may include a modem (not shown) that communicates billing information from the smart card to a program provider, such as a satellite broadcaster. The smart card can be programmed with an area code such as the location of the receiver and a telephone exchange. The EMM may include data that, when processed by the smart card, may name or deny receipt of a particular program with a particular region code.

The provider of the program may want to delete a particular area or group with a very short boot time. For example, if the ticket for a football game is not sold, the broadcaster may be required to delete the football game in a local area of the stadium. This information is not available until the game is close. With such a short boot time it is not possible to program EMMs such that local areas are deleted. Another type of encoding of naming information is included in the active part of the naming data to allow for immediate deletion.

A packet containing naming data includes a 128-bit valid portion header arranged in 4 groups (32 bits per group) of specialized codes. The matched filter or E-code decoder 30 detects a certain bit pattern in the 128-bit header. If a match is detected, the decoder communicates with the memory controller 17 and the smart card 31 to make the remainder of the nominated valid portion available to the smart card (via the memory 18). If no match is detected, the dedicated receiver does not receive the valid portion. If the matched filter 30 is made programmable, the unique code may be changed periodically. These codes may be provided periodically by the smart card. For more specific details of smart card operation in relation TO viewer naming, the reader is referred TO the satellite book section 25 "full oriented satellite Television THEORY and practice" ("A COMPLETE GUIDE TO SATELLITE TELETV THERY AND PRACTICE") Swift Television Publications, 17Pittsfield, Cricklade, Wilts, Engtand.

A matched filter or E-code decoder is used to perform the second function, namely to detect a particular MPEG video header. The length of these headers or start codes is 32 bits (this is why the header naming the active part is encoded in 32 bits). If video data is lost, the MPEG video decoder may simply resume decompressing the video data at a particular data entry point. These entry points are matched to the start code of the MPEG. The decoder may be arranged to communicate with the memory controller 17 to inhibit the video data stream from entering the memory after a video packet is lost and to resume writing the video active portion to the memory only after the decoder 30 detects the next MPEG start code.

Fig. 4 illustrates an exemplary arrangement of the memory controller 17 shown in fig. 3. Each program component is stored in a different contiguous block of memory 18. Still other data, such as data generated by the microprocessor 19 or by a smart card (not shown) may also be stored in the memory 18.

Addresses are applied to the memory 18 through the multiplexer 105 and input data are applied to the memory 18 through the multiplexer 99. The output data of the memory management circuit is supplied to the signal processor through another multiplexer 104. The multiplexer 104 provides output data from the microprocessor 19, the memory 18 or directly from the multiplexer 99. Program data is assumed to have a standard image resolution and quality and to appear at a particular data rate. On the other hand, the high definition television signal HDTV that can be provided by this receiver occurs at a rate that is much higher than the data rate. With the exception of the higher rate HDTV signals that can directly select a path from the multiplexer 99 to the multiplexer 104, virtually all of the data provided by the FEC will be routed through the memory 18 via the multiplexer 99 and the memory I/O circuit 102. Data is provided to the multiplexer 99 from the source of the decryptor 16, the smart card circuitry, the microprocessor 19 and the media error code 100. The term "media error code" as used herein refers to a specific code word inserted into the data stream, providing that the respective signal processor (decompressor) suspends processing until a predetermined code word, such as a start code, is detected, and then resumes processing based on, for example, the start code.

The memory addresses are provided to the multiplexer 105 from the program addressing circuits 79-97, the microprocessor 19, the smart card device 31 and the auxiliary packet address counter 78. The selection of a particular address at any particular time is controlled by the direct memory access DMA circuit 98. The SCID control signal from comparator 15 and the "data required" signal from the respective signal processor are applied to DMA98, in response to which memory access contention information is arbitrary. The DMA98, in conjunction with the service pointer controller 93, provides the appropriate read or write address for each program signal component.

The respective addresses of the different signal component memory blocks are generated by four sets of program component or service pointer registers 83, 87, 88 and 92. The start pointer of the respective block of memory in which the respective signal component is stored is included in the register 87 for the respective signal component. The start pointers may be fixed values or they may be calculated in the microprocessor 19 using conventional memory management methods.

The last address pointer of the respective block is stored in the service register set 88, one for each possible program component. Similar to the start address, the end address may be a fixed value or calculated by the microprocessor 19. The use of the calculated values of the start and end pointers is better because it provides a more general system with less memory.

A memory write pointer or head pointer is generated by adder 80 and service head register 83. There is one header register for each possible program component. The write or head pointer value is stored in register 83 and is provided to address multiplexer 105 during a write cycle of the memory. The head pointer is also connected to an adder 80, wherein the head pointer is incremented by one unit and for the next write cycle the incremented pointer is stored in the appropriate register 83. Register 83 is selected by service pointer controller 93 for the appropriate program component currently being used.

In this example, it is assumed that the start and end pointers are 16-bit pointers. Register 83 provides a 16-bit write or head pointer. The 16-bit pointer is selected to facilitate loading of the start and end pointers in registers 87 and 88 using a 16-bit or 8-bit bus. On the other hand, the memory 18 has an address of 18 bits. The 18-bit write address is formed by concatenating the two most significant bits of the start pointer of the 16-bit head pointer with the start pointer bit in the position of the most significant bits of the combined 18-bit write address. The start pointer is provided to the service pointer controller 93 through respective registers 87. The service pointer controller parses the more significant start pointer bits from the start pointer stored in register 87 and associates these bits with the 16-bit head pointer bus. This is represented by a bus 96 which is shown in conjunction with a head pointer bus exiting the multiplexer 85, see bold arrows in fig. 5.

In fig. 5, the boxes in the upper, middle and lower three rows represent the bits of a start pointer, an address and a head or tail pointer, respectively. The larger number of blocks indicates the position of the more significant bit. The arrows indicate from which start pointer bit position or head/tail pointer bit position the respective address bits of the address come. In this relationship, the solid arrows indicate steady state operation.

Similarly, a memory read pointer or tail pointer is generated by adder 79 and service tail register 92. There is one end-of-service register for each possible program component. The read or tail pointer value is stored in register 92 and provided to address multiplexer 105 during a read cycle of the memory. The tail pointer is also coupled to adder 79, where the tail pointer is incremented by one unit and the incremented pointer is stored in the appropriate register 92 in the next read cycle. The register 92 is selected by the service pointer controller 93 for the appropriate program component currently being used.

Register 92 provides a 16-bit tail pointer. The 18-bit read address is formed by concatenating the two most significant bits of the start pointer of the 16-bit tail pointer with the start pointer bit in the position of the most significant bits of the combined 18-bit write address. The service pointer controller parses the more significant start pointer bits from the start pointer stored in register 87 and associates these bits with the 16-bit tail pointer bus. This is represented by bus 94, which is coupled to the tail pointer bus exiting the multiplexer selector 90.

The data is stored in the memory 18 at the calculated address. After storing one byte of data, the head pointer is incremented by 1 and compared with the tail pointer of this program component, and if they are equal, the more significant bit of the head pointer is replaced with the lower 14 bits of the start pointer and 0 is placed in the lower two bits of the head pointer portion of the address. This is indicated in fig. 5 by the shaded arrow between the start pointer and the address. This operation is represented by arrow 97 from the service pointer controller 93 to the head pointer bus from the multiplexer 85. Assume that the lower 14 applications of the start pointer positions exceed the head pointer positions. For this write cycle, replacing the head pointer bits with the lower start pointer bits in the address allows the memory to be rolled up from the memory block specified by the upper two start bits, thus avoiding reprogramming the write address into the unique memory locations in the block at the beginning of each packet.

If the head pointer was equal to the tail pointer (indicating where data was read from memory 18), a signal is sent to the interrupt segment of the microprocessor indicating that a head-to-tail collision occurred. And further inhibits writing from the program channel to memory 18 until the microprocessor re-enables the channel. This is rare and should not occur during normal operation.

Data is retrieved from the memory 18 at addresses calculated by the adder 79 and the register 92 according to the requests of the respective signal processors. After reading out a byte of stored data, the tail pointer is incremented by one unit and compared with the end pointer of this logical channel in the service pointer controller 93. If the tail pointer and the end pointer are equal, the more significant bit of the tail pointer is replaced with the lower 14 bits of the start pointer and 0 is placed in the lower two bit position of the tail pointer portion of the address. This is represented by arrow 95 from the controller 93 and pointing to the tail pointer bus from the multiplexer selector 90. If now the tail pointer equals the head pointer, the corresponding memory block is defined as empty and no more bytes will be transferred to the associated signal processor until more data for this program channel is received from the FEC. The actual replacement of the head or tail pointer portion of the respective write or read address by the lower 14 bits of the start pointer may be done by appropriate selection of a multiplexer or by using a tri-state interconnect.

The data transmitted in the form of the auxiliary packets is generally directory, header or control information and thus is handled in a slightly different manner than the program component data. The data in the auxiliary package includes information necessary to establish the necessary memory storage for the individual program components and any included applications. Such an auxiliary package is preferred. Two service blocks are provided for each component. For 256 bytes of data, each block has eight bits of contiguous address or memory location. Each block has a total address of eighteen bits as shown in fig. 6. The eight LSBs of the address are provided by the sequence counter. The ninth bit is provided by the CS or secret key bit from the transport prefix. The tenth through twelfth bits are generated based on the specific SCID assigned for program detection. The present example assumes that the system provides for processing and detecting five program components (including program guides) or services. There are thus five SCIDs programmed into each programmable SCID register 13 and five SCID comparators 15. The five comparators each have an output to which a program component is assigned. The five possible programs associated with the five comparator outputs are assigned respective three-digit codes, three being the minimum number of digits that can represent the five states. A three-bit code is inserted as the tenth to twelfth bits of the auxiliary packet address. Assume that the SCIDs of the five corresponding program components are assigned to programmable registers numbered 1-5 arbitrarily. The three-bit code assigned to the components is assigned to programmable registers 1-5, which are 000, 001, 010, 011 and 100, respectively. Depending on which program component is currently being detected, the three-bit code associated with the programmable register containing the current program component SCID will be inserted in the tenth to twelfth-bit positions in the memory write address.

According to conventional memory management techniques, the six most significant bits of the 18-bit auxiliary address are provided by the microprocessor.

FIG. 7 exemplarily represents an auxiliary memory address generation circuit. Fig. 7 includes a prefix register 125 for receiving prefix bits CS that are applied to the microprocessor 19. The five control lines from SCID detector 15 are provided to a five control line/three bit converter 126, which may be a simple boolean logic operator. The three bits generated by the converter 126 are applied to the microprocessor 19 which constitutes the corresponding 10 Most Significant Bit (MSB) portion of the auxiliary address. When detecting the secondary packet, the 10-MSB address portion is applied to the MSB portion of one of the register sets 128. At the beginning of each secondary packet, the 8-LSB portion of the corresponding register 128 is set to a predetermined value, typically 0. The 8-LSB portion is applied to the 10-MSB portion and to one input port of the 10-to-1 multiplexer 129. The 8-LSB portion of each address provided by the multiplexer 129 is fed to an adder 130 where the 8-LSB address value is incremented by one unit and returned to the 8-LSB portion of the register 128 via a further multiplexer 127. The incremented LSB portion (along with its MSB portion) serves as the next sequential address for the corresponding secondary packet. The multiplexer selectors 127 and 129 are controlled by the DMA controller 98 to select the current memory block at the specified address. It should be noted that in another configuration, μ PC19 may be used to establish at least a portion of the auxiliary address.

The auxiliary package is typically handled separately and the entire active portion of the auxiliary package is typically loaded into memory before it can be used. Thus, the memory blocks addressed for writing the current auxiliary packet are not normally addressed simultaneously for read and write purposes. Thus, the same registers can be used for read and write addressing. Once the helper packet is stored in the corresponding block of memory, the 8-LSB portion is reset to the predetermined start address, ready to read the data. In another configuration, parallel register banks, multiplexers, selectors and adders similar to blocks 127 and 130 may be used to generate read addresses. These read addresses may be time division multiplexed by the next multiplexer in cascade with multiplexer 129.

Read/write control of the memory is performed by the service pointer controller and the direct memory access DMA units 93 and 94. The DMA is programmed to schedule read and write cycles. This arrangement depends on whether the FEC12 provides write data to the memory. The FEC data write operation is preceded and therefore incoming signal component data is not lost. In the exemplary device shown in fig. 4, there are four types of devices that can access the memory. These are a smart card (not shown), FEC12 (more precisely decryptor 16), microprocessor 19 and application devices such as audio and video processors. Memory information contention occurs in the following manner. The DMA allocates memory blocks for the respective program components in response to data requests from the different processing elements described above. The memory is accessed in a time interval of 95 nanoseconds during which a byte of data can be read from the memory 18 or written to the memory 18. There are two main access allocation schemes, which are defined by "FEC provided data" or "FEC not provided data", respectively. Assuming that the maximum FEC data transmission rate is 5 megabytes per second, or 1 byte per 200 nanoseconds, the time interval allocation and priority for each mode is as follows:

FEC provides data

1) Writing FEC data;

2) reading/writing by an application device/a microprocessor;

3) writing FEC data;

4) microprocessor read/write;

FEC does not provide data

1) Smart card read/write;

2) reading/writing by an application device/a microprocessor;

3) smart card read/write;

4) microprocessor read/write.

Because FEC data writing cannot be delayed, it must be guaranteed that the FEC (or more precisely the decryptor) accesses the memory every 200 ns interval when the data is supplied. The further time interval is shared by the application device and the microprocessor. The microprocessor service is provided to apply the time interval when no data is available for the requesting device.

Controller 93 communicates with the SCID detector to determine which of the various start, head and end pointer registers to access for a memory write operation. The controller 93 communicates with the DMA to determine which of the respective start, end and tail registers is accessed for a memory read operation. The DMA98 controls the selection of the corresponding address and data through the multiplexer selectors 99, 104, and 105.

Another preferred circuit for incrementing a memory address is shown in fig. 8, which can be used in either the device of fig. 4 or the device of fig. 7. Fig. 8 illustrates an embodiment of tail pointer incrementing according to fig. 4. At the start of the packet, the pointer in the associated register 92A is coupled to adder 79A, where the pointer is incremented by 1. Instead of storing the intermediate incremented tail pointer in the register 92A (92 of fig. 4) of fig. 8, the intermediate incremented pointer value is stored continuously in the working register 107. After the last pointer value of the signal packet is generated, the updated pointer in register 107 is transferred to register 92A associated with the packet SCID.

It is not uncommon for data in the memory buffer to need to be omitted. For example, when systematic errors and data interruptions occur, part packets may have been stored. To save memory space, data is omitted simply by overwriting a portion of the data packet. The data is overwritten by resetting the appropriate pointer to the value present at the beginning of the packet. This reset does not pass the value in register 107 to the pointer register, and nothing is done to complete the reset.

When packets are lost, it is preferable to insert a media error code into the video component stream so that the video decompressor can interrupt decompression until a particular entry point in the stream occurs. It is not practical to predict where and in which video packet the next entry point may occur. In order to find the next entry point as soon as possible, it is necessary to include a media error code at the beginning of the first video packet after detecting the missing packet. The circuit of fig. 4 places a media error code at the beginning of each video packet and deletes the media error code in the corresponding packet if the previous packet is not lost. The media error code is inserted into the first M memory address locations reserved for the active portion of the current video packet by writing to the memory 18M write cycles before the active portion of the video of the decryptor arrives. While enabling the multiplexer 99 to apply the media error code from the source 100 to the memory 18I/O via the DMA 98. M is an integer number of memory storage units required to store the media error code. Assuming that the memory stores 8-bit bytes and the media error code is 32 bits, then M will be 4.

The address for loading the media error code into memory is provided by the corresponding video component service register 83 via the multiplexer selector 82 and multiplexer 85. It will be appreciated that the first M addresses provided by the pointer register 83 for loading the media error code into the memory storage unit (and also the video component data) will simply be the next M sequential addresses, these addresses typically being generated by the video head pointer. These same addresses are combined with an M-stage delay element 84 so that the last byte of the media error code is stored immediately in the memory 18 and the first M addresses are available at the output of the delay element 84.

The time to load the media error code coincides with the time to determine packet loss. Loading the media error code while determining packet loss has no additional timing constraints on the processing of the signal stream.

If a packet loss is detected, the video component of the current packet is stored in memory 18 at the beginning of the address storage location of the next or (M +1) th memory block established for that component. This is achieved by having the multiplexer 85 continue to have the undelayed head pointer pass from the appropriate register 83. Furthermore, if no packet loss is detected, the first M bytes of the video component in the current packet are stored in memory locations of the memory where the media error code was just previously stored. This is achieved by the service pointer controller conditioning the multiplexer 85 to have the undelayed head pointer pass from the delay element 84 for M write cycles. At the end of the M write cycles, the service pointer controller 93 will cause the multiplexer selector to satisfy the condition, passing the undelayed head pointer again. When the multiplexer switches back to the undelayed pointer, the next undelayed pointer will correspond to the M +1 th address.

The error detector 101 performs packet error or loss detection in response to the CC and HD data of the current packet. The detector 101 checks the continuity count CC in the current packet to determine if it differs by one unit from the CC of the previous packet. The TOGGLE bit in the current packet is also examined to determine if it has undergone a change from the previous packet. If the CC value is incorrect, the TOGGLE bit state is checked. Depending on whether one or both of the CC and TOGGLE bits have errors or have changed, respectively, a first or second error correction scheme is implemented. The second mode is caused by errors in CC and changes in TOGGLE bits, so that the system satisfies the condition to reset packets containing the picture layer header. In the first approach, where only C C has errors, the system is conditioned to reset packets that contain a portion of the start code. (a portion of the layers is a subset of the compressed data in a frame.) in both the first and second modes, the media error code written to memory remains in the corresponding active portion, allowing the decompressor to correct.

Depending on the particular design of a given receiver, the media error code can or can not be included in different signal components when the corresponding component transmission packet is lost. In addition, different media error codes are preferably used for different signal component formats or compression processes. One or more sources of media error codes are then required.

Fig. 9 shows an exemplary flow diagram of a DMA98 memory access process. The DMA determines whether a received packet is detected by detecting the SCID (step 200). If a SCID has been detected indicating that data from the decryptor 16 is to be written to memory, then one byte of program data from the decoder is written to the buffer memory 18 (step 201). The memory block to be written is determined by the processor 93 from the current SCID. The DMA next determines whether any program component processor (including the smart card and the μ PC) is requesting data or read/write (R/W) access to the memory 18 (step 202). If the DMA determines that there is no data request, then the process returns to step 200. If there is a R/W request for data, the DMA determines the priority of the request (step 203). This can be done by a conventional interrupt routine or a variable order of one byte service in any order in which the program processors request data. For example, assume that an arbitrary order of access priority is video, audio I, audio II, smart card, and μ PC. Assume that only video, audio II and μ PC request memory access. During the current operation of step 203, one byte of video data will be read out of memory. During the next operation of step 203 one byte of audio II data will be read out of the memory, while during the sequentially following operation of step 203 one byte of μ PC data will be written to the memory 18 or read out of the memory 18, etc. It should be noted that the access addresses of the smart card and the μ PC are provided by the smart card and the μ PC, respectively, but the video, audio and program guide addresses are available from the address pointer unit (80-93).

Once the access priority is established (step 203), the desired program processor is used (step 204) by writing one byte of data to or reading it from memory 18. The next byte of data from the decryptor 16 is written to memory (step 205). It is determined whether the μ PC requests access by checking in step 206. If the μ PC requests access, one byte of data is used (step 207). If the mupc does not request access, the process jumps to step 202 to determine if any program processors request access. In this way, access to each further memory access cycle by incoming data is always guaranteed, and intervening memory access cycles are distributed among the program processors.

If no data is currently available from the decryptor 16, i.e. no SCID is currently detected, then the process continues (208-. The smart card is first checked to determine if memory access is requested at step 208. If so, a one byte memory access is given (step 209), otherwise a determination is made as to whether any program processor requests a memory access by checking in step 210. If there is a R/W request for data, then the DMA determines the priority of the request (step 211). The appropriate processor is used with a one byte memory read or write access (step 212). If the program processor has not made a data R/W request, then the process jumps to step 213 where it is determined by checking whether the smart card requests memory access. If so, a one byte memory access is used (step 216), otherwise the process jumps to step 200.

It will be appreciated that in the preferred embodiment, the smart card is provided with two/one access prior to all other program processors when in the "FEC no data" mode. This priority is programmed into a programmable state machine in the DMA device and is changed by the μ PC. As previously mentioned, the system is intended to provide interactive services, and the μ PC19 will perform at least a portion of the interaction in response to the interactive data. Thus, the μ PC19 uses the memory 18 as both application memory and working memory. In these examples, the system operator may change the memory access priority to provide more frequent memory accesses to the μ PC 19. Reprogramming of memory access priorities may be accounted for as a subset of the interactive application instructions.

When a packet is lost, it is preferable to insert a media error code into the video component stream so that the video decompressor satisfies a condition to interrupt decompression until a particular entry point in the stream occurs. It is not practical to predict where and in which video packet the next entry point may occur. In order to find the next entry point as soon as possible, it is necessary to include a media error code at the beginning of the first video packet after detecting the missing packet. The circuit of fig. 4 places a media error code at the beginning of each video packet and deletes the media error code in the corresponding packet if the previous packet is not lost. The media error code is inserted into the first M memory address locations reserved for the active part of the current video packet by writing to the memory 18M write cycles before the video active part of the decryptor arrives. While the multiplexer 99 is conditioned by the DMA98 to apply the media error code from the source 100 to the memory 18I/O. M is an integer number of memory storage units required to store the media error code. Assuming that the memory stores 8-bit bytes and the media error code is 32 bits, then M will be 4.

The address to load the media error code into memory is provided by the corresponding video component usage register 83 via the multiplexer selector 82 and multiplexer 85. It will be appreciated that the first M addresses provided by the pointer register 83 for loading the media error code into the memory storage unit (and also the video component data) will be directly the next M sequential addresses, these addresses typically being generated by the video head pointer. These same addresses are combined with an M-stage delay element 84 so that the last byte of the media error code is stored immediately in the memory 18 and the first M addresses are available at the output of the delay element 84.

The error detector 101 performs packet error or loss detection in response to the CC and HD data of the current packet. The detector 101 checks the continuity count CC in the current packet to determine if it differs by one unit from the CC of the previous packet. The TOGGLE bit in the current packet is also examined to determine if it presents the appropriate state for the corresponding video frame. If the CC value is incorrect, the TOGGLE bit state is checked. Depending on whether one or both of the CC and TOGGLE bits are in error, either the first or second error correction mode is implemented. In the first method in which only CC has an error, the system is made to satisfy a condition and a packet including a slice header is reset. (a slice is a subset of the compressed data in a frame.) a second way, caused by errors in the CC and TOGGLE bits, is to condition the system to reset the packets containing the picture layer header. In both the first and second modes, the media error code written to the memory is maintained in the corresponding active portion, allowing the decompressor to correct.

If a packet loss is detected, the video component of the current packet is stored in the memory 18 at the beginning of the next or (M +1) th address location. This is achieved by having the multiplexer 85 satisfy the condition to continue to have the undelayed head pointer go from the appropriate register 83. Furthermore, if no packet loss is detected, the first M bytes of the video component in the current packet are stored in memory locations of the memory where the media error code was just previously stored. This is achieved by the service pointer controller conditioning the multiplexer 85 to have the undelayed head pointer pass from the delay element 84 for M write cycles. At the end of the M write cycles, the service pointer controller 93 will cause the multiplexer selector to satisfy the condition, passing the undelayed head pointer again. When the multiplexer is switched off, the next undelayed pointer will correspond to the M +1 th address when the undelayed pointer is.

Depending on the particular design of a given receiver, the media error code can or can not be included in different signal components when the corresponding component transmission packet is lost. In addition, different media error codes are preferably used for different signal component formats or compression processes. One or more media error codes are then required.

Fig. 10 shows an exemplary apparatus for detecting a packet including conditional access information or an MPEG start code (decoder 30 of fig. 3). Either the decoder 30 satisfies the condition to detect the named valid part or the MPEG start code is a function of the SCID currently being received. In fig. 10, it is assumed that the data supplied from the decryptor 16 is one byte at 8 bits and the packets are aligned. That is, the first byte of the named valid part or the first byte of the MPEG start code is exactly aligned with the beginning of the packet valid part, so that their position in the bit/byte stream is exactly known for detecting a particular header or start code word. The data from the decryptor 16 is applied to an 8-bit register 250 having 8-bit parallel output ports connected to respective first input connections of comparators 254, the comparators 254 being formed, for example, by a set of eight exclusive nor (XNOR) circuits, the respective output connections of which are connected to an and gate, and a LATCH (LATCH). The latch may be a data latch for latching the result of the and gate at each byte interval.

The 32-bit MPEG start code is stored as four bytes in an eight-bit register set 265. The named header is stored as an 8-bit byte in an eight-bit register bank 251. The loading of the register sets 251 and 265 is controlled by the microprocessor 19 and/or the smart card. The start code register 265 is connected to the four/one multiplexer selector 266 and the named header register is connected to the sixteen/one multiplexer selector 257. The outputs of the multiplexer selectors 257 and 266 are connected to the two/one multiplexer 249. Respective output connections of the multiplexer 249 are connected to respective second inputs of the comparators 254. Note that the input and output connections of the multiplexer selectors 249, 257 and 266 are 8-bit buses. A true signal is generated for the corresponding data byte comparator 254 circuit if the respective value on the corresponding output connection of register 250 corresponds equally to the respective output value on the corresponding output connection of multiplexer 249.

For start code detection, the counter 258 scans the multiplexer 266 to sequentially connect four different registers 265 to the XNOR in synchronism with the first four data bytes presented by the decryptor 16. In addition, for named-active header detection, the counter 258 scans the multiplexer 257, sequentially connecting different registers 265 to the comparator circuit.

The output of the comparator circuit is connected to an accumulation and verification circuit 255. Circuitry 255 determines whether any of a predetermined number of byte matches of the bytes satisfies the condition and, if so, generates a write enable signal for the named data in the portion of the particular active portion that was examined. In the present system, the named-valid-part header contains 128 bits, which 128 bits are divided into four segments of 32 bits each. Different users may find different combinations of the 128-bit bytes. For example, a user device may be arranged to conform to the first four bytes of the named-active part header. And another user device may be arranged to conform to the second four bytes of the named-active part header, and so on. In either of the exemplary cases described above, circuit 255 will determine whether a match has occurred for the appropriate four consecutive bytes.

The apparatus of FIG. 10 also includes circuitry (element 261) for detecting an all 0 named-valid header condition. The bits of each incoming byte of data are connected to respective terminals of an 8-bit or gate 263. If any bit is a logic 1, then OR gate 263 produces a logic output. The output of or gate 263 is coupled to an input of a two-input or gate 262, or gate 262 having an output and a second input coupled to the data input and the Q output of D-type latch 261, respectively. In synchronism with the arrival of the incoming data byte, the D-latch is locked out by timing circuit 259. If any bit in any data byte that occurs after the latch is reset is a logic 1, then latch 261 will be a logic 1 at its Q output until the next reset pulse. The Q output of latch 261 is connected to an inverter whose output level is 0 whenever the output level of the latch is 1. Thus, if the output of the inverter is high after 128 bits (16 bytes) of the header have passed through register 250, then the 128 bits are a 0 value. The detection of the output high from the inverter after the passage of the named active part header will generate a data write enable signal based on this detection circuit 255.

From the above, it can be seen that it is very efficient to split the system such that the SCID detector, the decryptor, the addressing circuitry, the conditional access filter and the smart card interface are all included in a single integrated circuit. This limits the number of external lanes that may cause critical timing constraints.

Claims (5)

1. Apparatus for processing signals in a signal transmission processor, said signals comprising time division multiplexed switch selected packets of program components, wherein each packet comprises a valid portion of program component data and a header containing a program component identifier SCID, wherein the valid portions of the respective components are stored in mutually exclusive portions of a common buffer memory (18), circuitry for addressing said buffer memory comprising:

a source (11) of packets selected by a time division multiplex switch;

SCID detector (13-15), it responds to each component identifier in the header of the packet, detect the packet signal with predetermined program component;

a plurality of direct memory access circuits (79-97);

control means (98) programmed for adjusting respective ones of said direct memory adoption circuits to write valid portions of received packets into appropriate ones of said mutually exclusive portions of said common buffer memory in accordance with said detected identifier.

2. The apparatus of claim 1, wherein the plurality of direct memory adoption circuits each comprise:

a register for storing a start pointer provided by the control device; and

another register for storing a value associated with a last address of a respective mutually incompatible portion of said common buffer memory.

3. The apparatus of claim 2, wherein each of said plurality of direct memory access circuits further includes a register for storing the current write address, said plurality of direct memory access circuits further including a common increment circuit for incrementing the respective memory address stored in each of said registers for storing the current write address.

4. The apparatus of claim 3, wherein each of the plurality of direct memory access circuits further comprises a further register for storing a current read address.

5. The apparatus of claim 4, wherein said plurality of direct memory access circuits includes another common increment circuit for incrementing the respective memory address stored in each of said registers to store the current read address.