HK1002941A1 - Method and structure for evaluating and enhancing the performance of cache memory systems - Google Patents

Method and structure for evaluating and enhancing the performance of cache memory systems

Info

Publication number
HK1002941A1
HK1002941A1 HK98102009A HK98102009A HK1002941A1 HK 1002941 A1 HK1002941 A1 HK 1002941A1 HK 98102009 A HK98102009 A HK 98102009A HK 98102009 A HK98102009 A HK 98102009A HK 1002941 A1 HK1002941 A1 HK 1002941A1
Authority
HK
Hong Kong
Prior art keywords
cache hit
data
cache
hit rate
elements
Prior art date
Application number
HK98102009A
Inventor
Michael A Salsburg
Original Assignee
Zitel Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Zitel Corp filed Critical Zitel Corp
Publication of HK1002941A1 publication Critical patent/HK1002941A1/en

Links

Classifications

    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F12/00—Accessing, addressing or allocating within memory systems or architectures
    • G06F12/02—Addressing or allocation; Relocation
    • G06F12/08—Addressing or allocation; Relocation in hierarchically structured memory systems, e.g. virtual memory systems
    • G06F12/12—Replacement control
    • G06F12/121—Replacement control using replacement algorithms
    • G06F12/123—Replacement control using replacement algorithms with age lists, e.g. queue, most recently used [MRU] list or least recently used [LRU] list
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F11/00—Error detection; Error correction; Monitoring
    • G06F11/30—Monitoring
    • G06F11/34—Recording or statistical evaluation of computer activity, e.g. of down time, of input/output operation ; Recording or statistical evaluation of user activity, e.g. usability assessment
    • G06F11/3447—Performance evaluation by modeling
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F12/00—Accessing, addressing or allocating within memory systems or architectures
    • G06F12/02—Addressing or allocation; Relocation
    • G06F12/08—Addressing or allocation; Relocation in hierarchically structured memory systems, e.g. virtual memory systems
    • G06F12/0802—Addressing of a memory level in which the access to the desired data or data block requires associative addressing means, e.g. caches
    • G06F12/0888—Addressing of a memory level in which the access to the desired data or data block requires associative addressing means, e.g. caches using selective caching, e.g. bypass
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F11/00—Error detection; Error correction; Monitoring
    • G06F11/30—Monitoring
    • G06F11/34—Recording or statistical evaluation of computer activity, e.g. of down time, of input/output operation ; Recording or statistical evaluation of user activity, e.g. usability assessment
    • G06F11/3452—Performance evaluation by statistical analysis
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F2201/00—Indexing scheme relating to error detection, to error correction, and to monitoring
    • G06F2201/805—Real-time
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F2201/00—Indexing scheme relating to error detection, to error correction, and to monitoring
    • G06F2201/885—Monitoring specific for caches

Landscapes

  • Engineering & Computer Science (AREA)
  • Theoretical Computer Science (AREA)
  • General Engineering & Computer Science (AREA)
  • General Physics & Mathematics (AREA)
  • Physics & Mathematics (AREA)
  • Evolutionary Biology (AREA)
  • Computer Hardware Design (AREA)
  • Bioinformatics & Computational Biology (AREA)
  • Quality & Reliability (AREA)
  • Life Sciences & Earth Sciences (AREA)
  • Bioinformatics & Cheminformatics (AREA)
  • Memory System Of A Hierarchy Structure (AREA)
  • Management, Administration, Business Operations System, And Electronic Commerce (AREA)
  • Complex Calculations (AREA)

Abstract

Method and structure for collecting statistics for quantifying locality of data and thus selecting elements to be cached, and then calculating the overall cache hit rate as a function of cached elements. LRU stack distance has a straight-forward probabilistic interpretation and is part of statistics to quantify locality of data for each element considered for caching. Request rates for additional slots in the LRU are a function of file request rate and LRU size. Cache hit rate is a function of locality of data and the relative request rates for data sets. Specific locality parameters for each data set and arrival rate of requests for data-sets are used to produce an analytical model for calculating cache hit rate for combinations of data sets and LRU sizes. This invention provides algorithms that can be directly implemented in software for constructing a precise model that can be used to predict cache hit rates for a cache, using statistics accumulated for each element independently. The model can rank the elements to find the best candidates for caching. Instead of considering the cache as a whole, the average arrival rates and re-reference statistics for each element are estimated, and then used to consider various combinations of elements and cache sizes in predicting the cache hit rate. Cache hit rate is directly calculated using the to-be-cached files' arrival rates and re-reference statistics and used to rank the elements to find the set that produces the optimal cache hit rate.
HK98102009A 1993-07-16 1998-03-11 Method and structure for evaluating and enhancing the performance of cache memory systems HK1002941A1 (en)

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
US08/093,073 US5452440A (en) 1993-07-16 1993-07-16 Method and structure for evaluating and enhancing the performance of cache memory systems

Publications (1)

Publication Number Publication Date
HK1002941A1 true HK1002941A1 (en) 1998-09-25

Family

ID=22236828

Family Applications (1)

Application Number Title Priority Date Filing Date
HK98102009A HK1002941A1 (en) 1993-07-16 1998-03-11 Method and structure for evaluating and enhancing the performance of cache memory systems

Country Status (11)

Country Link
US (1) US5452440A (en)
EP (1) EP0708942B1 (en)
AT (1) ATE158425T1 (en)
AU (1) AU672719B2 (en)
CA (1) CA2167307A1 (en)
DE (1) DE69405758T2 (en)
DK (1) DK0708942T3 (en)
ES (1) ES2108475T3 (en)
GR (1) GR3025221T3 (en)
HK (1) HK1002941A1 (en)
WO (1) WO1995002864A1 (en)

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Also Published As

Publication number Publication date
AU672719B2 (en) 1996-10-10
ATE158425T1 (en) 1997-10-15
DE69405758T2 (en) 1998-04-09
WO1995002864A1 (en) 1995-01-26
GR3025221T3 (en) 1998-02-27
EP0708942B1 (en) 1997-09-17
AU7361194A (en) 1995-02-13
DK0708942T3 (en) 1998-05-04
DE69405758D1 (en) 1997-10-23
CA2167307A1 (en) 1995-01-26
ES2108475T3 (en) 1997-12-16
EP0708942A1 (en) 1996-05-01
US5452440A (en) 1995-09-19

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