GR20180200135U - Saving and restoring prediction state - Google Patents

Abstract

A branch predictor is provided with a branch state buffer, branch prediction save circuitry responsive to a branch prediction save event associated with a given execution context to save at least a portion of the active branch prediction state associated with the given execution context to a branch state buffer; and branch prediction restore circuitry responsive to a branch prediction restore event associated with the given execution context to restore active branch prediction state based on previously saved branch prediction state stored in the branch state buffer for the given execution context. This is useful for reducing the performance impact of mitigating against speculative side-channel attacks.

Description

SAVE AND RESTORE PREDICTION STATE

BRANCH

BACKGROUND

Technical field

The present technique relates to the field of data processing. More specifically it relates to industry forecasting.

Technical background

A data processing device may have a branch prediction circuit for predicting the results of branch instructions prior to their actual execution. By predicting branch results before the branch instruction actually executes, subsequent instructions that follow the branch can begin to be fetched and hypothetically executed before the branch instruction has finished executing, so if the prediction is correct then performance is protected because the trailing orders can be executed earlier than if they were submitted only as soon as the branch result was actually known.

SUMMARY

At least some examples provide an apparatus comprising:

a processing element for processing commands from a plurality of execution contexts;

a branch prediction means for predicting the results of branch instructions processed by the processing element based on the active branch prediction state stored in a branch prediction store;

a branch prediction control circuit responsive to an execution frame switch from a first execution frame to a second execution frame to prevent the branch predictor from predicting results of branch instructions of the second execution frame based on the trained branch prediction state based on results of previous branch commands of the first execution frame,

branch prediction storage circuitry responsive to a branch prediction storage event associated with a given execution context to store at least a portion of the active branch prediction state associated with the given execution context in a branch state buffer, and

a branch prediction reset circuit responsive to a branch prediction reset event associated with the given execution context to reset the active branch prediction state based on the previously stored branch prediction state stored in the branch state buffer for the given execution context.

At least some examples provide an apparatus comprising:

means for processing instructions from a plurality of execution frames, means for predicting results of branch instructions which are processed by the processing means based on the active branch prediction state stored in a branch prediction store;

means for controlling the branch predictor, which in response to an execution frame transitions from a first execution frame to a second execution frame, configured to prevent the branch predictor from predicting results of branch instructions of the second execution frame based on trained branch prediction state based on the results of the previous branch instructions of the first execution frame;

means for storing, in response to a branch prediction save event associated with a given execution context, at least a portion of the active branch prediction state associated with the given execution context in a branch state cache, and means for restoring, in response of a branch prediction reset event associated with the given execution context, the active branch prediction state based on the previously saved branch prediction state stored in the branch state cache for the given execution context.

At least some examples provide a branch prediction method for a device including a processing element for processing instructions from a plurality of execution contexts, the method comprising:

predicting results of branch instructions processed by the processing element based on the active branch prediction state stored in a branch prediction store;

in response to an execution frame switch from a first execution frame to a second execution frame, preventing the branch predictor of the second execution frame from predicting the results of branch instructions based on the trained branch prediction state based on the results of its previous branch instructions first execution frame,

in response to a save branch prediction event associated with a given execution context, storing at least a portion of the active branch prediction state associated with the given execution context in a branch cache, and

in response to a branch prediction reset event associated with the given execution context, resetting the active branch prediction state based on the previously saved branch prediction state stored in the branch state cache for the given execution context.

BRIEF DESCRIPTION OF THE DRAWINGS

Further aspects, features and advantages of the present technique will become apparent from the following description of the examples, which should be read in conjunction with the accompanying drawings, in which:

Figure 1 schematically illustrates an example of a data processing device having a branch predictor,

Figure 2 schematically illustrates the provision of a branch state cache for storing and restoring the branch prediction state in the branch predictor,

Figures 3 to 6 illustrate a number of examples of compression and decompression of the branch prediction state,

Figure 7 shows an example in which the branch prediction store includes a number of regions and the branch state cache includes at least one of the regions of the branch prediction store,

Figures 8 through 10 illustrate examples in which the active branch prediction state is disabled in response to an execution frame switch, and if it still remains when a subsequent execution frame switch returns to the previous frame, is then re-enabled;

Figure 11 illustrates an example of a TAGE branch predictor that uses a perceptron predictor as a transition predictor,

Figure 12 illustrates an example in which the TAGE branch predictor of Figure 11 is combined with a further perceptron in a hybrid predictor,

Figure 13 is a diagram comparing the performance of a predictor similar to that of Figure 11, which stores partial state, with conventional TAGE and perceptron predictors which do not maintain state through frame switches,

Figure 14 is a diagram illustrating the performance impact of starting a fully hot branch predictor after a frame switch to a new core,

Figure 15 illustrates a theoretical representation of a TAGE predictor using a dihedral predictor as a transition predictor,

Figure 16 illustrates a theoretical representation of a multidimensional perceptron prediction device,

Figure 17 shows a branch prediction state store and restore mechanism,

Figure 18 illustrates an example of branch prediction state migration between processing elements,

Figure 19 is a chart comparing different sizes and types of forecasting arrays,

Figure 20 is a graph that provides a comparison between the branch misprediction rate for the TAGE and perceptron predictors,

Figure 21 is a diagram illustrating the results of an investigation of the effects on branch misprediction rate when storing different subsets of branch prediction state;

Figure 23 illustrates the effect on branch misprediction rate when varying the size and number of feature matrices of the perceptron predictor,

Figures 24 and 25 are graphs illustrating the effects on branch misprediction rate when a maximum of 1.25 kilobytes of branch predictor state is maintained after a frame switch, and Figure 26 compares the fixed branch misprediction rate for different types of predictors sector.

DESCRIPTION OF EXAMPLES

Saving and Restoring Branch Predictor State A data processing device may have a branch predictor mechanism for predicting an outcome of a branch instruction. Traditionally a branch prediction mechanism would be thought of as a performance improvement mechanism whose mispredictions are not critical to the safety of the data being processed on a data processing device, but simply affect the level of performance achieved. This is because if a branch is incorrectly predicted then while processing circuitry may temporarily execute the wrong instructions, once the actual branch result is determined and compared to a prediction, the incorrect prediction can be detected and then a processing pipeline can be emptied of subsequent instructions that were served based on the wrongly predicted branch, while the processor's architectural state can be reverted to the point at which the branch was answered to cancel out the architectural effects of subsequently assumed instructions that turn out to be wrong.

However, it has recently been recognized that a branch prediction circuit could provide a path that an attacker could exploit to bypass security protections that may be provided on a data processing device to restrict certain software workloads from accessing data related to other software workloads; This is because in some branch predictors it is possible to assign a branch predictor state entry to the branch predictor based on the fact that it would be possible to access the branch history observed in an execution context by a different software workload and use of for predicting the outcome of branches of this different software framework. Previously, such use of the branch prediction state by one frame to predict the results of branches in another frame would simply be considered a performance issue, such as if the second frame succeeded in misregistering the branch predictor assigned by a first frame and then any incorrect prediction resulting from this can be identified later and resolved once the actual branch result is known and this would simply be expected to cause a delay in processing the correct branch result, but would not be expected to cause a risk security.

However, it has been recognized that instructions that are hypothetically executed incorrectly due to a mispredicted branch can still affect data in a cache or other unarchitected storage structure used by a data processing device. This could be exploited by an attacker to try to gain some information about potentially sensitive data that is not accessible to the attacker, but is accessible to another execution context that can be tricked by the attacker into executing commands designed to obtain access secrets and cause changes to the cache allocation that expose some information about the secret to the attacker. For example an attacker could train the branch predictor with a pattern of branch accesses so that when the victim execution framework later accesses the same entry it will incorrectly execute an instruction from a wrong destination address or follow a wrong prediction by how much a branch is occupied or unoccupied, causing an inappropriate access to secret information. Cache timing side channels can then be used to investigate the implications of the false hypothesis for leaking information about the secret.

A countermeasure technique to guard against such attacks may be to provide a branch prediction control circuit responsive to an execution frame switch from a first execution frame to a second execution frame to prevent the second frame from predicting results of branch instructions. branch layout based on the trained branch prediction state based on the previous results of the previous branch instructions of the first execution frame. This could be implemented in a number of ways, for example by flushing the branch prediction state associated with the first execution frame from the branch prediction store in response to the execution frame switch, or titling the branch prediction store entries to identify the execution frame with which they are associated and then ensuring that lookups of branch prediction storage performed in one execution context cannot find entries allocated by another execution context. However, such issues can have significant performance implications because when the second execution frame starts then the branch predictor may need to be started from a cold state, with no pre-populated branch predictions available to predict branch instructions in the next frame.

In the techniques described below, a branch state cache is provided in which the branch prediction state from the branch prediction storage can be stored and from which the previously saved branch prediction state can be restored. Accordingly, in response to the raising of a branch prediction store event for a given execution context, a branch prediction storage circuit stores at least a portion of the active branch prediction state in the branch state buffer. In response to the association of a branch prediction reset event with the given execution context, the active branch prediction state is restored to the branch prediction store based on the branch prediction state previously stored in the branch state cache for the given execution context. Therefore, even when after an execution frame switch the previously trained branch prediction state based on the outgoing execution frame becomes unavailable, restoring the previously stored branch prediction state for the incoming frame may mean that attacks of the form discussed above can be handled with less performance loss.

In some implementations the branch state cache may be used to store the entire set of active branch prediction states for a given execution context. However, in typical implementations of branch prediction arrangements this may be relatively large, for example 64 kilobytes, and it may not be acceptable to provide additional storage capacity to store previous branch prediction state of this size.

Accordingly, in some examples the branch prediction storage circuitry may perform branch prediction state compression to compress at least a portion of the active branch prediction state to create a compressed branch prediction state to be stored in the branch state cache. When restoring the previously saved branch prediction state, the state may be decompressed by the branch prediction reset circuit to create the active branch prediction state to be restored. This can reduce the amount of data that must be stored and retrieved (eg, by a factor of up to 64), reducing the impact of dealing with hypothetical side-channel attacks of the form discussed above.

Compression and decompression can be done in a number of different ways. In one example, the branch predictor may have a number of separate predictor units for predicting the results of branch instructions using various branch prediction methods and a selector for choosing between the results predicted by the various predictor units. For example, one of the predictor modules could be a TAGE predictor, which uses labeled geometric history matrices to provide the branch prediction, while another predictor module could be a transition predictor (p .eg a binary predictor using two-bit confidence counters or a perceptron predictor storing sets of weights, for which a prediction is produced based on a sum of terms, each term depending on a corresponding weight chosen based on a corresponding part of the program counter and/or historical information). In one example, instead of including all branch prediction states according to all different types of prediction layout units, the branch prediction state associated with at least one of the prediction layout units may be omitted from the compressed branch prediction state. When restoring the active branch prediction state based on the contents of the branch state cache, a prediction device whose state has been included in the compressed branch prediction state may be reset based on that compressed branch prediction state, while the branch prediction state of prediction layout units for which the branch prediction state was received from the compressed branch prediction state may be reset to default values for example.

As discussed below, different types of predictors can provide different levels of throughput gain per bit of storage capacity required to store the respective branch predictor state, and thus it may be preferable to select, as the predictor unit whose state is included in the compressed state of provisioning sector, one or more types of provisioning that provide the highest level of performance increase per unit of data storage. From the analysis discussed below, it is found that usually the transition prediction module, which produces a transition prediction in the event that at least one other prediction module outputs a prediction with confidence less than a predetermined threshold value, can provide the highest level of enhancement of the throughput per bit of information stored. Therefore, in some cases the compressed branch prediction state may include an active branch prediction state associated with the transition prediction module, but could omit a branch prediction state associated with other types of branch prediction modules. For example, the basic predictor is often a simpler type of branch predictor than other more complex branch predictors, and while other types of predictors may provide greater absolute performance improvement, it may cost more in terms of storage capacity, so it may be more efficient to cache the state of the transition predictor. In some examples, the transition predictor module may be a bi-row predictor that includes, as the branch prediction state, an array of confidence counters indicating whether a branch is predicted with a high degree of confidence when followed, predicted with a low degree confidence when followed, predicted with low confidence when not followed, or predicted with high confidence when not followed. Alternatively, as discussed below the transition predictor could be a perceptron predictor.

Another way to compress the branch prediction state can be to apply compression to the branch prediction state of a given type of branch prediction layout. For example, the active branch prediction state may include, for a given branch prediction layout unit, a number of branch prediction entries each specifying a prediction state value for generating a branch prediction. Branch prediction entries may be indexed based on an index determined as a function of at least one target instruction address for which a branch prediction is required and at least a portion of past execution history indicative of an execution behavior pattern preceding an instruction at the instruction address . For example, if the branch predictor unit is a bi-root predictor then the prediction state values of each entry could be the confidence counters of the bi-root predictor. If the prediction array unit is a perceptron then the prediction state values in each entry could be weight values used to generate weighted sums of index parts. Compression and decompression can be performed on individual entries or groups of entries.

For example, some implementations may apply compression to a single branch prediction entry. The prediction state value of a given branch prediction entry may be mapped to a compressed prediction state value that has fewer bits than the prediction state value, to reduce the total storage required in the branch state cache when the compressed data is stored. In this case, when resuming the compressed state as the active state, then each omitted bit can either take the default values or could take variable values determined based on other parts of the compressed prediction state.

In another example, compression may be applied in a vertical fashion between entries of the active branch prediction state. For example, the compression may include merging a group of multiple branch prediction entries corresponding to different index values into a single entry to be stored in the branch state cache within the compressed branch prediction state. In this case, when the state is restored from the branch state cache then each of the multiple entries from which a given entry of the compressed state was merged can be restored based on the values resulting from the single merged entry. For example each of the group entries could take the same value as indicated by the merged entry of the compressed state. When saving state, merging a group of branch prediction entries into a single shared entry could be accomplished in a number of ways. In some cases, any entry from the group of entries may be selected, and the single merged entry may take the values of that selected entry. Alternatively, for a given segment of the merged entry in the compressed branch prediction state, that segment could take the value that a majority of the group of entries used for that segment.

Some branch prediction layouts may reduce the total number of branch prediction states by sharing some portions of the prediction state value between multiple entries. For example, for a group of two or more branch prediction entries of the active branch prediction state, each prediction state value could include a hidden part specified separately for each of the branch prediction entries in the group and a shared part used by shared by each of the group's industry prediction entries. This would avoid the need to specify the shared section multiple times for each group entry. When the active branch prediction state shares part of the prediction state value between entries in this way, then compressing the branch prediction state could involve either omitting the shared part and keeping the hidden part, or omitting the hidden part and keeping the shared part. On rollback, the part of the predicted state value that is omitted can then take a default value or a value inferred from the preserved part that was included in the compressed state.

Another option may be a form of compression that partially merges a group of branch prediction entries and forms a compressed branch prediction state in which a first part of the prediction state value of each branch prediction entry in the group is specified separately within the compressed branch prediction state while a second portion of the prediction state value of each branch prediction entry is merged to form a value representing a shared second part for each entry from the group of branch prediction entries. Therefore, even if the active branch prediction state used by the branch predictor does not share any part of the prediction state value between entries, compression could introduce such sharing as to reduce the amount of data that required to cache branch states. By restoring the previously compressed state, the decompression can then determine values for the second part of the group entries based on the merged value, e.g. copying the merged value to each of the entries for the second segment of the branch forecast state value.

The save event of the branch prediction associated with the given execution context could include any or more of the following:

• the execution frame switch, for which the given execution frame is the first execution frame;

· the transition of the given execution context from the processing element to another processing element,

• the passage of a predetermined period since a previous branch forecast storage event;

• detecting or executing a branch prediction store instruction within the given execution context, and

• an update of the active branch prediction state that satisfies a predetermined condition that occurs during the execution of the given execution context.

Accordingly, in some cases the prediction state may be stored in the branch state buffer in response to the execution frame switching itself or in response to the transition of a frame from the processing element to another processing element. However, it may also be possible to cache the active branch prediction state associated with a given execution context in the branch state cache periodically during the processing of the given execution context so that fewer state saves are required during execution context switching, which which can improve performance. For example, a state could be periodically stored in the branch state cache or in response to an update of the active branch prediction state that satisfies some predefined condition (eg, a change that results in greater than a threshold confidence level). . Also, in some cases a state prediction save instruction may be defined which when included in the software of the given execution framework can trigger the branch prediction storage circuitry to store the currently active branch prediction state (with compression if necessary) to branch state cache.

Similarly, the branch prediction reset event associated with a given execution context may include one or more of the following:

• execution frame switching, for which the given execution frame is the second execution frame,

• the transition of the given execution context from another processing element to the processing element associated with the branch predictor for which the state is reset;

• the passage of a predetermined period since a previous industry forecast reset event, and

• detecting or executing a branch prediction reset command within the given execution context.

In some examples the branch state cache may be a separate storage area from the branch prediction store. In this case, the save and restore may involve actually transferring the branch prediction state between the branch prediction store and the branch state cache.

However, in other examples the branch state cache may correspond substantially to a portion of the branch prediction store that is not currently in use. For example the branch prediction store may have a number of regions and at a given time one of these regions may correspond to the active branch prediction state while other regions may correspond to previously stored branch prediction states in the branch state cache. Accordingly, the branch state cache may include at least one region of the branch prediction store. In this case, the branch prediction reset circuit can store and restore the active branch prediction state simply by switching the area of the branch prediction storage used to represent the active branch prediction state. This can improve performance by preventing the need to actually transfer data when saving or restoring a state.

In approaches that apply compression or decompression, however, it may be preferable to use a separate branch state cache, as this can reduce the overall size of branch state storage in the branch prediction store and the branch state cache as a whole.

In some examples, in response to execution context switching, the active branch prediction state associated with the first execution context could simply be discarded so that it is invalidated and no longer accessible (except by restoring the saved branch prediction state from the temporary branch state memory). However, in other examples following execution frame switching the branch prediction state associated with the first execution frame could be disabled so that it cannot be accessed to make branch predictions for the incoming second execution frame, but could be maintained within the industry forecast repository. This can help improve performance because then on a later execution frame switch the previously disabled branch prediction state associated with the incoming execution frame could still be present in the branch prediction store, in which case it can be re-enabled so that allowing the incoming second execution frame to restart with a warm branch prediction state that has already been trained based on a previous time at which the second execution frame was executed. This means that even parts of the branch prediction state that are lost during the application of any compression when caching branch states can be preserved for some time so that if the system returns relatively quickly to a previously executed frame then it is possible to performance improvement.

Various approaches can be used to control whether or not the active branch prediction state associated with an outgoing process should be maintained in a disabled manner after execution context switching. In one example, in response to execution frame switching the branch prediction control circuitry may disable a portion of the branch prediction arrangement for an initial processing period of the second execution frame while maintaining in the branch prediction store an active branch prediction state associated with that part of the branch predictor which was trained based on the results of the branch instructions of the first execution frame. For example, the disabled segment may be the branch predictor units whose state is not included within the compressed state stored in the branch state cache. By disabling this part of the branch predictor for an initial period and maintaining the corresponding state within the branch prediction store, this means that if one more execution context switch occurs within that initial period which causes processing to roll back on the first execution frame, then that frame in the branch prediction state may still be available within the branch prediction store and may be retriggered to improve performance even if that part of the branch prediction state had not been cached branch state memory. On the other hand, if the initial period expires before any subsequent execution switch occurs then the active branch predictor state associated with the part of the branch predictor that was disabled may be canceled, and that part of the branch predictor may be re-enabled to continue. processing the second execution frame so that the second execution frame can then begin to benefit from the use of the previously disabled portion of the branch predictor. Therefore, with this approach if the second execution frame lasts less than the initial period then this may provide an opportunity for an incoming execution frame to reactivate its unsaved branch state, while if the second execution frame lasts longer than in the initial period then the state associated with the disabled part of the branch predictor may be discarded so that the second execution frame will not make predictions based on the branch prediction state derived from a different frame, so as to reduce the effects of the attack on security discussed above.

An alternative approach to this may be to provide a prediction of the lifetime of the second execution frame in response to an execution frame switch, and depending on the predicted lifetime, choose whether to (a) disable a portion of the branch predictor; while processing the second execution frame while maintaining the active branch prediction state associated with the disabled portion of the branch predictor that was trained based on the first execution frame, or (b) invalidate the branch prediction state data associated with the portion of branch predictor that was trained on the first execution frame and then allow that portion of the branch predictor to be used when processing the second execution frame. Therefore, for execution frames that are expected to be relatively long-lived, it may be more efficient to enable the second execution frame's portion of the branch prediction arrangement to be used from scratch, and thus in this case the branch prediction state data trained based on the first execution frame can be canceled at the time the execution frame switch is handled, instead of waiting for an initial period to expire as discussed above. On the other hand, if the second execution frame is predicted to have a shorter lifetime, it may be preferable to keep the active branch prediction state associated with the first execution frame in a disabled part of the branch predictor to prevent branch predictions from being made by the second execution framework based on a state trained by a different execution framework. Although disabling this part of the branch predictor may slightly reduce performance for the second execution frame, since the second execution frame is expected to have a short lifetime, then the performance benefit of re-enabling the preserved state for the first frame execution time when the first execution frame is executed again, may outweigh the small performance decrease for the second, short-lived, execution frame.

Therefore, these approaches can allow a better performance in cases of frequent frame switches in and out of frames with relatively short lifetime.

Execution contexts can for example be different processes executed by the processing element (where each process can for example be a given application, operating system or supervisor running on the processing element). In some cases, one could consider mapping different sub-parts of a given process to different execution contexts. For example, different address ranges within a given program could correspond to different execution frames, or execution frame split instructions included in software code could be thought of as marking the points at which there is a switch from one execution frame to another . In other examples, a group of software processes executed by the processing element could be considered as a whole to be part of a single execution framework. Also, in some cases, corresponding threads executed by processing circuitry that correspond to the same process, or a subset of threads among multiple threads, could be considered an execution context. Accordingly, it will be appreciated that the exact manner in which a number of software workloads may be divided into execution contexts may vary from implementation to implementation.

TAGE branch predictor with Perceptron predictor as transition predictor

A TAGE (tagged geometric) branch predictor is a common form of branch predictor used to predict the results of branch instructions. A number of different variations of a TAGE branch predictor are available, but in general the TAGE branch predictor may have a number of TAGE prediction tables to provide a TAGE prediction of the result of a branch instruction, where each TAGE prediction table includes a number prediction entries trained based on previous branch command results. The TAGE prediction tables are searched based on an index determined as a function of a destination instruction address and a portion of the previous execution history that is indicative of the execution behavior of the previous instruction at the destination instruction address. The part of the previous execution history used to define the index has different lengths for different TAGE prediction tables of the TAGE branch prediction array. By tracking predictions for various lengths of past execution history, TAGE branch prediction is enabled to be relatively accurate since when there is a match to a larger pattern of past execution history then the result of the predicted branch instruction is more likely to be relevant with the current target address instruction, but nevertheless the TAGE branch predictor also has the ability to record predictions for shorter lengths of the previous execution history in case there is no match for a longer length of the previous execution history. Therefore, in general this could provide a better branch prediction performance than alternative branch predictors which identify only a length of previous execution history.

A TAGE branch predictor typically also includes a transition predictor which provides a transition prediction for the result of a branch instruction in the event that the search in the TAGE prediction tables fails in all TAGE prediction tables. In some examples, in addition to using the transition prediction when the search fails, the transition prediction could also be used if the confidence in the prediction result from one of the TAGE prediction tables is less than a given threshold limit. In conventional TAGE branch predictors, the transition predictor is implemented as a binary predictor, which provides a number of 2-bit confidence counters that track whether a branch should be predicted with high confidence when followed, predicted with low degree of confidence when followed, to be predicted with a low degree of confidence when not followed, or to be predicted with a high degree of confidence when not followed. Although the bi-root predictor is usually much less accurate than the TAGE predictors after the TAGE predictors are properly trained, providing the bi-root predictor as a transition predictor to handle cases where the TAGE predictors have not yet reached a sufficient level trust, can be useful for improving performance.

However, most existing branch predictor designs are designed to optimize performance in a steady-state condition when the branch predictor is already fully warmed up, i.e. when sufficient training of the predictor state has already taken place based on the results of previous branch instructions, so that to ensure that forecast provisions can be relatively accurate. However, the inventors recognized that, increasingly, frame switches between different execution frames are becoming much more frequent in typical processing systems and therefore a larger fraction of the total processing time is spent in a transient state in which the branch predictor is still adapting to a new execution context after a recent context switch.

Also, recent disclosures have identified a class of security attacks based on hypothetical side channels, which in some variations can use the training of the branch predictor based on a first execution framework as a means of tricking a second execution framework into leaking sensitive non- accessible in the first execution context. This is because in some branch predictors it is possible to access a branch predictor state entry assigned to the branch predictor based on the branch history observed in an execution context by a different software workload and use them to predict the results of the branches of this different software framework. Previously, such use of the branch prediction state by one framework to predict results in another framework would simply be seen as a performance issue, as in the case where the second framework tries the wrong entry of the branch prediction array assigned by a first frame then any misprediction resulting from this can be recognized later and resolved once the true branch result is known and this would simply be expected to cause a delay in processing the correct branch result, but not expected to cause a risk in security.

However, it has been recognized that instructions that are hypothetically executed incorrectly due to intra-branch misprediction may nevertheless affect data in a cache or other non-architectural storage structure used by a data processing device. This could be exploited by an attacker and try to gain some information about potentially sensitive data that the attacker does not have access to but another execution framework does which can be tricked by the attacker into executing commands designed to access the secret and cause changes to the cache allocation that reveal some information about the secret to the attacker. For example, an attacker could train the branch predictor with a pattern of branch accesses so that when the victim execution context later accesses the same entry then it will incorrectly execute an instruction from an incorrect destination address or follow an incorrect prediction whether or not a branch is followed, causing an inappropriate access to secret information. Cache timing side channels can then be used to investigate the implications of the false assumption for secret information leakage.

A possible countermeasure for such attacks may be to discard the branch prediction state by detecting a frame switch so that the incoming execution frame cannot make use of the previously trained branch prediction state derived from the outgoing execution frame. However, in this case the transient behavior of the branch prediction device when the branch prediction state has just been rejected may become more important than the steady state behavior.

In the techniques discussed below, a TAGE branch predictor is provided in which the transition predictor includes a perceptron predictor. The perceptron predictor includes at least one weight table for storing the trained weights based on the previous branching command results. The perceptron predictor predicts the result of the branch command based on a sum of terms, each term depending on a corresponding weight selected from the at least one weight matrix based on a corresponding portion of at least the destination command address and the previous branch history. A perceptron predictor would normally be treated as a completely different type of branch predictor than the TAGE branch predictor, which could be used by itself to provide a complete prediction of an outcome of a branch instruction. It would normally be used as the transition predictor in a TAGE branch predictor. However, the inventors have recognized that by using a perceptron predictor as the transition predictor of a TAGE branch predictor, this can provide a branch predictor which learns faster in the transition state soon after a frame switch and reduces the penalty of frame switches and branch predictor status discards, to improve performance and provide a branch predictor that can better cope with the demands placed on branch predictors in modern processing systems. Also, the perceptron predictor can provide better prediction accuracy per byte of stored data, which makes it more suitable for systems with limited available space.

A selection circuit may be provided to select between the transition prediction provided by the transition predictor and the TAGE prediction provided by the TAGE prediction tables depending on a confidence value indicating a level of confidence in the TAGE prediction. The confidence value may be derived from the TAGE prediction tables by the search circuit which searches the TAGE prediction tables. That is, each prediction entry of the TAGE prediction tables may specify, not only a take or no-take prediction, but may also specify a level of confidence in the correctness of that prediction (the same enumerator may indicate both the predicted outcome and the trust). The confidence cues from the TAGE prediction matrices themselves thus influence whether transition prediction from the perceptron or TAGE prediction based on the TAGE prediction matrices is used. In some examples, the perceptron predictor may also produce a confidence indication (eg, the value before applying a threshold function) which could also contribute to the decision to choose between the transition and TAGE predictions.

The selection circuit may select the transition prediction when the search fails in all TAGE prediction tables or when the confidence value associated with the TAGE prediction indicates a confidence level lower than a threshold limit. In some cases these events can be compared in a comparison, since the case where the search fails in all TAGE prediction tables can be treated as if the confidence value is 0. Therefore, although the main TAGE prediction may be preferred in most cases, the transition prediction arrangement provides a backup option in case the primary TAGE prediction is unsuitable.

If the search succeeds in at least one TAGE prediction table, the TAGE prediction may include a prediction based on an indexed entry of a selected TAGE prediction table, where the selected TAGE prediction table is the prediction table for which the index is determined based on the largest portion of the previous branch history among the TAGE prediction tables that were successful in the search. Accordingly, if there is a hit on a first TAGE prediction table corresponding to a pointer derived from a first length of execution history and a second prediction table accessed based on a pointer derived from a second length of the previous execution history which is greater than the first length, then the array corresponding to the index derived from the second run history length would be used to provide the TAGE prediction.

The total size of the branch prediction state stored by the perceptron predictor is smaller than the total size of the branch prediction state stored by the majority of TAGE prediction arrays. Therefore, if the perceptron predictor is used as the transition predictor which provides a transition in the event that the TAGE prediction tables fail to provide an appropriate level of confidence in the prediction, then it is not worth the burden of a larger area/power cost for the providing a particularly large perceptron prediction array. A relatively small perceptron prediction array may be sufficient to provide a relatively significant performance improvement in transient operation as discussed above. Providing a relatively small perceptron prediction array can also reduce the time overhead of storing and restoring branch prediction state as discussed below.

The TAGE branch predictor may have control circuitry responsive to an execution frame switch of a processing element from a first execution frame to a second execution frame to prevent the TAGE branch predictor from providing a branch prediction for an instruction of the second execution frame based on the branch prediction state trained based on the commands of the first execution frame. In this way the effects of hypothetical side-channel attacks of the form discussed above can be reduced.

The TAGE branch predictor may have a branch prediction store circuit responsive to a branch prediction store event for storing information in a branch state buffer according to at least a portion of the at least one weight table of the perceptron predictor and a branch prediction reset circuit responsive to a branch prediction reset event associated with a given execution context to reset at least a portion of the at least one weight matrix of the perceptron predictor based on information previously stored in the branch state cache. Storing the active state in the branch state buffer and later restoring it to the perceptron predictor can ensure that even if the active state is rejected by the perceptron predictor in an execution frame switch as discussed above to deal with hypothetical side-stepping attacks channel, on returning to a given execution context some branch predictor states can be reset for that context, to reduce the loss in performance caused by preventing a prediction state trained by an execution context from being used by commands from a another execution context. Essentially the save and restore functions allow the incoming frame that follows the execution frame to start from a partially warm state of the branch predictor.

It has been found that storing the entire set of branch prediction states across the entire TAGE branch prediction array as a whole (including the TAGE prediction tables) in the branch state cache can require a relatively large amount of storage space in the branch state cache, which can may not be acceptable for some limited area processor designs. In practice, the perceptron predictor provided as a transition predictor can provide a greater level of performance gain per unit of stored data and by storing at least a portion of the state of the perceptron predictor in the branch state cache in response to the save prediction event branch (but not the state storage from the TAGE prediction tables), this can reduce the amount of storage capacity required for the branch state cache, to limit area costs while still providing a reasonable level of transient state performance operation after a frame switch as discussed above.

In a system that supports saving and restoring state from the perceptron predictor, some examples may apply compression and decompression to the store and restore respectively, so that it is not necessary to store the weight tables (or any other state of perceptron) to the state cache in exactly the same form as they are stored within the perceptron itself.

The branch prediction save event associated with the given execution context could include one or more of the following:

• the execution frame switch, for which the given execution frame is the first execution frame;

• the transition of the given execution context from the processing element to another processing element,

• the passage of a predetermined period since a previous branch forecast storage event;

• detecting or executing a branch prediction store instruction within the given execution context, and

• an update of the active branch prediction state that satisfies a predetermined condition that occurs during the execution of the given execution context.

Therefore, in some cases the prediction state may be stored in the branch state buffer in response to the execution frame switching itself or in response to the transition of a frame from the processing element to another processing element. However, it may also be possible to cache the active branch prediction state associated with a given execution context in the branch state cache periodically during the processing of the given execution context so that fewer state saves are required during execution context switching, which which can improve performance. For example, a state could be periodically stored in the branch state cache or in response to an update of the active branch prediction state that satisfies some predefined condition (eg, a change that results in greater than a threshold confidence level). . Also, in some cases a state prediction save instruction may be defined which when included in the software of the given execution framework can trigger the branch prediction storage circuitry to store the currently active branch prediction state (with compression if necessary) to branch state cache.

Similarly, the branch prediction reset event associated with a given execution context may include one or more of the following:

• execution frame switching, for which the given execution frame is the second execution frame,

· the transition of the given execution context from another processing element to the processing element associated with the branch predictor for which the state is reset;

• the passage of a predetermined period since a previous industry forecast reset event, and

· the detection or execution of a branch prediction reset command within the given execution context.

Execution contexts can for example be different processes executed by the processing element (where each process can for example be a given application, operating system or supervisor running on the processing element). In some cases, one could consider mapping different sub-parts of a given process to different execution contexts. For example, different address ranges within a given program could correspond to different execution frames, or execution frame split instructions included in software code could be thought of as marking the points at which there is a switch from one execution frame to another . In other examples, a group of software processes executed by the processing element could be considered as a whole to be part of a single execution framework. Also, in some cases, corresponding threads executed by processing circuitry that correspond to the same process, or a subset of threads among multiple threads, could be considered an execution context. Accordingly, it will be appreciated that the exact manner in which a number of software workloads may be divided into execution contexts may vary from implementation to implementation.

In cases where saving and restoring perceptron predictor states is used, then during an initial period following the branch prediction reset event, there may be a phase where, although the perceptron predictor has warmed up from the reset state industry prediction, TAGE prediction tables can still provide relatively low confidence predictions as they may previously have been disabled or rejected. Accordingly, during an initial period following the branch prediction reset event, the selection circuit for selecting between the TAGE prediction and the transition prediction may be configured to select the transition prediction provided by the transition prediction device. During this initial period, the TAGE prediction tables may still be updated based on the results of the branch instructions, despite the fact that these entries are not used at that time to actually predict the results of the branch instructions. Therefore, gradually during the initial period confidence in the TAGE forecast may increase as the TAGE forecast tables are trained based on actual industry results. In some examples the initial period may correspond to a fixed duration regardless of the level of confidence achieved by the TAGE predictions. For example the initial period could be one of: a predetermined length of time after the branch prediction reset event, a predetermined number of processing cycles after the branch prediction reset event, a predetermined number of commands processed after the branch prediction reset event, a predetermined number of branch instructions processed after the branch prediction reset event or a predetermined number of searches performed by the seek circuit after the branch prediction reset event. Alternatively, the size of the initial period could be varied based on the confidence level achieved by the TAGE forecast. The initial period may end once a confidence level in the TAGE forecast exceeds a predetermined level.

The TAGE branch predictor discussed above (including the main TAGE prediction tables and the perceptron predictor provided as a transition predictor for the TAGE branch predictor) can be used to predict the results of branch instructions processed by a first processing element within a data processing device.

In some examples the device may also have a second processing element that has a second branch predictor for predicting the results of branch instructions processed by the second processing element. This second branch predictor could have a different design than the TAGE branch predictor used by the first processing element. For example, in a device that provides heterogeneous processor cores with different levels of performance and energy efficiency, a more energy-efficient (but less powerful) processing element may use a simpler form of branch predictor than the TAGE branch predictor used by a more performance oriented, but less energy efficient, processing element.

In some examples, the second branch predictor may include a perception predictor that corresponds in design to the transition predictor of the TAGE branch predictor. For example the second branch predictor could have exactly the same configuration of weight tables (same number of tables and same size of tables) as the transition predictor of the TAGE branch predictor used by the first processing element. This can make the execution frame transition between the first and second processing elements much clearer since it is possible to simply copy all perceptron states (including the weight matrices) when transitioning an execution frame between the first processing element and the second element processing, which can reduce the performance impact of frame switching. When transitioning an execution frame from the second processing element to the first processing element, then while the at least one weight table may be transferred from the second branch predictor to the transition predictor of the first branch predictor, the TAGE prediction tables may be initialized in initial values which are independent of the state of the second branch predictor. This can be similar to the case where, after a state reset event, the TAGE branch predictor is initialized to default values since its state has not been cached in the branch state memory. On the other hand, when an execution frame transitions from the first processing element to the second processing element, then while the at least one weight table may be transferred from the transition predictor (perceptron predictor) of the first branch predictor TAGE to the second branch predictor, the TAGE prediction tables of the TAGE industry predictor may be invalidated or disabled.

Examples

Figure 1 schematically illustrates an example of a data processing device 2 with a processing pipeline comprising a number of pipeline stages. The pipeline includes a branch predictor 4 for predicting the results of branch instructions and generating a sequence of present addresses of the instructions to present. A fetch stage 6 fetches the commands identified by the fetch addresses from an instruction cache 8. A decode stage 10 decodes the fetched commands to generate control information to control subsequent pipeline stages. A renaming stage 12 performs register renaming to map the architectural register specifiers specified by the instructions to physical register specifiers that specify the registers 14 provided in the hardware. Renaming registers can be useful to support out-of-order execution as this can enable de-risking between instructions that specify the same architectural register by mapping them to different physical registers in the hardware register file to increase the probability that the instructions will execute in a different order than their program order in which they were fetched from cache 8, which can improve performance by allowing a later instruction to execute while an earlier instruction is waiting for an operand to become available. The ability to map architectural registers to different physical registers can also make it easier to restore the architectural state in the event of an incorrect branch prediction. An issue stage 16 queues the instructions awaiting execution until the required operators to process those instructions become available in the registers 14. An execution stage 18 executes the instructions to perform the corresponding processing operations. An asynchronous write stage 20 again writes the results of the executed instructions into the registers 14.

The execution stage 18 may include a number of execution units such as a branch unit 21 for evaluating whether branch instructions have been correctly predicted, an ALU (arithmetic logic unit) 22 for performing arithmetic or logic operations, a floating point 24 for performing operations using floating point operators and a load/store unit 26 for performing load operations to load data from a memory system into registers 14 or store operations to store data from registers 14 into the memory system . In the present example the memory system includes a level one instruction cache 8, a level one data cache 30, a level two cache 32 which is shared between data and instructions, and a main memory 34, but it will be appreciated that this is simply an example of a possible memory hierarchy while other implementations may have further cache levels or a different layout. Memory access may be controlled using a memory management unit (MMU) 35 to control address translation and/or memory protection. The load/store unit 26 may use a translation lookaside buffer (TLB) 36 of the MMU 35 to map the virtual addresses produced by the pipeline to physical addresses specifying locations within the memory system. It will be appreciated that the pipeline shown in Figure 1 is simply an example while other examples may have different sets of pipeline stages or execution units. For example, an in-line processor may not have a rename stage of 12.

The branch predictor 4 may include structures for predicting various results of branch instructions. For example the branch predictor 4 may include a branch direction predictor which predicts whether or not the conditional branches should be followed. Another component of branch results that can be predicted can be a branch's target address. For example, some branch instructions calculate the target address indirectly based on values stored in registers 14 and thus may branch to addresses that are not deterministically known by the program code itself. The branch target buffer (BTB) (also known as the branch target address cache (BTAC)) may be a portion of the branch predictor 4 which has a number of entries each of which provide a prediction of the target address of each branch that occurs within a given instruction group. Optionally the BTB or BTAC may also provide other branch information, such as a prediction of the specific branch type (eg, function call, function return, etc.). Again, the predictions made by the BTB/BTAC can be refined based on the actual branch results 44 determined for the executed branch instructions by the execution stage branch unit 21 .

The processing pipeline shown in Figure 1 can support the execution of a number of different software workloads (execution contexts). Software workloads could include different processes executing according to different program code, or they could include multiple threads corresponding to the same process. Also, in some cases different parts of a process could be considered as different workloads, for example some address ranges within the process could be marked as a separate workload.

When different processes are running on the same pipeline, usually branch predictor 4 is shared between those processes. Since different processes may have different branch behavior at the same instruction address, this may mean that searching the branch predictor structures for a given instruction address could provide a predicted behavior that may not be relevant to a process because it has been trained based on another procedure. Typically, incorrect branch predictions caused by a process accessing a branch prediction entry that was trained by another process would simply be considered a performance-affecting issue rather than a security issue, since if the prediction is incorrect then this will be detected when the branch is actually executed on branch unit 21 and then the branch unit can trigger the pipeline to reject subsequent instructions that are incorrectly served based on the incorrect prediction, while the processor state can be reset to the last correct state resulting from the last correctly predicted command.

However, while the architectural effects of a misprediction can be reversed, the misprediction can cause longer-lasting effects on micro-architectural state such as the data cache 30 or the TLB 36. It has recently been recognized that it is possible for an attacker to exploit the prediction arrangement. branch 4 to gain access to secret information that the attacker should not have access to. The memory management module 35 may implement a privilege scheme to allow only processes running at certain privilege levels to access certain areas of memory. For example, some secret data may not be accessible to the attacker's process (e.g., because the attacker's process is running at a lower privilege level), but may be accessible to a process running at a higher privilege level such as an operating system or a supervisor. Secret data can be any data that is considered sensitive, such as a password, personal financial information, etc. The attack can be based on training the branch predictor 4 so that a branch within the victim code running on a more privileged state of the processor branching to some contrived code that the most privileged victim code should not be executing, but is executing incorrectly due to an incorrect branch prediction in a branch of the victim code unrelated to the secret. Deception code can be designed by the attacker to access a memory address that is computed based on the secret data, so that the data (or other information such as TLB entries) associated with a memory address that depends on the secret data to be loaded into one of the caches 30, 32, 36, 42 of the data processing system. The loaded address can then be deduced through cache timing analysis, and this can enable the secret information to be deduced.

A possible countermeasure for these types of attacks might be to discard the branch prediction state from the branch predictor every time an execution context switch occurs, but this approach can come at a cost, because every time a given process returns for a another execution slot may then have to infer its branch prediction state from scratch again, which can cause many additional mispredictions that impact performance.

As shown in Figure 1, the overhead of dealing with the attacks discussed above can be reduced by providing the branch predictor 4 with a branch state buffer (BSB) 40 in which the branch prediction state from the main state store can be stored forecast 42 (used by the branch forecaster 4 to store the active state used to generate the actual branch forecasts) and from which previously saved states can be restored to the forecast state store 42. The active branch forecast state in prediction state store 42 is trained based on actual branch results 44 determined by branch unit 21. In response to various state save or restore events, state may be stored from the prediction state store 42 in BSB 40 or restored from BSB 40 to prediction state storage 42. BSB 40 may tag the stored portions of the states with an identifier of the execution context associated with that state so that, on a reset event associated with a given execution context, the state that is relevant to that context be reset to avoid making predictions from one execution context based on the state trained by another execution context. When switching an execution frame indicated by signal 46, the active prediction state in the prediction state 42 associated with the outgoing execution frame may be discarded, invalidated, or disabled in some way to prevent it from being used to make predictions for the incoming frame, while state reset by BSB 40 can be used to reduce the performance impact of this discard.

Figure 2 shows an example of the branch predictor 4 in greater detail. The example of Figure 2 applies to a branch direction predictor for predicting whether or not branches are followed, but it will be appreciated that similar techniques could be used for a branch target address cache or BTB. The branch prediction device 4 may comprise a number of prediction device units 50, 51 which provide different predictions, based on different prediction methods. For example, predictor modules can include a main predictor (for example, a TAGE predictor 50 ), as well as additional predictor subarrays 50 which can provide predictions for specific scenarios, such as detecting branches involved in loops. The TAGE predictor 50 may itself include multiple predictor units 51, such as tagged history geometric matrices (TAGE) used to generate a master predictor and a transition predictor (also referred to below as a base predictor) used to providing a transition prediction in case the TAGE tables fail to provide a suitable prediction. The transition predictor could be a bistable predictor or a perceptron predictor as discussed below. In general, each of the prediction arrangement units 50, 51 is searched based on the search information which is derived as a function of the program counter (PC) which represents a target instruction address for which a prediction is required and /or the previous execution history which represents a history of execution behavior leading to the instruction associated with the address of the program counter. For example the execution history could include a sequence of fetch/no fetch pointers for a number of branches leading to the instruction represented by the program counter or portions of one or more addresses of previously executed instructions, or it could represent a stack call history representing a sequence of function calls that resulted in the instruction represented by the program counter. The execution history could also include an indication of how early the branch was previously answered (eg, number of commands interjected or branch commands interjected). By looking at some aspects of the history leading to a given program counter address in addition to the address itself, this can provide a more accurate prediction of branches that may behave differently depending on the sequence of previous execution. The various predictor units 50, 51 may examine different portions of the search information to determine the prediction. A selector 52 may then choose between the alternative forecasts provided by each forecasting unit, depending on a level of confidence in those forecasts and/or other factors. For example, the transition predictor could be selected in cases where the primary TAGE predictor fails to provide a sufficiently high confidence prediction.

Each of the predictor units 50, 51 may store some prediction state which may be used to make predictions for the compared branch context represented by the search information. For example, each predictor unit may include an array which is indexed based on a function of portions of the lookup information. The function used to generate the index may differ for the respective prediction array units 50, 51. The entire set of branch prediction states stored in each of the prediction array units 50, 51 may collectively be considered as the storage space of branch predictions 42 of branch predictor 4. It will be appreciated that the selector shown in Figure 2 is simplified and in practice may consider a number of factors to determine the predictor unit to be used as a basis for predicting the actual output branch.

As shown in Figure 2, a reject/disable control circuit 54 may be provided to control the various branch predictor units 50, 51 to reject or disable portions of the active state of branch predictors when an execution frame switch is detected. Frame switching could be detected based on a number of signals within the processor pipeline shown in Figure 1. When processing switches between execution frames then a signal 46 is provided to branch predictor 4 from any detectable element of the pipeline. of frame switching. For example presentation stage 6 could recognize that instruction presentation addresses have reached a program instruction address which marks the boundary between different frames, or decoding stage 10 could detect that a frame separation instruction has been answered and inform the layout branch prediction for frame switching. Also, the execution stage 18 could flag the frame switch when detected and signal it to the branch predictor 4. Also in some cases the frame switch may be triggered by an interrupt or an exception and in this case the switch signal 46 can be signaled by an interrupt controller. Regardless of the source of the switching signal 46, in response to the switching signal 46 the branch prediction store 42 may cancel entries. Therefore, this prevents any content of the prediction units 50 which were trained on a previously executed frame from being used for the new frame after the execution frame is switched.

Either in response to the execution frame switching itself, or periodically during the execution of a given execution frame, a state storage circuit 56 may compress at least a portion of the branch prediction state stored in branch prediction storage 42 and allocate the compressed state to a branch state cache 40. In response to a state reset event, the previously stored branch prediction state may be unzipped from the branch state cache and restored to the branch prediction store 42 by a state reset circuit 58. The store events and reset states could be triggered by a range of events such as the execution of specific commands used to trigger the save or reset for the branch predictor, the elapse of a given time or a certain number of processing cycles from since the last state save or restore, or making a specific update of the branch prediction state that satisfies a condition (such as reaching a given confidence level) so that it is desirable to store a portion of that branch prediction state in the branch state cache 40 to allow it to be reset later if required when the same execution box is executed again. This can help improve performance by reducing the discard cost when an execution frame switch is answered.

Figures 3 through 6 show a number of ways to perform compression after saving state and decompressing after restoring state. For example, Figure 3 shows how a horizontal compression may be applied to a number of branch prediction entries 60 in a given unit of the branch prediction array units 50, 51 . In this example branch predictor registers 60 are shown as binary predictor registers which provide 2-bit confidence counters for tracking receive/no-receive confidence. Bit 1 of the 2-bit counter may for example indicate whether the outcome should be predicted to have followed or not followed and bit 2 may indicate whether the strength of confidence in that prediction of take or no take should be interpreted as strong prediction or weak prediction (eg 11 could indicate strong sequence, 10 weak sequence, 01 weak non-sequence and 00 strong non-sequence). In one example, the state storage circuit 56 may apply a compression so that one of the bits of each counter is discarded to compress the value of the prediction state of a given entry 60 into a compressed value with fewer bits.

Although Figure 3 shows an example in which horizontal compression is applied to a bistable prediction array entry, it could also be applied to other types of branch prediction entries. For example in a perceptron prediction device, at least one weight table may be provided and compression could reduce the number of bits representing the weight from a larger number to a smaller number to reduce the resolution at which the weights are represented . When restoring a compressed state previously stored in branch state cache 40, a decompression may be applied where the value being restored is chosen as a function of the compressed value. For example, bits that were not discarded during compression can be reset based on the values stored in value state buffer 40, while any other bits of each branch prediction entry that were discarded during compression can be set to some value X which can be determined based on the compressed data or could be set to a default value. For example, with a bistable prediction arrangement the default could be that bit 2 is set to whatever value indicates that the receive/no-receive prediction denoted by bit 1 is strongly predicted (e.g. with the above encoding, bit 2 could be set to the same value as bit 1). Other approaches could instead initialize each entry as weakly predicted (eg by setting bit 2 to the opposite of bit 1). Another approach could be to set bit 2 to the same value (either 1 or 0) in all entries regardless of the prediction implied by bit 1. Therefore, although compression and decompression may result in the prediction from rollback not having the same level of confidence as was present before the state data was compressed, this may make it possible to reduce the storage capacity of the overall state cache 40 and thus reduce the implementation overhead of the storage and of the rollback while making a performance improvement over the case where no state was saved.

As shown in Figure 4 another example of compression may be to apply a vertical compression to reduce the number of entries stored in the branch state cache compared to the number of branch prediction entries 60 provided in the original prediction state store 42. Again, Figure 4 shows an example for a bistable prediction array but it will be appreciated that similar techniques could also be applied to tables that provide other types of branch prediction states. In this case, compression may merge a group of entries 62 into a single entry 64 in the compressed branch prediction state. For example, the merge could be performed by selecting the branch prediction value stored in a selected entry from the group of entries 62 and recording that value as the merged entry 64. A more sophisticated approach could be to check the values of each entry from the group of entries and determining the most common value represented by those group entries (eg, by majority vote) and then setting the merged entry 64 to the value obtained from the majority of the individual entries 60 in the group 62. After decompressing the state stored in the branch state buffer 40, then each of the individual entries 60 in the same group 62 could be set to the same value as indicated by the merged entry 64 of the compressed state. Again, while this may introduce some level of inaccuracy relative to the initial state, this still allows for improved performance compared to the case where no state is stored. This approach recognizes that often branch behavior can be relatively similar for a number of entries, and thus the loss in performance associated with not representing each of these entries in the branch state cache can be relatively insignificant. Although Figure 4 shows an example in which four adjacent entries 60 of table 42 are merged into a single merged entry 64, this is not necessary and the group of entries merged into a single compressed entry could be in non-contiguous positions within the table . This can be advantageous because it is common in branch prediction arrangements for the sharding algorithm used to create the table index to map nearby branch addresses to discrete enough areas of the table to reduce hotspots and thus branches which might be expected to behave similarly could be represented by entries in non-adjacent positions in the table.

Figure 5 shows another example of compression and decompression. In some branch prediction devices it is possible for each branch prediction entry 60 to provide a branch prediction state value which includes a hidden part 70 which is specified separately for each entry and a shared part 72 which is specified once for an entire group of entries 62 to be shared among the group. This can reduce the overhead of the main prediction store 42. Again, Figure 5 shows an example applied to a bistable predictor, but in a similar way the weights in a weight matrix of a perceptron predictor for example could include such hidden and shared sections. In this case, the compression could include omitting the shared part 72 from the compressed state as shown in the case of Figure 5. After decompression, the shared part could be set to some default value X (0 or 1) or to a value chosen based on a function of the hidden portion reconstructed from the compressed state. It would also be possible, instead of skipping the shared part, to keep only the shared part and skip the hidden part 70.

Also, as shown in Figure 6, compression could introduce such sharing of a portion of a prediction value between entries corresponding to separate index values, which could then be removed again after such compression. For example, in Figure 6 a group of entries 62 includes separate values for both bit 1 and bit 2 of the bit counter, but after compression to create the state stored in BSB 40, although bit 1 is represented separately for each one of the entries in a hidden portion 76 of a given entry 78 of the compressed state, the second bit of each entry 60 in the group 62 is merged to form a single value X represented as the shared portion 79 of the compressed branch prediction state 78. For example the shared value X could be set to any of the values E to H of bit 2 in the initial state entry group 62 or it could be set to the value obtained from the majority of the second bit E to H in this group 62. Then decompression the shared value 79 could simply be copied to the corresponding part of each entry 60 in the group 62 when the active state n is referred based on the compressed state stored in BSB 40. Again although Figure 6 is applicable to a bistable prediction array, a similar approach can be applied to other array formats providing various types of branch prediction states.

So, in general by applying compression and decompression after saving and restoring state, this can significantly reduce the overhead to make such saving and restoring more practical. Another approach to compression and decompression may be to omit the state for a given prediction unit 50 from the compressed state stored in the branch state cache 40. For example the save and restore may only apply to the associated state with the transition predictor, while the state associated with other predictors could simply be discarded or disabled on a frame switch without implementing any saving or restoring state. This recognizes that the transition predictor 50 can often provide the greatest level of performance improvement per bit of information stored as a branch prediction state, as shown in the graphs discussed below.

In examples that apply compression and decompression resulting in a transform format in which the branch prediction state entries 60 are represented, it may be preferable to provide a physically distinct branch state cache 40 separate from the branch prediction storage 42 n which provides the active branch prediction state so that BSB can be smaller than the branch prediction store.

However, in other examples the branch state cache 40 may be efficiently implemented using a portion of random access memory (RAM) which is used in conjunction with the branch prediction store 42 which provides the active branch prediction state. For example as shown in Figure 7, a RAM can be provided which has sufficient space to store a given set of active branch state predictions as well as a number of backup slots which can be used to provide multiple snapshots of the branch state cache 40 which can be used to store the saved branch prediction states for a number of different execution contexts. In this case saving and restoring the branch prediction state could be done simply by switching the regions 90 of the RAM used to provide the active state used as the branch prediction store 42 to generate branch predictions for the frame that executed at that time and of the areas used as BSB 40 to store the previously saved state which is no longer updated based on the results of actually executed branch instructions, but is retained so that if the corresponding execution frame is executed again later then this state it can be reset by switching the region 90 which represents the active state. This allows the incoming execution frame to continue with a partially warm branch prediction layout. It will be appreciated that the approach shown in Figure 7 could be applied to one of the types of predictors such as the transition predictor, but need not be applicable to other types of predictors 50, 51 . The approach shown in Figure 7 can reduce the amount of state transfer required, simply by designating areas of the total storage capacity as active or inactive, and this can be sufficient to record the area that should be used to perform the existing provisions. The state associated with a previously executed execution frame in one of the regions 90 which is currently being used as BSB 40 may remain in the global branch prediction store until another execution frame is executed which has not already allocated one of the regions 90 in this execution context and therefore this may require overwriting the state for a previously executed execution context. Each region 90 for example may be associated with an identifier of the particular execution frame associated with the corresponding branch prediction state, to allow decisions as to whether an incoming execution frame already had branch prediction states saved or needs to start over .

As shown in Figure 8, when the processing pipeline switches between different execution frames, sometimes a given execution frame may run for a longer period than other times. If a given execution frame runs for a relatively short time, and then the processor returns to the same execution frame it was executing before the short execution frame, then it may be desirable to re-enable any previously active branch prediction state for continuing execution frames. For example, in Figure 8 execution frame B runs for a relatively long time and thus can accumulate a set of branch prediction states which can be relatively efficient, but then for a short time a different execution frame A executes before returning in execution frame B. For the parts of the branch predictor for which state save and restore 56, 58 is supported, it may be relatively simple to restore the state associated with execution frame B. However, for other parts of the predictor branch, such as prediction array units 50 for which no state is saved or restored, if that prediction state is discarded from the main branch prediction store 42 on each execution frame, this would mean that such a state would have to be trained again from the beginning when it resumes execution frame B. This can be if desired. Figures 9 and 10 show different techniques that allow the non-stored part of the branch prediction state associated with execution frame B to be preserved for at least one execution period by execution frame A, in case execution frame A lasts for a relatively short period and then the state associated with frame B may still be available when processing returns to frame B.

As shown in Figure 9, in some approaches the branch predictor may have no indication of whether execution frame A is likely to be long or short-lived. In this case, for an initial run period of 100 at the beginning of the period allocated for run frame A, some parts of the branch predictor 4 may be disabled. For example these disabled sections could be the prediction device units 50, 51 whose state is not stored in the branch state buffer 40 by the state storage circuit 56. For example, these could be the main prediction device sections and of the provision sub-provisions other than the transition provision provision. The branch prediction state associated with these disabled portions of the branch predictor that was trained based on execution frame B commands may be retained in these prediction stores during the initial period 100 of execution frame A. As long as these portions of the branch predictor are disabled this means that it is not possible for branch predictor 4 to make predictions of the results of branch instructions of execution frame A based on the previous branch prediction states associated with execution frame B, so there is still protection against attacks side channel as discussed above.

If a subsequent execution frame switch occurs before the end of the initial period 100, (eg in the case shown in Figure 8), then if execution switches back to frame B then the previously disabled portions of the branch predictor can simply be activated again as long as the branch prediction state associated with frame B still exists in those parts of the branch prediction arrangement. This means that once box B resumes it can do so from where it left off with the performance level associated with the previously trained branch predictor state. This reduces the performance impacts of frame B caused by temporary switching to frame A.

On the other hand, in the case shown in Figure 9 where the initial period 100 ends without encountering any subsequent execution frame switching, then at the end of the initial period, the branch prediction state associated with those disabled portions of the branch prediction device (such as the main branch predictor and its predictor sub-arrangements) can be dropped or invalidated, and then previously disabled sections of the branch predictor can be re-enabled so that execution context A can start using those sections. This means that during the initial period 100, the predictions for execution frame A may rely solely on the transition predictor 51 whose state has been stored in the branch state buffer 40, but once the initial period is over then the full branch prediction function can to be available in frame A. Although this approach may initially reduce performance for an incoming frame by not making the entire branch predictor available, it has the advantage that when a particular execution frame has a short lifetime and processing returns to frame which was executed before the short-lived frame, the longer-lived execution frame B can be handled more efficiently, which will tend on average to increase performance overall. The initial period 100 could be of fixed duration (defined in units of time, processing cycles, executed orders or branch prediction layout lookups, for example) or could be of variable duration (eg, until the confidence of the branch prediction reaches a certain level).

Alternatively, as shown in Figure 10, instead of limiting the operation of execution frame A during the initial period in response to frame switching from frame B to frame A, the branch predictor could make a prediction of the frame's expected lifetime A. For example a table could be maintained with a confidence counter or prediction value that was trained based on previous measurements of the lifetime of frame A and the lifetime (duration) of frame A is expected to be greater than a certain threshold value then it may be assumed that it is not worth keeping the unstored prediction state associated with frame B (other than the prediction state stored in branch state cache 40). In this case, when frame A is predicted to be long-lived, the unstored portion of frame B's prediction state may be discarded from branch prediction storage 42 and the entire branch prediction array together with all prediction array units 50 , 51 may be triggered to make predictions for frame A immediately from the start of processing by frame A, rather than waiting for the end of the initial period 100.

If instead frame A is predicted to have a short lifetime (with a duration less than a threshold value), then in response to frame switching from frame B to frame A the portion of the branch predictor corresponding to the state which is not cached branch states can be disabled and the state associated with the disabled part which was trained based on commands from frame B can be maintained throughout processing in frame A. Therefore with this approach the disabled parts would remain disabled until another frame switch occurs and processing returns to a different frame.

Accordingly, regardless of the approach used in Figure 9 or Figure 10, generally as shown in Figure 8, if there is any residual active branch prediction state recorded in the main branch prediction storage 42 associated with an incoming frame B at time of a frame switch from an outgoing frame A, then this residual active branch state can be reactivated so that it can be used to make branch predictions for the incoming frame B without requiring any state to be restored from the branch state cache. This can be particularly useful for any portions of the prediction state that are not included in the compressed image of the branch prediction state stored in the branch state cache 40 .

Figure 11 shows an example design of the branch predictor 4 which can provide improved performance in the transition state immediately after the branch prediction state is discarded in response to an execution frame switch. Branch predictor 4 is implemented as a TAGE branch predictor which uses a relatively small perceptron predictor 120 as a transition predictor which provides a transition prediction in case the main TAGE prediction tables 122 cannot provide a sufficient level of confidence. The total amount of prediction states is smaller for the perceptron predictor 120 than for the TAGE arrays 122. The TAGE 4 predictor may also include additional structures such as a loop predictor 140 for detecting program loops and a statistical corrector 142 for the correction of previously detected incorrect predictions in the main predictor.

Both the TAGE master prediction tables 122 and the perceptron 120 are searched based on search information derived from the program counter (PC) and execution history information 124 indicating a sequence of behavior that led to the command represented by the counter program. For example history 124 may include a sequence of bits indicating past branch history, such as a sequence of received and unreceived results for previously executed branches. It will be appreciated that different TAGE schemes may use different representations of history 124 and that any known TAGE search scheme may be implemented. In general, the history 124 may be divided into a number of segments (for example P0 to P3 in the example shown in Figure 11) while each TAGE table 122 may have its prediction entries indexed based on a segment of varying length of the value history 124. For example a first TAGE array 122 could be indexed as a function of the program counter and the PO segment, a second TAGE array 122 could be indexed as a function of the program counter and the PO and P1 segments, a third array TAGE could be indexed as a function of the program counter and the combination of sections PO, P1 , P2 and so on. Each TAGE table can provide a number of prediction state values, for example bistable confidence counters or larger counters that capture confidence at a lower resolution than the 2-bit bistable counter. When the TAGE arrays 122 are searched against the program counter and history 124 , then each array can output an indication of whether there was a hit, and if there was a hit, the prediction derived from that array and the associated confidence level with this prediction. A selector 126 may select among the different predictions output from the TAGE tables such that if each of multiple TAGE tables 122 outputs a prediction with a confidence level greater than a certain threshold value, then the selector 126 may select, as the prediction TAGE, the prediction output by the TAGE array 122 which used the largest portion of the history 124 to create the pointer to that TAGE array. This recognizes that if there was a coincidence in a longer history, then that prediction is more likely to be accurate than if there was a coincidence in a shorter history, since more information about the old execution behavior leading to the prediction has been considered in order to derive the prediction. current command represented by the program counter.

However, sometimes the TAGE tables 122 may not be able to provide an appropriate prediction of the current program counter and history 124, for example when an instruction is answered in a new script that was not previously detected. Therefore, sometimes each of the TAGE tables 122 may output a TAGE confidence which indicates a confidence lower than a certain threshold value. Also, in some cases the lookup may simply fail all TAGE tables (this may be interpreted as a confidence level of 0 or the minimum confidence level). The perceptron predictor 120 is provided as a transition predictor to provide a transition prediction in the event that the TAGE arrays 122 cannot provide a prediction with a sufficiently high level of confidence. Accordingly, when the TAGE confidence derived from the confidence indications stored in the TAGE tables 122 is not sufficiently high, the selector 126 may instead select the transition prediction output from the perceptron predictor 120 .

As shown in Figure 11, the perceptron predictor 120 includes a number of weight tables 130 each of which stores a number of weight values which can be used to multiply corresponding portions of the program counter and/or history value 124 (optionally weighting symbols of other information could also be considered) to produce a weighted sum using an adder 132. Again, a wide range of perceptron schemes are known in the literature which specify various ways of applying the weights to the various parts of the search information, but in generally the perceptron is a type of branch prediction device where the generated prediction confidence depends on the sum of a number of terms dependent on weights selected from matrices indexed by portions of the program enumerator and/or history 124. For example, each weight matrixmay be indexed based on a different portion of the search information so that the sum is produced based on terms each of which results from a weight selected from a different weight table 130. In some implementations the selected weights could be added directly so that provide a prediction indicating the take/no-take outcome and predicted confidence level. In other implementations the weights could be used to multiply corresponding parts of the search information, and the products of the weights and the search information can be summed to generate the prediction.

A perceptron predictor would normally be treated as a distinct type of predictor in its own right, rather than being included as a transition predictor 120 in a TAGE 4 predictor as shown in Figure 11. However, as discussed in the performance analysis described below, using a perceptron as the transition predictor of a TAGE predictor can be particularly useful in the scenarios discussed above where there are frequent discards of branch prediction states at execution frame switches. This is because the perceptron can, in a relatively small amount of a branch prediction state, provide a relatively high rate of performance boost when the perceptron state is reset from the branch state cache 40 after an execution frame switch or other reset event . Compared to a TAGE predictor which uses a bistable transition predictor, this can provide much higher performance in transient operation.

As shown in Figure 12, the TAGE 4 predictor of Figure 11 may itself be part of a larger hybrid predictor which may include an additional perceptron predictor 150. That is, the TAGE 4 branch predictor may further include the main TAGE arrays 122 and the perceptron 120 which acts as the transition predictor of the TAGE 4 branch predictor. The selector 126 within the TAGE 4 predictor can still select between the predictions between the TAGE arrays 122 and the transition predictor 120 based on a confidence indication 128 derived from the confidence value stored in the TAGE tables 122 themselves (and in some cases, a confidence indication 129 obtained from the perceptron predictor 120 may also be considered).

However, in addition a further selector 152 may then choose whether to use the prediction output 154 from the TAGE 4 branch predictor (which could be based on the TAGE tables 122 or transition predictor 120) or a further perceptron prediction 156 provided by a further perceptron predictor 150 which may be a more complex predictor than the perceptron used as transition predictor 120. Such hybrid predictors exhibiting multiple forms of branch prediction can be useful for improved performance in applications where space overhead is less important. However unlike the selector 126 within the TAGE 4 branch predictor, the selector 152 which selects between the TAGE 4 branch predictor and the perceptron predictor 150 may select one of the predictions 154, 156 based on a separate table 160 that indicates the preferred type of prediction array for a given combination of program counter and execution history, a fact independent of the TAGE tables 122. For example, the TAGE table 160 may be learned from an old evaluation of whether the perceptron prediction 156 or the TAGE prediction 154 is more accurate for some industries.

Therefore, the selector 152 may not consider the particular confidence indication 128 which is derived from the TAGE tables 122 themselves.

Flexibility of industry forecast provisions

Modern processors use branch prediction to improve system performance. Consequently, prediction devices have become larger and more sophisticated to achieve higher accuracy. However, due to the presence of frame switches and central transitions, branch prediction layout designs fail to reach steady-state accuracy. Additionally, they reduce their accuracy by storing multiple histories from different processes, which also creates opportunities for side-channel attacks on branch predictors. Under these conditions, there is a need to isolate the processes in the industry prediction and efficiency provisions with a shorter warm-up time.

In this paper, we (1) introduce the concepts of steady-state and transient prediction layout accuracy, (2) show that current designs underperform on realistic workloads with frequent frame switches. To solve this, (3) we design a hybrid predictor and a novel mechanism that can store a reduced branch predictor state and maintain performance, during frame switching or switching. Our results show that, compared to the state of the art, the misprediction rates are reduced by a factor of 2 for high-resolution switches without increasing the area. At the same time, our mechanism makes thread isolation practical, since resetting the reduced state stops the cold execution of the predictor.

I. INTRODUCTION

Branch prediction contributes to high performance in modern deep-pipeline processors by enabling accurate design. Since the conception of hypothetical execution, improvement has gradually increased the overall performance of processors as Branch Prediction (BP) designs have become steadily more sophisticated and complex.

Originally, when area was less of a concern, and pipelines were getting deeper and deeper, accuracy was the dominant factor in the design of predictors. However, as energy became a limiting factor, designs had to take more constraints into account. Predictors had to continually improve accuracy as their primary goal, but they also had to consider energy and area.

Systems in general have become significantly more complex today, featuring multiple types of cores and accelerators in a single die. The software, taking advantage of the aforementioned improvements, has also changed to allow more applications to be managed simultaneously. Applications today are often multi-threaded, while systems context switch (or CS) more often between processes or even switch between cores.

This flexibility of execution has some impact on branch prediction, since with each switch some penalty is imposed and some states are no longer accurate for predictions. In addition, newly discovered micro-architectural vulnerabilities can lead to potentially exploitable side-channel attacks, which can be countered by discarding the branch predictor state during frame switching. This method isolates the processes from each other ensuring no leakage, albeit at the expense of performance since provisioning provisions must be restarted systematically.

The above observations lead us to believe that future system designs should take into account one additional design constraint, that of the ability to handle frequent outages and efficient warm-up. For the BP mechanism in particular, future designs should be able to handle frequent transitions between different cores and similarly guarantee case isolation between different applications without compromising accuracy. This can be described by distinguishing between the accuracy of steady-state and transient predictors as shown in Figure 13. Figure 13 provides a comparison of TAGE and Perceptron with our predictor, ParTAGE (described below), which maintains a minimum status between rejects. This can significantly reduce mispredictions due to frame switches, transitions, or clearing states for security reasons.

Contributions include:

<•>We introduce the concept of transient prediction accuracy and show that it differs from the steady-state performance by which designs are currently evaluated.

· We show that state-of-the-art branch predictors perform particularly poorly since frequent frame switches and transitions do not allow them to fully warm up. We doubt that this issue can be addressed with designs that can handle frequent outages.

· We propose and evaluate a novel mechanism that mitigates the effects of cold-starting by preserving the partial state of a frame-by-frame branch prediction layout. We use our industry predictor design, ParTAGE, which achieves the same high steady-state accuracy but has superior transient accuracy.

Because of hypothetical execution, branch predictors are a critical part of a modern core design, dramatically increasing processor performance. However, events such as frame switches can reduce the applicable accuracy of branch prediction layouts and result in reduced performance. Moreover, the examples identified in recent works show that frame switching and state loss of a branch predictor will become a more important issue for future systems, particularly affecting their operational performance.

A. Motivational examples

We identify three scenarios that guarantee more flexible industry forecasting layouts, which assimilate information better and reach their maximum performance faster.

Transitions in Heterogeneous Systems: Research in heterogeneous systems has shown that the ability to transition as often as 1k instructions between heterogeneous cores can unlock performance potential and power savings and enable operation at improved levels of energy delay products. However, recent findings show that although the overheads of in-line cores mainly stem from cache misses and the inability to cover memory latency, accurate hypothetical execution and thus branch prediction is critical for out-of-line (out -of-order or ОоО) cores.

Following current design trends, future systems will incorporate a multitude of heterogeneous cores targeting specific applications. The challenge with heterogeneous systems is that they should provide an efficient transfer of data and frames between cores. The effects of cold start on branch predictors significantly degrade performance by up to 40% in frequent transition scenarios, as shown in Figure 14, which shows a simulated system using an out-of-order core design that performs a transition to the same core type in different command periods. Solid lines lose BP status, while outline ones retain it. The results are normalized to a system which continues without transitions.

Sharing branch predictors would be a solution, however, this is problematic because branch predictors are directly tied to the cores and have very tight latency constraints to be able to provide predictions in time. In addition, heterogeneous systems combine drastically different core designs to cover more energy/performance points of operation. As such an InO core has a much smaller front end with a smaller branch predictor arrangement compared to aggressive CoO cores. Instead of direct sharing, we analyze branch prediction provisions for their "essential" state and show how this can be used (or ported) to improve cold-start behavior.

Security, Isolation, and Hypothetical Side-Channels: Another issue requiring attention for future branch prediction device designs stems from potential micro-architectural exploits associated with hypothetical execution. Recent research has shown that side-channel attacks that leak sensitive data are possible in most modern CPU designs. As these exploits exploit design-time hardware omissions, countermeasures are often difficult, impractical due to particular performance losses, or completely unfixable. The Specter and BranchScope exploits are an illustrative example of the scope of these threats, both in terms of the risk they present and the difficulty of addressing them on already developed hardware.

Although countermeasures have been developed for known exploits, the question remains about potential unknown exploits and whether current safeguards are effective. Isolation is usually accepted as a sufficient measure to ensure that there will be no leaks, but it is often at the expense of performance. For branch prediction, removing the branch predictor from any state for each frame switch is assumed to take care of such side channels, but with a reduction in throughput with each switch. A more flexible design that can train efficiently and quickly reach steady-state performance will be useful in a post-Meltdown and Spectre world.

The increase in frame switches: An additional reason that drives us to improve the behavior of branch predictors during warm-up stems from the performance loss during frame switches. Even for small and simple designs, frame switches degrade performance, and the effects intensify as the complexity and size of prediction devices increase. For example, the difference in prediction rate of an initial 1k skewness prediction array is 7%. We present in Table I frame switching numbers extracted from a modern mobile device (Google Pixel phone):

Table I:

These show that frame switches for Android apps can reach up to 32k per second. This roughly translates to 1 frame switch every 64k instructions or every 12k branch instructions. We measured an idle system to have 4000CS/S.

Another interesting point is that traditionally, devices (such as I/O, non-volatile memories, and accelerators) had a latency in the millisecond range while frame switches completed in millionths of a second. This meant that a system could perform frame switches and remain useful instead of waiting. However, these millisecond overheads are expected to decrease in the future and become comparable to those of frame switching. Systems will find fewer opportunities to cover device latency through switches as these exploitable windows become smaller. To solve this, frame switches should be made more efficient and allow execution streams to be multiplexed at a more granular level.

We therefore question redesigning components such as branch predictors to accommodate more volatile environments where frame switches are more frequent and short-lived.

B. Industry forecasting design

Branch forecasting has evolved over the years from small and simple designs to large, complex structures that store long histories of control flow. Here, we focus on two designs: the TAGE predictor and the Multiperspective Perceptron predictor.

TAGE-based predictive layouts. The TAGE forecaster is one of the most accurate designs. It uses geometric labeled history lengths that capture correlation from remote branch results and recent history. Internally, TAGE consists of arrays that store the information for various history lengths. Briefly, when a prediction is required, TAGE looks for the match that belongs to the table with the longest history. If no match is found it uses its transition predictor, a bistable design, as a transition mechanism.

The TAGE design has been refined over the years and incorporates other small components to further improve its performance in situations where the original design proved to often mispredict. For example, the TAGE-SC-L predictor also incorporates a statistical corrector and a loop predictor as shown in Figure 15.

Perceptron-type prediction devices: Perceptron prediction devices are broadly based on neural network theory. Perceptron-type predictors achieve high accuracy from efficiently stored states. The working principle of the Perceptron, as shown in Figure 16, uses a table of sets of weights which are multiplied by the historical bits. The output and confidence of the predictor depends on the sign of the sum of all historical y<x>weight products. Confidence can be inferred from the range of the sum of the products. Modern versions of the Perceptron have reduced the amount of computation required for each prediction and use multiple matrixes of weighted die symbols which are indexed using both the history and the sector (PC) address. These tables are commonly referred to as feature tables. In more modern Perceptrons, instead of actually multiplying segments of history by weights, segments of history are used to index the weight matrices, and weights chosen based on history and/or PC are added directly afterwards to form the prediction (without requiring the multiplication of the weights by the history).

III. FLEXIBILITY OF FORECAST PROVISIONS

Branch layouts are evaluated based on how accurate their predictions are, given a reasonable amount of history from which to learn. However, in many real-world cases they operate on time frames much shorter than ideal, predicting from a partially warm, partially replaced state. Large predictors that store more information usually have the potential to provide better predictions. However, if the state is lost or aborted before the prediction device has time to warm up, then it will essentially not reach peak performance. In this case, a smaller predictive array may be able to provide equivalent performance for a fraction of the situation.

A. Steady-state and transient accuracy

We therefore distinguish between steady-state accuracy and transient accuracy. The term steady-state accuracy refers to the performance of the branch predictor when fully saturated. In contrast, transient accuracy describes the behavior of a predictor during the warm-up phase. To quantify the transient accuracy, we propose to discard the state of the branch prediction array at various branch instruction periods and monitor the change in average mispredictions per kiloinstruction (MPKI).

B. Preserving the Hypothetical Status

To improve the transient accuracy, we propose a mechanism (Figure 17) which allows the state of the branch predictor to be stored. The mechanism, which is triggered after frame switches or transitions, stores the state in a dedicated buffer called the branch state buffer (BSB).

The branch state cache is closely related to the branch predictor and can hold many separate entries. Ideally, storing the entire state would allow high accuracy with no warm-up time. However, the size of designs today is too large to fully store without imposing significant overhead. To reduce extra shipping and storage costs, we intend to make this component as small as possible. We find 10kBit (1.25kB) to be a useful size in our experiments. We therefore suggest using a reduced state which sacrifices accuracy but may still provide better performance than a large but “cold” predictor.

An additional advantage of storing a reduced state is that it makes process isolation effective and thus improves security. Storing the state of the branch predictor in the extra buffer on frame switches, maintaining this state per process, and restoring it during frame resumption (with an otherwise cleared predictor) ensures that the state of the branch predictor is not used never shared between mutually untrusted processes and the kernel. Performance degradation is mitigated in this case, since the preserved state preserves a portion of the performance.

Our study examines TAGE and Perceptron prediction devices which are highly structured. We break them down and determine the best way to reduce their state so that the greatest percentage of performance can be preserved in frequent switching situations.

TAGE uses a bistable core predictor, a number (eg 12) of matrices for the TAGE core predictor, a statistical corrector, and a loop predictor. These components vary in size and how much they affect overall accuracy. We evaluate their contribution to the prediction as the predictor is warmed up for various states rejection frequencies.

The evaluated Multiperspective Perceptron design uses multiple hash tables to provide a prediction. The design also uses some helpers to improve accuracy, for example the inner most loop iterator (IMLI) as well as several registers that keep track of when certain branches have been answered in the past.

The question, in this case, is which method is used to reduce the data in the most conflicting way. This question is not trivial since it is directly related to BP implementation and the amount of states that can be efficiently stored when overhead constraints are taken into account. We review state reduction techniques for both forecast layouts that are closely related to the specifics of each baseline and show how to optimize data reduction against retained forecast accuracy.

One way to preserve state is to select some components that provide a good balance between the amount of data stored and the accuracy achieved and discard the state of the remaining components. This "vertical cut" method can be used in the case of TAGE since it consists of several components that can provide accurate stand-alone predictions.

For example, the basic predictor may be isolated from the rest of the components and still provide reasonable accuracy. Similarly, separate TAGE arrays can be maintained instead of the entire design, to target specific history sizes.

Some components, however, only provide additional benefits to predictions. So it doesn't make sense to consider maintaining the state of all components. For example, the loop predictor is a relatively small component that identifies regular loops with a fixed number of iterations. The overall effect of this component on the accuracy of TAGESCL was measured to be approximately 0.3% improvement.

Another way to preserve state is to partially store state across all predictor components. For TAGE this can be done by naively storing a section of each of the TAGE arrays. The logic of this "horizontal" approach is to capture the information throughout the history, albeit with less precision than storing the entire state. The same method can be used to maintain the Multiperspective Perceptron state, as long as all arrays are combined to provide accurate predictions.This case can store more information since perceptron arrays are designed to have multiple pointers which condense the amount of data stored in each entry.

C. Perceptron enhanced / empowered TAGE

We propose a hybrid approach to state maintenance which we call ParTAGE - Perceptron amplified / reinforced TAGE. This design uses a Multiperspective Perception predictor with smaller and fewer feature matrices as the basic predictor of the TAGE design, replacing the bistable predictor. The Perceptron used is the same size as the replaced bistable consuming up to 10kbit of “budget”.

ParTAGE also incorporates a branch state cache, which is a multiple of the basic prediction array in size. This size compatibility allows ParTAGE to store Perceptron state in the branch state buffer when stopping a frame's execution and restore it when it resumes. This addresses the issues described above, as state can thus be maintained throughout frame switches.

Additionally, since the state is stored per frame in the BSB, the rest of the branch predictor design can be eliminated to eliminate the possibility of side-channel leaks targeting the branch predictor. For transitions between cores, the corresponding BSB state can also be pushed to the target core to reduce transfer overheads. This can also be applied to heterogeneous multiprocessors, where the basic prediction arrangement of a ccO core is perfectly identical to the entire prediction arrangement of the inline core used for rendering. This is shown in Figure 18. For example, the branch predictor in the in-line core (second processing element) can have exactly the same design as the basic predictor of the ParTAGE branch predictor in the out-of-order core (first processing element), so to make the transition of workloads between cores clear. After a workload transitions from the C0O core to the In-O core, the branch prediction state associated with parts of ParTAGE other than the basic prediction layout may be discarded, while after a workload transitions from the In-0 core to the In-0 core OO kernel, these other parts of ParTAGE can be initialized with default values.

To reduce the size of the Perceptron within the allocated budget, we use a similar configuration to the 8kB Multiperspective Perceptron with 8 smaller feature matrices instead of 16. The limited size of the Perceptron in ParTAGE allows its state to be preserved during frame switching or transition. In the intermediate warm-up state, ParTAGE has chosen between the transient prediction of the TAGE arrays and the steady-state prediction of the preserved Perceptron. We design two versions of ParTAGE, one that hardwires the perceptron predictor to always be selected during the predictor transition phase, and one that evaluates the confidence of the base perceptron predictor's prediction before the outcome is selected.

IV. Experimental setup

The experiments performed use the CBP5 framework with traces from 2016 as a base. The framework uses 268 traces, with combinations of large / small workloads and mobile / server workloads. We are modifying the CBP framework slightly so that industry forward provisions can carry out a full or partial rejection of their status. This allows studying the history of the behavior of branch prediction devices, showing the effects that a complete or partial loss of state has on the structure.

For our experiments, we use a number of predictors that are widely used today. As a basic design, we implement a set of dichotomous type predictors, with and without lag. To compare several state-of-the-art forecasting arrangements, we use the submitted TAGE-SC-L [A. Seznec, “TAGE-SC-L branch predictors”, JWAC-4: Championship Branch Prediction, 2014] and Multiperspective Perceptron without TAGE [D.A. Jiménez, “Multiperspective Perceptron Predictor”] from CBP5. We slightly modify both designs to allow partial or complete rejection of their designs when required, while carefully preserving their exact steady-state behavior.

Furthermore, we implement two variants of ParTAGE which express different policies for selecting the optimal transient prediction. ParTAGE-S bypasses the prediction of TAGE tables below a period threshold value which we have set equal to 200k branch instructions. ParTAGE uses a unified confidence value that is evaluated by the rest of the TAGE design to indicate the most accurate prediction.

We focus on 8kB and 64kB forecast layouts, similar to those evaluated in CBP. A detailed list of all forecasting provisions evaluated is shown in Table II:

Table 2:

We evaluate the transient accuracy of the forecasting arrangements evaluated for the cases described in Section II. To achieve this, we cover a range of discard periods from 10 to 60M branch instructions per discard, deriving the optimal design for each use case.

V. RESULTS

We perform three different types of comparisons focusing on simple bistable predictors, state-of-the-art TAGE and Perceptron designs, and our ParTAGE proposal.

A. Results of inconsistent accuracy

The bistable is used as a basic experiment, consisting of a single array of counter bits. In Table III we show how the MPKI of various bistable designs improves with increasing hold period:

Table III: (MPKI for various BPs at various branch rejection periods)

Despite a 100x difference in size, the steady-state MPKI increase is only 12.28%. The results reveal that, although size contributes to steady-state accuracy, transient accuracy is not affected by the size of a forecast array.

Conversely, a design variation such as adding lag (sharing part of the prediction state values between entries—used in the BIMH variants shown in Table III ) improves transient accuracy, even in smaller prediction layouts. This happens as the lag bits also affect neighboring branches and ultimately warm up the design faster. This is clearly visible at shorter rejection periods where mispredictions are on average 18% less for the lag-steady designs. Figure 19 shows the difference in performance for various bistable sizes and designs.

B. Transitional accuracy: TAGE versus Perception

Our second set of results focuses on comparing the transient behavior of the two most distinguished designs in modern systems, TAGE and Perceptron. Figure 20 shows the various behavioral transitions between the TAGE and Perceptron designs. We note that the 8kB variant of the Perceptron has the worst cold start, yet it manages to quickly improve and similarly continue steady-state performance.

The transient MPKI for a discard period of 20k branch instructions is 7.75 and 6.98 for the TAGE 8kB and 64kB designs and 7.57 and 6.93 respectively for the Perceptron. Switching every 20k branch instructions is within a realistic range for applications such as those presented in Table I and for proposed systems that support high-resolution transitions or frequent frame switches. This result shows that TAGE can provide better steady-state performance. However, for applications that perform frequent frame switches, Perceptron provides more accurate predictions.

One more observation can be drawn when comparing the 64kB and 8kB variants in smaller non-interrupted execution windows. Considering for example switching every 20k or 200k branch instructions, 8kB prediction designs perform on average 10% and 15% worse than 64kB designs. However, the performance gap increases to 33% when observing the same designs at steady state.

Using the steady-state performance as a baseline and comparing the transient accuracy, at all resolutions up to 20k branch instructions, we estimate how much worse the accuracy can be in workloads with frame-switch loads. From Figure 20, MPKI increase reaches 90% and 80% for TAGE and Perceptron respectively. This reinforces our belief that forecast provisions today are evaluated without considering the problems that occur during realistic execution.

C. PARTAGE

To improve the transient accuracy of branch prediction, we present results from our proposal, ParTAGE, a design that is influenced by both Perceptron and TAGE. Before we analyze its performance compared to today's competitive designs, we highlight its design choices.

Fragmentation TAGE: We analyze the performance of TAGE by measuring the reduction in total transient MPKI caused by each component while maintaining its state between discards. In Figure 21 we observe the size required to maintain the components in each configuration and the relative MPKI, normalized to TAGE's steady-state performance. The analysis in the figure shows the transient state with a rejection period of 20k branch commands. For example, it shows that, for this analysis, keeping none of the components increases MPKI by 90%.

From the figure, we make two additional observations. First, the majority of the performance is provided by the TAGE arrays, which are too large to maintain, especially considering that the discard frequency is set at 20k branches. Second, we observe that on the other side of the spectrum, the basic bistable predictor and the statistical corrector improve MPKI by 16% and 10% respectively. However, since bistable requires only 1.25kB of states to maintain, compared to the statistical corrector's 8kB, its MPKI improvement per kB value is much higher than that of the statistical corrector.

Finding the right, “small” prediction layout: The analysis of TAGE leads to the basic idea for ParTAGE. The idea is to design a predictor with a small enough key to maintain during a frame switch or transition, but at the same time with enough precision to justify the overhead of storing the state. From Figure 20 we observed that Perceptron predictors rapidly improve their MPKI with time before reaching steady state accuracy. This reveals an interesting aspect of Multiperspective Perceptron prediction devices. Compared to dichotomous prediction schemes, biased and common-weighted values in modern Perceptron designs are more efficient designs and have the ability to aggressively train and store information in a denser form. We focus on the second feature, that of dense branch information storage, to design the basic predictor since we intend to store and restore it for each frame, never allowing it to return to its transitive accuracy.

In Figure 22 we compare the bistable design and the Perceptron design with sizes that fit roughly within a 1.25kB budget. The results show that while the Perceptron has a higher MPKI in analyzes up to 200 branching orders, its steady-state accuracy is significantly better.

Improvement of the small perceptron: We chose to use a small perceptron as the basic predictor for ParTAGE. To reduce the size of the Perceptron predictor to 1.25kB and achieve better accuracy, we calibrated the volume of feature matrices and the size of the Perceptron predictor we use. We first set the size of the prediction array to 1.25kB (part (a) of Figure 23). We conclude that eight feature matrices provide optimal performance.

We then arrive at the eight attribute tables and perform a size scan to further optimize the design, from 0.25kB to 2.5kB. Part (b) of Figure 23 shows that 1.25kB is close to the optimal configuration. We observe that changing the feature sizes affects the prediction more than changing the size. We find that for the sake of completeness, a genetic algorithm as proposed in Multiperspective Perceptron can provide even better results. We leave such final performance optimizations for the future.

D. Results for ParTAGE

We created the ParTAGE predictor based on our observations of small predictors by replacing the 1.25kB bistable with a perceptron of the same size.

Comparison of ParTAGE Variants: The results in Figure 24 compare ParTAGE with a TAGE design that loses the entire state and TAGE (B) that keeps the bistable state intact across discards. For ParTAGE, we compare the two variants which modify the part selection policy. ParTAGE-S statically bypasses the TAGE components for a short period after a discard, forcing the predictor to select the Perceptron prediction. ParTAGE uses the Perceptron confidence levels of each prediction to decide which prediction fits best.

In general, maintaining a minimal state can have a significant improvement when the state is frequently discarded but has a negligible impact on steady-state MPKI. This shows that for systems with sparse frame switching, discarding the branch predictor state, to improve security for example, has no negative impact on performance.

On the other hand, for systems that transition as fast as every 1k instructions, our design can cut the misprediction rate in half. This can be seen when the discard period is 200 branch commands, in Figure 24. When we consider current systems with fast frame switching, we see that the best performance is provided by our proposed extension to the original TAGE design which maintains its bistable state in BSB. Figure 25 shows that the improvement is about 15%.

Comparison of ParTAGE with TAGE and Perceptron: Comparing the different implementations of ParTAGE, we notice that while ParTAGE-S performs well for high-resolution switching, the transient accuracy degrades at longer rejection periods since the TAGE arrays are not sufficiently trained. In contrast, ParTAGE, which simply relies on TAGE, does not achieve the same transient accuracy when the period is less than 2k branch instructions. This is the case where the TAGE arrays are completely cold, but their prediction takes precedence over the more accurate one from the perceptron component. This is also the reason why ParTage does not improve the transient accuracy at 20k branch instructions. This can be solved by better regulation of the selection policy in the future.

Improving the steady-state performance of the basic predictor and efficiently maintaining its state allows efficient operation at higher resolutions. This can be achieved either by increasing the size of the branch state cache to accommodate more states, or by developing 1kB predictors with better steady state accuracy. For example, achieving the equivalent performance of an 8kB perceptron can further reduce additional mispredictions.

Although it is aimed to improve the transient accuracy of branch prediction, it is equally important to maintain a competitive steady-state accuracy for our proposed design. We perform a direct comparison between TAGE-SC-L, both Multiperspective Perceptron versions submitted to CBP5, and the optimal version of ParTAGE. Figure 26 provides a detailed look at steady-state MPKI compared to TAGE and the optimal version of the Multiperspective Perceptron. We observe that ParTAGE provides 3,726 MPKI, competitive with TAGE (3,660 MPKI) and even better than perceptron (3,826 MPKI).

VII. FINAL COMMENTS

In the present work, we have focused on the phenomena that cause problems in the performance of industry prediction devices. We highlight real-world cases where problems arise, such as frequent frame switches or transitions, but also techniques to counter side-channel attacks that target the case engine. We show that these problems create a disconnect between the reported nominal performance of branch predictors and the actual accuracy in real applications. To distinguish between the two, we introduce the concepts of steady-state branch predictor performance and transient branch predictor performance.

We propose a novel mechanism, the branch state cache, which maintains a minimal, isolated state per frame to reduce the high number of mispredictions. We propose two designs which store the necessary frame state in the BSB. First an extension of TAGE, called TAGE(B), which preserves the bistable state of the prediction array. Second, a new branch predictor design, ParTAGE, which replaces the bistable in TAGE with a Perceptron. We evaluate the use of a new methodology, which modifies the framework used in the industry prediction champion to enable the elimination of the industry prediction layout state at different frequencies.

We show that branch predictors today can have up to 90% more mispredictions than expected at steady state when operating under some realistic conditions. Using TAGE (B) we achieve a 15% reduction in MPKI. In addition, we show that, using ParTAGE, high-resolution transitions in heterogeneous systems can be made much more efficient, as our design halves the misprediction rate. We achieve all of this by ensuring that frames remain isolated and protected from side-channel attacks and keep steady-state performance consistent with current competitive designs.

More examples of layouts are presented in the following paragraphs:

(1) A TAGE branch predictor for predicting a branch command result, which includes:

a plurality of TAGE prediction tables for providing a TAGE prediction of the result of the branch instruction, each TAGE prediction table including a plurality of prediction entries trained based on the previous results of the branch instructions;

a lookup circuit for searching each of the TAGE prediction tables based on an index determined as a function of a target instruction address and a portion of past execution history indicative of execution behavior preceding an instruction at the target instruction address, with that portion of the previous execution history be used to determine the index with different lengths for various TAGE prediction tables, and

a transition prediction arrangement for providing a transition prediction for the result of a branch command in case the lookup fails in all TAGE prediction tables, in which:

the transition predictor includes a perceptron predictor including at least one weight table for storing weights trained based on previous branch command results and predicting the branch command result based on a sum of terms, each term depending on a corresponding weight selected from said at least one weight table based on a corresponding portion of at least one of the target command addresses and past branch history, and

a total size of a branch prediction state stored by the perceptron predictor is smaller than a total size of a branch prediction state stored by the plurality of TAGE prediction tables.

(2) The TAGE branch prediction device of paragraph (1), which includes a selection circuit for selecting between the transition prediction provided by the transition prediction device and the TAGE prediction provided by the plurality of TAGE prediction tables, depending on a a confidence value indicative of a level of confidence in the TAGE prediction, said confidence value being derived from the TAGE prediction tables from the search circuit during the search.

(3) The TAGE branch prediction arrangement of paragraph (2), wherein the selection circuit is configured to select the transition prediction when the search fails in all TAGE prediction tables or the confidence value indicates a confidence level less than a threshold value.

(4) The TAGE branch prediction arrangement of paragraph (3), wherein when the search succeeds in at least one TAGE prediction table, the TAGE prediction includes a prediction based on an indexed entry of a selected TAGE prediction table, with the selected TAGE prediction table to include the one of at least one TAGE prediction table for which the index is determined based on the largest portion of the previous execution history.

(5) The TAGE branch prediction device of paragraph (1), which includes a control circuit responsive to an execution frame switch of a processing element from a first execution frame to a second execution frame, to prevent the TAGE branch prediction device from providing a branch prediction for an instruction of the second execution frame based on the branch prediction state trained based on the instructions of the first execution frame.

(6) The branch prediction device TAGE of paragraph (1), which includes a branch prediction storage circuit responsive to a branch prediction storage event to store information in a branch state buffer according to at least one portion of the at least one weight table of perceptron prediction array, and

a branch prediction reset circuit responsive to a branch prediction reset event associated with the given execution context to reset at least a portion of the at least one weight matrix of the perceptron predictor based on information previously stored in the branch state cache.

(7) The TAGE branch prediction device of paragraph (6), which includes a selection circuit for selecting between the transition prediction provided by the transition prediction device and a TAGE prediction provided by the plurality of TAGE prediction tables, in which :

during an initial period following the branch prediction reset event, the selection circuit is configured to select the transition prediction provided by the transition prediction device.

(8) The TAGE branch prediction arrangement of paragraph (7), in which during the initial period, the TAGE prediction tables are configured to update the prediction entries based on the results of the branch commands.

(9) The TAGE branch provision provision of paragraph (7), in which the initial period includes one of the following:

a predetermined length of time after the branch prediction reset event;

a predetermined number of processing cycles after the branch prediction reset event;

a predetermined number of commands processed after the branch prediction reset event;

a predetermined number of branch commands processed after the branch prediction reset event or

a predetermined number of searches performed by the search circuit after the branch prediction reset event.

(10) The TAGE industry forecast provision of paragraph (7), in which the initial period includes a period that lasts until a confidence level in the TAGE forecast exceeds a predetermined level.

(11) A device which includes:

a first processing element for processing instructions in at least one execution context, and

the TAGE branch prediction arrangement of paragraph (1), for predicting the results of branch instructions processed by the first processing element.

(12) The apparatus of paragraph (11), which includes a second processing element that includes a second branch prediction device for predicting the results of branch instructions processed by the second processing element.

(13) The apparatus of paragraph (12), wherein the second branch predictor comprises a perceptron predictor corresponding to the transition predictor of the TAGE branch predictor.

(14) The device of paragraph (13), which includes a branch prediction state transfer circuit responsive to the transition of an execution frame from the second processing element to the first processing element to:

transferring the at least one weight table from the second branch predictor to the transition predictor of the first branch predictor, and

initializing the TAGE prediction tables of the first branch predictor with the initial values regardless of a state of the second branch predictor.

(15) The device of paragraph (14), which includes a branch prediction state transfer circuit responsive to the transition of an execution frame from the first processing element to the second processing element to:

transferring the at least one weight table from the transition predictor of the TAGE branch predictor to the second branch predictor, and

canceling or disabling the TAGE prediction tables of the TAGE industry prediction array.

(16) A TAGE branch prediction arrangement for predicting a branch command result, which includes:

means for storing TAGE prediction tables for providing a TAGE prediction of the result of the branch instruction, each TAGE prediction table including a plurality of prediction entries trained based on previous branch instruction results, means for searching each of TAGE prediction tables based on an index determined as a function of a target instruction address and a portion of past execution history indicative of execution behavior preceding an instruction at the target instruction address, with said portion of past execution history being used to determining the index to be of different length for various TAGE prediction tables, and

means for providing a transition prediction for the result of a branch command in case the lookup fails in all TAGE prediction tables, in which:

means for providing a transition prediction includes means for providing a perceptron prediction, which includes means for storing weights trained based on previous branch command results and means for predicting the branch command result based on a sum of terms, with each condition depending on a corresponding weight selected from said at least one weight table based on a corresponding portion of at least one of the target command address and the previous history branch, and

the total size of the branch prediction state stored by the means for providing a perceptron prediction is less than the total size of the branch prediction state stored by the TAGE prediction tables.

(17) A method for predicting the result of a branch instruction using a TAGE branch predictor that includes a plurality of TAGE prediction tables for providing a TAGE prediction of the result of the branch instruction, each TAGE prediction table including a plurality of entries trained prediction based on the results of previous branching commands, the method comprising:

searching each of the TAGE prediction tables based on an index determined as a function of a target instruction address and a portion of past execution history indicative of execution behavior preceding an instruction at the target instruction address, with said portion of past history execution to be used to determine the pointer that has a different length for various TAGE prediction tables, and

providing a transition prediction for the result of the branch command in case the search fails in all TAGE prediction tables, using a perceptron prediction array that includes at least one weight table for storing the weights trained based on the previous command results branching, the transition prediction being predicted based on a sum of terms, each term depending on a corresponding weight selected from said at least one weight table based on a corresponding portion of at least one of the target command address and the previous branch history , and

the total size of the branch prediction state stored by the perceptron predictor is smaller than the total size of the branch prediction state stored by the plurality of TAGE prediction tables.

In the present application, the words "configured for..." are used to mean that an element of a device has a configuration capable of performing the specified function. In these contexts, a “configuration” means an arrangement or way of interconnecting hardware or software. For example, the device may have specialized hardware that provides the specified function, or a processor or other processing device may be programmed to perform the function. The words “configured for” do not imply that the device element must be modified in some way to provide the specified function.

Although the invention has been described herein with reference to the appendants, it is to be understood that the invention is not limited to various changes and modifications

by persons skilled in the art without invention as determined by the accompanying detailed illustrative embodiments schematic drawings, must be i in those embodiments and that they can be realized in the same from the object and spirit of the claims.

Claims (18)

1. A device which includes: a processing element for processing commands from a plurality of execution contexts; a branch predictor for predicting the results of branch instructions processed by the processing element based on the active branch prediction state stored in a branch prediction store; a branch prediction control circuit responsive to an execution frame switch from a first execution frame to a second execution frame and prevents the branch predictor from predicting the results of branch instructions of the second execution frame based on the trained branch prediction state the results of the previous branch instructions of the first execution frame, branch prediction storage circuitry responsive to a branch prediction storage event associated with a given execution context to store at least a portion of the active branch prediction state associated with the given execution context in a branch state buffer, and a branch prediction reset circuit responsive to a branch prediction reset event associated with the given execution context to reset the active branch prediction state based on the previously stored branch prediction state stored in the branch state buffer for the given execution context. 2. The apparatus according to claim 1, wherein the branch prediction storage circuit is configured to perform compression of the branch prediction states to compress said at least a portion of the active branch prediction state to create a compressed branch prediction state to be stored in the branch state cache, and the branch prediction restore circuit is configured to decompress the branch prediction states to decompress the previously stored branch prediction state to create the active branch prediction state to be restored. 3. The apparatus according to claim 2, wherein the branch predictor comprises a plurality of predictor units for predicting the results of branch instructions using various branch prediction methods and a selector for selecting among the results predicted by the plurality of units of provision provisions, and compressing the branch prediction state includes omitting the active branch prediction state associated with at least one of said plurality of prediction arrangement units from the compressed branch prediction state. 4. The apparatus according to claim 3, wherein the plurality of predictor units includes a transition predictor unit for generating a transition prediction in the event that at least one other predictor unit outputs a prediction with confidence lower than a predetermined threshold value and said compressed branch prediction state includes the active branch prediction state associated with the transition prediction arrangement unit. 5. The apparatus of claim 2, wherein the active branch prediction state comprises a plurality of branch prediction entries each specifying a prediction state value for generating a branch prediction, the branch prediction entries being indexed based on a pointer determined as a function of at least one of the following: a target instruction address for which a branch prediction is required and at least a portion of past execution history indicative of an execution behavior pattern preceding an instruction at the instruction address. 6. The apparatus according to claim 5, wherein said branch prediction state compression comprises mapping the prediction state value of a given branch prediction entry to a compressed prediction state value having fewer bits than the state value industry forecast. 7. The apparatus according to claim 5, wherein said branch prediction state compression comprises merging a plurality of branch prediction entries corresponding to different values of said index into a single entry to be stored in the branch state cache in frames of said industry forecast compressed state. 8. The apparatus according to claim 5, wherein the active branch prediction state further comprises at least a group of two or more branch prediction entries for which each prediction state value includes a hidden portion which is separately determined for each branch prediction entry of group and a shared segment shared between each of the group's branch prediction entries, and with said industry forecast statement including one of the following: the omission of the common part, and omitting the hidden part and keeping the shared part. 9. The apparatus according to claim 5, wherein said branch prediction state compression comprises partially merging a group of branch prediction entries to create a compressed branch prediction state in which a first portion of the prediction state value of each branch prediction entry of the group is determined separately within the compressed branch prediction state, and a second part of the prediction state value of each branch prediction entry is merged to create a value representing a shared second part for each of the group's branch prediction entries. 10. The apparatus according to claim 1, wherein the branch prediction store event associated with said given execution context comprises at least one of: said execution frame switching, for which said execution frame is said first execution frame; the transition of said given execution context from said processing element to another processing element; the elapse of a predetermined period since a last branch forecast storage event; detecting or executing a branch prediction store instruction within said given execution context, and an update of the active branch prediction state that satisfies a predetermined condition that occurs during the execution of said given execution context. 11. The apparatus of claim 1, wherein the branch prediction storage circuit is configured to store the active branch prediction state associated with the given execution frame in the branch state buffer periodically during processing of the given execution frame. 12. The apparatus of claim 1, wherein the branch prediction reset event associated with said given execution context comprises at least one of: said execution frame switching, for which said execution frame is said second execution frame; the transition of said given execution context from another processing element to said processing element; the elapse of a predetermined period since a last industry prediction reset event, and detecting or executing a branch prediction reset command within said given execution context. 13. The apparatus of claim 1, wherein the branch prediction store includes a plurality of areas, and the branch state cache includes at least one of the areas of the branch prediction store. 14. The apparatus according to claim 13, wherein the branch prediction reset circuit is configured to reset the active branch prediction state by switching the area of the branch prediction storage used to represent the active branch prediction state. 15. The apparatus of claim 1, wherein in response to execution frame switching, when the branch prediction store still contains a previously disabled prediction state associated with the second execution frame, the branch prediction control circuit is configured to enable and again the previously disabled branch prediction state associated with the second execution frame. 16. The apparatus of claim 1, wherein in response to execution frame switching, the branch prediction control circuit is configured to disable a portion of the branch predictor for an initial processing period of the second execution frame, while maintaining in the prediction store branch the active branch prediction state associated with that portion of the branch predictor trained on the results of the branch instructions of the first execution frame, and when the initial period ends before any subsequent execution frame switching occurs, the branch prediction control circuit is configured to cancel said branch prediction active state data associated with said portion of the branch prediction arrangement and re-enable said branch prediction device part of the branch prediction arrangement for continuous processing of the second execution frame. 17. The apparatus of claim 1, wherein in response to execution frame switching, the branch prediction control circuit is configured to predict the lifetime of the second execution frame and, depending on the predicted lifetime, determine whether: disable a portion of the branch predictor during processing of the second execution frame while maintaining the active branch prediction state associated with the disabled portion of the branch predictor trained based on the results of the branch instructions of the first execution frame; or to invalidate the branch predictor state data associated with said part of the branch predictor trained on the results of the branching instructions of the first execution frame and to allow said part of the branch predictor to be used when processing the second execution framework. 18. A device comprising: means for processing instructions from a plurality of execution frames, means for predicting the results of branch instructions processed by the processing means based on the active branch prediction state stored in a branch prediction store; means for controlling the branch predictor, which in response to an execution frame switch from a first execution frame to a second execution frame is configured to prevent the branch predictor from predicting the results of branch instructions of the second execution frame based on branch prediction state trained based on the results of the previous branch instructions of the first execution frame; means for storing, in response to a branch prediction save event associated with a given execution context, at least a portion of the active branch prediction state associated with the given execution context in a branch state cache, and means for restoring, in response of a branch prediction reset event associated with the given execution context, the active branch prediction state based on the previously saved branch prediction state stored in the branch state cache for the given execution context. 4&= - A cAadtty prediction method for a ttkip·pi p<»>i· TirpiAfliiP*<1>"·· — , "miycin GTTG^rgpGGips for the\/ cTTrfrpynwiw mwnki'.wt nwr A ·*ni ttellithHii; w»mrrimw ♦execution, with the -method including: ■ the prediction — of — the — results — of — the — commands — of the TTOU TTOU TP^GG'Hi-itiii atto TG element processed based on the united state of PG^P^^TiG.. C MG'P I IIIG hppPiGGIGtii GTG GIGGT hiiiirp ppiliitipis pr^bleps™<»> in response to an execution frame switch from a first execution frame to a second execution frame, preventing the branching results of the second execution frame from being affected by the branch prediction algorithm based on the -T<1>'<,T>Tnift<cl>'<ITr>|<l,>T |<IC>β*-η<πση η>·ττ<η>τπ> *»| ·>it .. irpni |y. in| . .<h>it<h>lii»! Lipitl^Li.Igtis of-the first frame of execution, response to a branch prediction storage event associated with a given Execution context, the storage of a portion of the active branch prediction state associated with the given execution context. - execution context in a branch state buffer, and — ~0i response of a branch prediction reset event associated with, -with— -the given execution context, the active state reset. forecast — branch — with — ba^i the _ prpigii 1| ii^niiis apppAkti imrgi — branch ■ ■prediction state stored in the branch state cache — , for the given execution context. -