GR20170200061U - An apparatus for transferring data between address ranges in memory - Google Patents

Abstract

An apparatus is provided for transferring data between address ranges in memory. The apparatus comprises a data transfer controller, that is responsive to a data transfer request received by the apparatus from a processing element, to perform a transfer operation to transfer data from at least one source address range in memory to at least one destination address range in the memory. A redirect controller is then arranged, whilst the transfer operation is being performed, to intercept an access request that specifies a target address within a target address range, and to perform a memory redirection operation so as to cause the access request to be processed without awaiting completion of the transfer operation. Via such an approach, the apparatus can effectively hide from the source of the access request the fact that the transfer operation is in progress, and hence the transfer operation can be arranged to occur in the background, and in a manner that is transparent to the software executing on the source that has issued the access request.

Description

AN ARRANGEMENT AND MEASURES FOR THE TRANSFER OF DATA

BETWEEN ADDRESS AREAS IN MEMORY

The present technique relates to an arrangement and method for transferring data between address ranges in memory.

In data processing systems, situations may arise in which it is desirable to move tiers of data between different physical locations in memory. For example, often the memory system is arranged as a series of pages, while it may be desirable to transfer data from one page to another page, merge several smaller pages into one larger page, etc.

Often, the operating system running on a processor within the system can be used to manage the transfer of data between various physical locations in memory. However, the process of transferring the data under such software control can take a significant period of time. This not only consumes significant processor resources, but also requires measures to be taken during this period to ensure that any attempt to access data subject to the transfer operation will not give rise to data inconsistencies. Often this may require blocking write accesses until the transfer operation is complete.

Additionally, when performing such data transfer operations under the control of the operating system, the process typically requires multiple memory management operations, which can also give rise to performance issues due to the time required to perform these memory management operations. .

It would therefore be desirable to provide an improved mechanism for managing the transfer of data between memory address ranges.

In a first exemplary embodiment, an apparatus is provided, comprising: a data transfer controller, responsive to a data transfer request received by the apparatus from a processing element, for performing a transfer operation to transfer data from at least one area of source addresses in memory to at least one area of destination addresses in memory, and a redirection controller arranged, v

performing the operation to intercept an access request that specifies a destination address within a destination address range and performing a memory redirection operation to cause said access request to be processed without waiting for the transfer operation to complete.

In a further exemplary embodiment, a system is provided comprising: a plurality of processing elements, an interface connected to said plurality of processing elements and for controlling access to a memory by said plurality of processing elements, the interface having a transfer engine configured by an arrangement according to the first exemplary embodiment, for performing a transfer operation on behalf of one of the processing elements for the purpose of transferring data from at least one source address range to at least one destination address range while enabling continuation the processing of access requests issued by the plurality of processing elements with respect to the data subject to the transfer function during the execution of the transfer function.

In a still further exemplary embodiment, a method of transferring data between address ranges in memory is provided, comprising: in response to a data transfer request received from a processing element, using a data transfer controller to perform a transfer operation to transfer data from at least one source address range in memory to at least one destination address range in memory, and during execution of the transfer operation, intercepting an access request that specifies a destination address within a destination address range and performing a memory redirection operation to cause that access request to be processed without waiting for the transfer operation to complete.

In a still further exemplary embodiment, an arrangement is provided, comprising: data transfer control means for performing, in response to a data transfer request received by the arrangement from a processing element, a transfer operation for transferring data from at least one area source addresses in memory to at least one destination address range in memory and redirection control means for intercepting, during execution of the transfer operation, an access request specifying a destination address within a destination address range and performing a memory redirection operation to causes the access request in question to be processed without waiting for the transfer operation to complete.

The present technique will be further described, by way of example only, with respect to embodiments thereof as illustrated in the accompanying drawings, in which:

Figure 1 is a block diagram of a system according to one embodiment,

Figure 2 is a block diagram illustrating in greater detail the data transfer engine of Figure 1 in accordance with one embodiment;

Figure 3 schematically illustrates information that may be held within the control registers of Figure 2 in accordance with one embodiment,

Figures 4A and 4B are flowcharts illustrating steps within the system of Figure 1 according to one embodiment for transferring data from at least one source address range in memory to at least one destination address range in memory;

Figures 5A, 5B and 5C are flowcharts illustrating three different mechanisms that may be used to implement step 245 of Figure 4B;

Figures 6A through 6C schematically illustrate the use of one embodiment's data transfer engine (referred to in these figures as a copy engine) for an example case where two source address ranges are merged into a single, larger destination address range;

Figure 7 schematically illustrates how a reserved address region within the memory address space may be associated with the data transfer engine in accordance with one embodiment, and

Figure 8 illustrates a system according to an alternative embodiment where a non-uniform memory access (NUMA) configuration is used and multiple data transfer engines are provided to manage data transfer operations.

Before considering the embodiments with respect to the accompanying drawings, the following description of the embodiments is provided.

In an example implementation, an arrangement is provided which includes a data transfer controller and a redirection controller. The data transfer controller responds to a data transfer request received by the device from a processing element to perform a transfer operation to transfer data from at least one source address range in memory to at least one destination address range in memory. The source address range(s) and destination address range(s) can be specified in a number of ways, but in one embodiment they are provided as information within the data transfer request received by the processing element.

The redirection controller is then ordered, during the transfer operation, to intercept an access request that specifies a destination address within a destination address range and perform a memory redirection operation to cause the access request to be processed without waiting for the completion of transfer operation.

With such an approach, some access requests may be intercepted by the arrangement of the above implementation and subjected to a memory redirection operation in order to cause these access requests to be processed even though the transfer operation has not yet completed. The arrangement may therefore, in practice, hide from the origin of such an access request the fact that there is a transfer operation in progress. From the perspective of the origin of the access request, the transfer operation occurs in the background and can be ordered to be transparent to software running on that origin. Access requests issued by such a source that specify an address within the destination address range are not blocked while the transfer operation is in progress, thereby significantly improving performance.

The destination address range may be specified in a number of ways, but in one embodiment the system in which the device is used is arranged so that, during the transfer operation, any access requests are issued with respect to data subject to that transfer operation they will identify destination addresses that are within the destination address range and will accordingly be intercepted by the redirection controller and subjected to the memory redirection function.

In one embodiment, the arrangement further includes a settlement controller arranged to receive the data transfer request and issue a control signal which forces access requests issued while the transfer operation is in progress and which are related to the data transferred by the operation transport, to specify an address within the destination address range as the destination address. The control signal can take a number of forms. For example, the settlement controller may itself directly update address translation structures that are used to determine the addresses for access requests, for example page tables in memory, so that access requests issued during transfer operation execution and associated with the data transferred by the transfer function, will specify addresses within the destination address range. In cases where the various processing elements within the system that can issue access requests to the corresponding portion of memory use associated address translation stores (for example, translation lookaside buffers (TLBs)) for temporary storage address translation data used by these processing elements, the settlement controller may also issue control signals to cause relevant portions of these address translation stores to be invalidated, which would, for example, ensure that the updated page tables the next time an access is issued about the relevant address range.

In an alternative embodiment, the settlement controller may not perform such tasks itself, and instead the control signal may take the form of an acknowledgment signal returned to the processing element that issued the data transfer request, with the processing element being ordered to to respond to the identification signal to perform the tasks described above. Thus, for example, this processing element can update the page tables in memory so that subsequent access requests issued with respect to the transferred data are mapped to addresses within the destination address space, and it can additionally invalidate the relevant entries in its address translation store and broadcast a signal to other processing elements in the system to ensure that they also invalidate those relevant portions of their local address translation stores.

The destination address range can take a number of formats. For example, it may be ordered to be said at least one source address range, while in another embodiment it may be ordered to be said at least one destination address range. As a further alternative, the destination address range may be a dedicated address range associated with the layout. In the event that the destination address range is said at least one destination address range, then the control signal issued by the settlement controller shall cause the relevant address translation structures to be updated prior to performing the transfer operation so that any access requests are issued in accordance with performing the transfer operation and related to the data being transferred will point to an address within the destination address range and on that basis will be intercepted by the redirect controller. If alternatively the destination address range is chosen to be said at least one source address range, then the relevant address translation structures may not be updated before the transfer operation begins, so that any access requests issued during the transfer operation will be issued to addresses within the source address range and will be intercepted by the redirect controller accordingly. Once the transfer operation is complete, then the memory management structures may be updated so that subsequent accesses to the relevant data will point to addresses within the destination address range.

In the example where a dedicated array-related address range is used, then prior to performing the transfer operation, the relevant address translation structures are updated so that any access requests issued with respect to the data being transferred, while performing the transfer operation, will are issued to addresses within the array's exclusive address range. In such a provision, it may be directed that the redirect controller will only receive access requests that specify an address within that exclusive address range, and thus need not determine whether or not an access request needs to be intercepted. Specifically, any access request received by the redirection controller while performing the transfer operation will be treated as intercepted and thus submitted to the memory redirection operation. Once the transfer operation is complete, then the address translation structures can be updated again so that any subsequent accesses to the associated data will point to addresses within the destination address range.

There are a number of ways in which the memory redirection function can be performed by the redirection controller. In a first exemplary embodiment, the redirection controller is arranged to perform said memory redirection function such that: when the intercepted access request is a read access request, the destination address is mapped to a corresponding source address within said at least one address range source address to cause a read operation to be performed by said corresponding source address, and when the intercepted access request is a write access request, the destination address is mapped to a corresponding source address within said at least one source address range and to a corresponding destination address within said at least one destination address range to cause a write operation to be performed on both the corresponding source address and the corresponding destination address. Such an approach ensures that the original version of the data and the copied version created within the at least one destination address range remain in sync, but repeat the write operations. However, the overhead of this approach is likely to be small if the address ranges in question are not overused and accordingly the incidence of such write access requests during the run of the transfer function will be few.

In an alternative embodiment, said data transfer controller is arranged to maintain a progress file of the transfer operation, while the redirection controller is arranged to perform the memory redirection operation such that: when the destination address of the intercepted access request is associated with an whose data has yet to be transferred by the transfer function, the destination address is mapped to a corresponding source address to cause an access to be performed at that corresponding source address, whereas when the destination address of the intercepted access request is associated with an address of whose data has already been transferred by the transfer function, the destination address is mapped to a corresponding destination address to cause an access to that corresponding destination address to be performed. Such an approach requires the redirect controller to monitor the information maintained by the data transfer controller about the progress being made with the transfer operation to decide how to process the intercepted access request, but avoids the requirement to retry the write operation where the intercepted access request is a registration request. Often, the transfer operation is performed sequentially with respect to addresses within the source address range(s), and accordingly the status information required to determine what data has been transferred and what data remains to be transferred is relatively small.

In a still further alternative embodiment, the data transfer controller may be arranged to maintain a progress file of the transfer operation, while the redirection controller is arranged to perform the memory redirection operation such that: when the destination address of the intercepted access request is associated with an address whose data remains to be transferred by the transfer function, the data transfer controller is ordered to initiate the transfer of a data tier that includes the data associated with the destination address, before processing the intercepted access request, and when the destination address of the intercepted access request is related to an address whose data has already been transferred by the transfer function, the destination address is matched with a corresponding address which is one of the corresponding source address and the corresponding the destination to cause an access to that corresponding address to be performed.

In one embodiment, when the destination address of the intercepted access request is associated with an address whose data has already been transferred by the transport function, the destination address is mapped to the corresponding destination address, since the most up-to-date version is assumed to be kept within the address range destination. However, in an alternative implementation, a copy to write mechanism could be used where, when a write operation is performed, the original data at the source address is copied to the destination address and then the data at the source address is written to. In this scenario, it would be appropriate, when the destination address of the intercepted access request is associated with an address whose data has already been transferred by the transfer function, to map the destination address to the corresponding source address. For the following analyses, it will be assumed that the destination address corresponds to the destination address according to the first option discussed above.

There are a number of ways in which the intercepted access request can be processed when it relates to data that remains to be transferred, after the transfer of a data tier that includes the data associated with the destination address has been initiated. For example, in one implementation, the access request may be temporarily delayed while transferring this layer of data, the progress file is then updated to indicate that the data has been transferred, and then the access request is processed, mapping the destination address to a corresponding destination address. However, performance can be improved by actually merging the processing of the access request with the transport of the data tier. For example, transferring the data tier would involve the data transfer controller reading the data tier from the relevant source address range and then writing that data to the relevant destination address range. In case the access request is a read access request, then after the data is read, the required data for the access request can be obtained directly from the read data tier and returned for the purpose of processing the access request. Similarly, if the access request is a write access request, then after the data tier is read, the write data identified by the write access request can be merged into the read data, with the merged merged data then written to the area destination addresses, thereby processing the write access request when performing the transfer of the data tier from the respective source address range to the relevant destination address range.

In one embodiment, the arrangement may further include control stores for storing control information used to control the performance of the transfer operation by the data transfer controller, the control store storing an indication of said at least one area source addresses, an indication of said at least one destination address range, and progress indicator data which identifies the progress of the transfer operation. If desired, additional information can also be kept. For example, control data can be used to indicate a specific type of read access request that should be used when reading data from the source address space (as discussed in more detail later, this can improve the utilization of cache causing cached copies of data in the source area to be invalidated) or a valid flag or other similar element may be used to indicate the records whose content is related to a transfer operation that has not yet completed. Upon completion of the transfer operation, the associated valid flag may then be cleared, indicating that the record may be reused for a subsequent data transfer request.

As mentioned earlier, in some implementations the destination address range can be either said at least one source address range, or said at least one destination address range. In one implementation, the redirection controller may be ordered to receive all access requests issued to memory while the transfer operation is in progress and determine which of those access requests should be intercepted, while in other implementations the redirection controller may to receive only a subset of the requests, with the interface determining which subset the redirect controller is to receive. In one implementation the redirection controller may be ordered, during the execution of the transfer operation, to refer to the control store to determine whether a received access request is to be intercepted and thus submitted to the memory redirection operation.

In particular, through such an approach, the redirect controller can detect when the address specified by an access request falls into at least one destination address range (where the at least one destination address range is used as the destination address range) or the at least one address range source address range (where at least one source address range is used as the destination address range) and accordingly can detect which access requests should be intercepted.

In the case where the destination address range is an exclusive address range associated with the provisioning, then no such check is required, since the redirect controller can be provisioned so that the only access requests it receives are access requests that specify addresses associated with the array's exclusive address space and will perform the memory redirection function for all such received access requests. The control store can then be referenced when performing the memory redirection operation to determine how to redirect the access request, depending on the memory redirection technique being used.

In one embodiment, the processing element is arranged to implement the translation of virtual addresses to corresponding physical addresses and has access to an address translation store to store address translation data used to translate a virtual address to a physical address within a page of said memory, said address translation data being derived from descriptor information stored in page tables within said memory, and the data transfer request being issued for the purpose of transferring data from at least one source page to at least one destination page within memory. Migration of data from one or more source pages to one or more destination pages in memory can occur for a number of reasons within systems that implement virtual addressing. For example, it may be desirable to migrate a number of non-contiguous pages in physical memory to an area of physical memory where they can be merged to form a larger, contiguous, physical page (referred to herein as a pooling operation). Alternatively, it may be desirable to split a larger page into a number of smaller pages (referred to as a spread operation herein). Data migration can also be done for other reasons, for example ECC (Error Correction Code) enabled data migration, data migration in non-uniform memory access (NUMA) systems, etc.

In such implementations using virtual addressing, it is desirable to take steps to actively check the contents of the in-memory page tables during the transfer operation and to invalidate certain entries in the address translation store to ensure that they are referenced the updated page tables for subsequent access requests issued during the transfer operation. For example, in an embodiment in which the destination address range is selected to include said at least one destination address range, the settlement controller may be ordered, before the data transfer controller performs said transfer operation, to issue a control signal and causing the page tables within said memory to be updated so that virtual addresses that were translated to physical addresses within said at least one source address range will instead be translated to physical addresses within said at least one destination address range, with the settlement controller to further issue a control signal that causes any records providing address translation data for the data to be subjected to the transfer operation to be invalidated within the address translation store.

By taking such measures, it can be ensured that the expired information in the address translation store will not be used for subsequent access requests issued for the data submitted to the transfer operation and instead will be referenced in the updated page tables, as a result of which any such access requests will specify addresses within at least one destination address range and will accordingly be intercepted by the redirect controller.

As mentioned earlier, in one embodiment, the settlement controller may issue control signals to directly update the page tables and/or directly cause the corresponding entries in the address translation store to be invalidated. However, in an alternative embodiment the control signal(s) issued by the settlement controller may take the form of an acknowledgment signal returned to the processing element that issued the data transfer request, with that processing element responding to such an acknowledgment signal to effect the required update to the in-memory page tables and cancel the associated entries in its address translation store. In systems where multiple processing elements are provided that can access memory, that processing element can also issue a signal to the other processing elements that causes them to invalidate the relevant entries in their local address translation stores.

Although it is possible to issue separate control signals from the settlement controller that cause the page tables to be updated and the associated entries within the address translation store to be invalidated, in one implementation it is possible to issue a single control signal that causes both to occur steps.

As mentioned earlier, in an alternative implementation in which the source address range(s) is (are) used for the destination addresses, then it is possible to delay the update of the page tables and invalidate the associated address translation store entries until the transfer operation is complete.

The implementations described above can provide significant performance advantages over prior operating system-controlled migration of data to physical memory. In particular, in the embodiments described above in which the at least one destination address range or the at least one source address range is used as a destination address range, invalidating the associated entries within the address translation store (which may be, for example, a temporary translation lookaside buffer (TLB)) need only occur once during the execution of the data transfer process. In contrast, when the familiar operating system-controlled approach is adopted, the in-memory page tables would initially be updated simply to change the access rights for the source address range to read-only, but without changing the address mapping, and at the same time the associated address range within the TLB structures would be invalidated to ensure that the updated page table information is referenced. Such an approach would ensure that any write accesses issued during the software-controlled data transfer operation would be blocked. Upon completion of the transfer operation, the page tables would again be updated, this time to indicate the destination address ranges and remove the read-only restriction, again this would require invalidating the relevant address range within the TLB structure to ensure that a reference will be made to the updated content of the page tables.

TLB cancellations can cause significant performance issues. For example, it is often the case that there are many processing elements in the system, and TLB cancellation must be performed with respect to each such processing element through the use of an appropriate broadcast function. Furthermore, each processing element that subsequently requires the use of the region must perform a new page-table walk to discover the new translation, and page-table walks significantly increase the latency of memory accesses that fail to TLB, since they require multiple dependent memory accesses to the page tables that must be serialized to service the access request. Therefore, significant performance benefits can be achieved by reducing the number of TLB cancellations required during such a page migration operation.

In one implementation, upon completion of the transfer operation, a subsequent access request is prevented from being intercepted by the redirect controller that specifies a destination address within the destination address range. In the implementations described above in which the at least one destination address range is used as the destination address range, it will be noted that no further steps are required at this point since the page tables will already have been updated to indicate the correct ( s) address range(s) and accordingly once the redirect controller's interception mechanism is disabled, accesses will naturally be directed to the correct location within physical memory.

In many systems, processing elements have associated cache structures to cache data that has been accessed in memory, and a cache coherency protocol is used to ensure consistency between cached data and data stored in data memory. The cache coherency protocol may then be used in connection with access requests issued by the data transfer controller during execution of the transfer operation to ensure access to a more up-to-date version of data identified by said access requests from the data transfer controller.

The data migration operations described above can result in inefficient use of cache storage space, as it can result in the same data being cached for both the source address range(s) and the destination address range(s). However, in one embodiment the data transfer controller may be arranged to free space within such cache structures when performing the data transfer operation. In particular, the data transfer controller may be directed, when issuing read access requests and performing the transfer operation, to read the data within said at least one source address range, to use a specified type of read access request the which causes any cached copies of this data to be invalidated when implementing the cache coherency protocol.

In a particular implementation, the specified type of read access request is a read-only access request. When such a read-only access request is issued, then a cache coherency circuit within the system will perform coherency operations on the relevant cache structures to determine the most up-to-date version of the data (if any cache structure holds a version of data that is more up-to-date than the version in memory), with that version of the data being returned to the data transfer controller. Further, the cache coherency protocol will require that each cached copy be invalidated, and accordingly such a process will naturally free space from any cache structures holding a copy of the data at the source address.

This process can be particularly beneficial in systems where multiple processing elements are provided, each of which has its own associated cache structure or cache structures, since by benefiting from the rules of the cache coherency protocol, many of these cache structures may invalidate each copy of the data they have cached in association with the source address range, thereby providing significant cache utilization benefits.

The transfer operation performed by the data transfer controller can take a number of forms, but in one implementation it is used to perform one of the following types of data transfer: a pooling of data from multiple source address ranges into a single destination address range, a spread of data from a single source address range to multiple destination address ranges, or a transfer of data from a source address range to a destination address range of the same size.

In addition, the transfer function may include a move function or a copy function. According to a copy operation, data is copied from the at least one source address range to the at least one destination address range, but the data in the source address range is also kept as valid. According to a move operation, data is moved from the at least one source address range to the at least one destination address range, while the data in the at least one source address range is invalidated (for example by issuing separate delete commands if required).

In one embodiment, the arrangement described above may be used within a system interface. In particular, a system may be provided which includes: a plurality of processing elements and an interface connected to said plurality of processing elements and for controlling access to a memory by said plurality of processing elements, the interface having a machine transfer configured by an arrangement according to the embodiments described above, for performing a transfer operation on behalf of one of the processing elements for the purpose of transferring data from at least one source address range to at least one destination address range while allowing processing to continue of the access requests issued by the plurality of processing elements with respect to the data submitted to the transfer operation during the execution of the transfer operation.

Accordingly, the transfer engine provides a hardware mechanism within the interface to which processing elements can offload data transfer requests, with this transfer engine having the ability to perform the required transfer operation in the background in a manner that is transparent to the software that is performed on the processing elements. In particular, it is however possible to process subsequent access requests issued by any processing element with respect to data submitted to the transport operation without waiting for the transport operation to complete, by intercepting such access requests by the transport engine's redirection controller, and executing the associated memory redirection function in order to process these access requests.

When the transfer engine is used within the interface in the manner described above, it can be arranged to respond to other input signals to control the execution of the transfer function. For example, the interface will have a certain maximum bandwidth, and other traffic will be routed through the interface at runtime of the transport operation by the transport engine. Running the transfer operation requires a number of read and write access requests to be issued by the transfer engine in order to read data from memory and write data back to memory and this can impact the bandwidth available for other functions. However, in one embodiment the transport engine may be arranged to respond to an indication of bandwidth usage within the interface to slow down the execution of the transport operation. Therefore, during periods of heavy traffic or periods of running latency-sensitive operations, the transport engine can be ordered to slow down the execution of the transport operation and make less use of bandwidth, thereby freeing up bandwidth for use by other operations . Since the transfer operation is performed as a background task and does not require subsequent access requests to be blocked, the increase in time required to execute the transfer operation when it is slowed down in such a way does not become problematic. Therefore, the described technique provides significantly improved flexibility since the transfer function can be performed as a background task taking into account the requirements of other functions performed within the system, in particular the bandwidth within the interface required by such functions.

In one embodiment, in cases where each of several separate memories is associated with an interface, a NUMA-like system may be used. Accordingly, the system in such an arrangement may further include: an additional interface connected to said interface and for controlling access to an additional memory by said plurality of processing elements, the additional interface having an additional transfer engine configured by an arrangement as claimed in any preceding claim, for performing a transfer operation on behalf of one of the processing elements for the purpose of transferring data from at least one source address range to at least one destination address range while allowing the processing of requests to continue access rights issued by the plurality of processing elements with respect to the data submitted to the transfer operation while the transfer operation is being performed.

Therefore, in such implementations, a transport engine will be provided within each interface, and thus in association with each memory.

There are a number of ways in which individual transfer machines can be controlled to perform the required transfer functions. In one embodiment, the transfer engine is used to manage the transfer operation when the at least one destination address range is within said memory, while the additional transfer engine is used to manage the transfer operation when the at least one destination address range is within the said extra memory.

Accordingly, in such an embodiment, the transfer engine associated with the memory comprising the at least one destination address range is used to manage the transfer operation. Even in the case where the at least one source address range is within a different memory, this reference engine can still perform the transfer function, through its connection to the other interface or interfaces.

Specific embodiments will now be described with respect to the diagrams. Figure 1 is a block diagram of a system including a transport engine 35 according to one embodiment. The system includes a plurality of processing elements 10, 20 which are connected via an interface 30 to a memory 40. Although two processing elements are shown for simplicity, it will be appreciated that in any particular embodiment there may be a different number of processing elements connected to the interface.

The processing elements shown use virtual addressing schemes and thus the virtual addresses will be converted to physical addresses within memory 40 so that when a processing element issues an access request intended to access a memory location, that access request as forwarded to interface 30 specifies the physical address of the memory location to be accessed. In a typical manner, memory 40 may be organized into a number of pages, and page tables 45 may be provided within the memory which include descriptors used to determine how virtual addresses should be translated to corresponding physical addresses. addresses. Each processing element 10, 20 may have an associated translation look-ahead buffer (TLB) 15, 25 in which the address translation data resulting from the page tables 45 can be cached to improve the speed of translation from virtual to physical addresses . Specifically, when a virtual address that does not fit into the TLB is issued, it is necessary to perform a page table walk operation with respect to page tables 45 in memory 40 in order to sequentially traverse multiple page tables to generate the necessary address translation data for this virtual address. Once this address translation data is determined, it can be cached within the local TLB.

The address translation data cached in the TLB will typically specify not only how the virtual address is translated to a physical address, but also any associated permission attributes, such as whether the location is read-only and write-only. read, can be cached, etc.

During normal operation, one or more of the processing elements may decide that it is appropriate to seek to transfer data from one or more pages in memory to one or more other pages in memory, this operation generally referred to herein as data migration. For example, it may be considered appropriate to merge several smaller pages into one larger page (referred to herein as the aggregation operation), or conversely in some cases it may be considered appropriate to split a larger page into several smaller pages (referred to herein as dispersion mode). Alternatively, it may be desirable to move data from one page to another page.

According to the embodiments which will be discussed in more detail herein, the data transfer engine 35 is provided within the interface 30 to manage such data migration operations. Specifically, the data transfer engine 35 is arranged to respond to a data transfer request issued by one of the processing elements 10, 20, to handle the required transfer operation on behalf of that processing element, leaving the processing element free to continue the its functions. In addition, the data transfer engine includes a redirection controller which is arranged, during the execution of the transfer operation, to intercept certain access requests issued by the processing elements 10, 20 and in particular access requests made with respect to the data which are the object of the transfer function. For such access requests, the data transfer engine performs a memory redirection operation that allows access requests to be processed without waiting for the transfer operation to complete. Accordingly, such access requests can be handled asynchronously from the execution of the transport function and thus without the need to block any such access requests. This can result in significant performance improvements. In addition, the mechanism used by the data transfer engine 30 reduces the number of times required to invalidate entries in the TLBs 15, 25 when performing the transfer operation, compared to prior art approaches that manage the data transfer process. with software under the control of the operating system within one of the processing elements.

The techniques of the described embodiments can be used regardless of whether the processing elements have associated cache structures or not. However, as shown in Figure 1, processing elements 10, 20 may have one or more cache structures 50, 55 that are used to cache data held in memory 40 to improve performance. In such cases a cache coherency circuit 60 will usually be provided which will ensure that coherency is maintained between the data held in memory and the various copies which may be held within the caches 50, 55. Specifically, when a request is issued access by one of the processing elements that identifies a physical address in memory 40, the cache consistency checker 60 may determine whether any of the cache structures 50, 55 can maintain a copy of the data associated with that physical address, in which case a snoop circuit is used within the cache coherency check circuit to issue snoop requests to the respective caches to determine whether the data exists. With such an approach, access to the most up-to-date version of the data can be ensured. Depending on the coherency protocol used, caches subject to snooping operations may return data to the cache coherency check circuit 60 when it is determined that the data associated with the address specified by the snooping request is held in the cache and/or cause a cached copy of any such data to be invalidated. In addition to the dependence of such actions on the coherence protocol used, they may also depend on the type of access request issued by the processing elements 10, 20.

In one embodiment, as will be discussed later, when data transfer engine 35 performs a transfer operation to move a tier of data from one or more source pages to one or more destination pages within memory 40, it will issue a series of read access requests and write access requests to read the data required to be moved and then write that data to the landing pages. Access requests issued by the data transfer engine 35 will be reviewed by the cache coherence control circuit 60 in the same manner as access requests issued by the processing elements 10, 20. Using a specific read access request format, this can ensure that any cached copies of the data being moved and associated in the caches 50, 55 with the source address range(s) will be invalidated and thereby free resources within the cache. It will be appreciated that once the transfer operation is performed, the data will remain within the destination page(s), having the associated destination address range(s), and thus any cache copies associated with the source address range will not be used. Therefore, by invalidating these copies during the data transfer process, a very efficient mechanism can be provided for removing redundant data from caches 50 , 55 .

Figure 2 is a block diagram illustrating in more detail the data transfer engine 35 of Figure 1, according to one embodiment. A settlement controller 100 is provided which is arranged to receive the data transfer requests from the processing elements 10, 20. Upon receiving a data transfer request, the settlement controller populates certain information within the control registers 105, such information providing for the one or more source address ranges from which the data is to be transferred and the one or more address ranges to which the data is to be transferred. Typically the source address range(s) and destination address range(s) will be specified by the transfer request issued by the processing element and this information is extracted from the request and filled into one or more control registers . Additional information may also be specified, for example specifying whether the transfer should implement a copy (where after the data is moved, the data remains valid within the source address range(s)) or a move ( where after the data is transferred, the data within the source address range(s) is invalidated). The transfer request may also specify some further information, for example whether the particular form of read access request mentioned earlier should be used to help flush redundant information from caches.

Once the relevant information within the control registers 105 is populated, the settlement controller may issue an acknowledgment signal back to the processing element, this acknowledgment signal being an example of a form of a control signal that may be issued by the settlement controller. In particular, in one embodiment the processing element is responsive to receiving the identification signal to take steps to update the relevant page tables 45 to ensure that when the transfer operation is performed by the data transfer engine 35, any virtual addresses within the relevant virtual area of addresses will be mapped to target addresses within a specific range of target addresses which will then be intercepted by the data transfer engine. In a particular example implementation, the processing element may be ordered to modify the appropriate page tables so that such virtual addresses will map to addresses within the one or more destination address ranges and will not continue to map to addresses within the one or more source address ranges. As discussed in more detail later, the redirection controller 115 within the data transfer engine may then intercept any access requests issued to addresses within the one or more destination address ranges during execution of the data transfer operation, and perform an memory redirection with respect to such access requests.

In addition to updating the page tables, the processing element may also invalidate any relevant entries within its local TLB, i.e. entries which provide address translation data for the relevant virtual address space, and will also typically broadcast a message to the other processing elements and will force them to invalidate such writes to their local TLBs. Invalidating the associated contents in the TLB ensures that if an access request is issued by any of these processing elements using a virtual address within the associated virtual address range, a hit in the TLB will not be detected and cause a walk procedure to be used page table, as a result of which the new mapping provided in the updated page tables 45 will be retrieved and used to convert the virtual address to a physical address. If desired, this new address translation data can then be cached within the TLB.

As an alternative to using such an acknowledgment signal to the acknowledgment element to force the processing element to undertake the page table update process and the TLB invalidation process, the settlement controller can issue control signals directly to the memory for the update of page tables 45 and may additionally issue one or more control signals that will cause associated entries in the TLBs of processing elements 10, 20 to be invalidated.

After such measures have been taken, a data transfer controller 110 within the data transfer engine 35 may be activated to begin executing the transfer operation, using the information held in the control registers to determine the source addresses from which the data will be read. and the destination addresses to which this data should then be written in order to perform the required data migration within memory 40. Redirection controller 115 will typically be activated simultaneously so that while data transfer controller 110 is performing the transfer, the redirection controller 115 monitors the access requests issued by any of the processing elements 10, 20 in order to detect instances in which those access requests specify addresses within a target address range. According to the earlier example in which the page tables are updated before the transfer operation is performed to ensure that the associated virtual addresses map to physical addresses within the one or more destination address ranges, the redirect controller may monitor for access requests that specify a physical address within one or more destination address ranges and upon detection of such an access request shall intercept that access request and perform a memory redirection operation. The memory redirection function will be discussed in more detail later, but it aims to ensure that the access request can be processed while the transfer operation is in progress, while ensuring that the data remains unchanged.

As shown in Figure 2, the redirection controller 115 will therefore generate read or write addresses from redirection in response to the read or write addresses it intercepts. Some of the redirect read or write addresses may actually be the same addresses as received, for example in some cases for an intercepted access request it may be decided that the redirect address may remain the same as the address specified by the request access.

Addresses from redirection are forwarded to the load and store queues 120, while the associated read or write data is also routed through the load and store queues as shown in Figure 2. As also shown in Figure 2, the data path need not be intercepted by the redirect controller 115.

There are a number of ways in which access requests that are not intercepted by the redirect controller can be processed. In some implementations, such access requests are not even reviewed by the redirect controller, since the interface will not route such access requests to the data transport engine. Alternatively, in some implementations the redirection controller may review each access request, but for any access request that is determined not to require interception, that access request could be ordered to bypass the load and store queues 120 if such access request shall not conflict with address ranges subjected to data transfer operations by the data transfer engine. In this second case, a separate set of ports could be provided to which any access requests from the redirect controller that it has determined do not require interception could then be forwarded.

In the implementations shown in Figure 2, the load and store queues 120 are shared between the redirection controller 115 and the data transfer controller 110. Accordingly, the data transfer controller will issue a series of read and write addresses to the load and store queues 110 in order to cause the required data to be read from the source addresses and then written to the required write addresses. As shown in Figure 2, the load and store queues 120 may maintain one or more temporary memories 125 in which data read from memory during the transfer operation can be temporarily stored before being written back to memory. Thus the data itself does not need to be returned to the data transfer controller 170, but instead progress information about the progress being made on the various read and write requests can be forwarded back to the data transfer controller, which in one implementation also completes the information within the control registers 105 as an indication of the progress being made. For some types of memory redirection operation, this progress information within the control registers may be referred to by redirection controller 115 when deciding how to redirect a received physical address of an intercepted access request.

By using the structures of the load and store queue 120 for both the access requests selectively modified by the redirect controller and the access requests issued by the data transfer controller during the transfer operation, it is possible to detect and deal with any possible contention status within load and store queues. There are a number of ways in which the load and store queue structure 120 can be arranged to detect and deal with such race conditions. For example, in one implementation the data transfer controller 110 may be ordered, before issuing a read request to a source address, to commit a substitute write request (without any data) to the destination address in a write of the load queue structure and storage 120. This register can be used to delay conflicting accesses until the transfer operation is complete. The data transfer controller can then update the progress status within the control registers 105 and issue a read access request for the source address. Once the read response arrives from memory, the data transfer controller can then issue an actual write request that updates the proxy request that was committed earlier. At this point, the load and store queue structure 120 can then forward the write request to memory. By adopting such a sequence, this ensures that any read or write request from a redirect that overlaps with an address specified in a surrogate write record in the load and store queues is delayed until the write is forwarded to a "real" write after the read data has acquired from memory.

Such an approach may also provide some performance benefits in the way access requests are processed. For example, if an access request is issued for a write to an address within the destination address range, and the redirection controller determines that it is appropriate to transmit that write to the destination address, but it overlaps with the data transfer controller performing a transfer with respect to at the destination address, then once it is determined that the required data has been read from the source address but not yet written to memory, the new record data from the access request can be merged into the record data in buffer 125 so that the updated record data to be exported to memory.

Figure 3 illustrates an example arrangement of information within control registers 105 in accordance with one embodiment. According to this embodiment, a plurality of slots 150 may be provided, each slot including a number of fields. A first field 155 is used to identify a source region, while field 160 is then used to identify a corresponding destination region. A field 165 may optionally be provided to identify the current status of the data transfer being performed with respect to that source and destination area, and a flag field 170 may also be provided to store additional information if required. As an example of such flag information, a flag can be set to specify whether read access requests associated with data transfer should be issued as read-only requests, so as to cause any cached copies within of the cache structures 50, 55 which are associated with the source address range. Finally, a valid flag 175 may be provided, which may be set to determine whether the socket includes information about a valid data transfer that has yet to be completed.

In one embodiment, each of the slots is arranged to accommodate information for a contiguous address range of a certain size, for example the smallest possible page size. By ordering the slots in this way, it can simplify the address comparison logic used by the redirect controller 115 when determining whether an access request specifies an address that is within a range of a valid slot. However, in an alternative implementation it may be possible to reconfigure the size of the address range associated with each slot, in which case a general size field may be provided within the general status information 180 to specify the size information.

Therefore, purely by way of illustration, when performing a data migration operation to merge two pages with a minimum page size into a larger destination page, two separate sockets may be transmitted, the first covering the source address range of the first source page and the second to cover the source address range of the second source page. The destination address range associated with the largest landing page will then be divided into two sub-ranges, with the first sub-range stored within the first slot and the second sub-range stored within the second slot.

If desired, an additional general status 180 may also be provided. For example, a general status flag may be set when the settlement controller 100 determines that the data transfer controller may begin performing the transfer operation. Specifically, as discussed earlier, there are a number of settlement steps that must be completed before the transfer can begin. In addition to settling the contents of the control registers, the settlement controller may additionally await confirmation from the processing element that any relevant page table updates and TLB cancellations have been performed, before setting the general status flag which enables the data transfer controller 110 to start transfer mode. If desired, a similar redirection enable flag may also be provided for the redirection controller 115. Typically the redirection controller will be enabled to perform any required redirection for access requests issued while the data transfer controller is actively managing the transfer operation, but redirection may also be required to run for a period of time either before the transfer operation begins, or after the transfer operation is complete, depending on the target address range used by the redirection controller when identifying access requests to intercept. For example, in cases where the redirect controller is arranged to intercept addresses within the destination address range, one implementation will enable redirection before updating the page table and subsequently starting the transfer operation. Conversely, when the redirect controller is arranged to intercept addresses within the source address range, the redirect controller in an implementation will remain enabled until the transfer operation is complete and the page table is updated.

As an alternative to providing a separate redirect enable flag within the general state 180, valid flags 175 can for example be used to determine when the redirect controller should be enabled. In such a case, failover would always be enabled pending copy operations.

Figures 4A and 4B provide a flow diagram illustrating the operation of the system of Figure 1 in accordance with one embodiment, in order to implement a data transfer within the memory 40. In step 200, the data transfer engine 35 determines whether it has been received a new transfer request. When a new transfer request has been received, then in step 205 the control registers 105 are populated with the source and destination address ranges and any other relevant information, as discussed earlier.

In one implementation, the data transfer engine may be ordered not to accept a new transfer request while another transfer request is already pending. In one embodiment, the system software would be arranged to ensure that transfer operations are ordered and prevent such a situation from occurring, but in an alternative embodiment the data transfer engine may be arranged not to accept a transfer request that presented at its entrance while another transfer request is pending.

Once the control registers are filled, then in step 210 the settlement controller again issues an acknowledgment signal to the requesting processing element. In step 215 the requesting processing element then updates the page tables 45 so that the relevant virtual addresses map to the destination address range(s) rather than the source address range(s). Specifically, in this implementation it is assumed that the target address range is chosen to be the destination address range(s) and that access requests specifying addresses within the destination address range(s) will be intercepted by the controller redirection. However, in other implementations, as discussed earlier, the target address range may instead be the source address range(s) in which case the page tables will not be updated before the transfer operation is performed, but instead will be updated afterwards.

In some implementations, the data transfer engine may determine the target address range to use depending on the type of migration being performed. For example, for an aggregation operation in which multiple contiguous source address ranges are merged into a larger contiguous destination address range, it may be advantageous to use the contiguous destination address range as the destination address range, since using a contiguous range makes the circuit address matching used by the redirect controller to determine significantly more simply whether an access request should be intercepted. Conversely, when performing a scatter operation to scatter data from a contiguous source address range to multiple non-contiguous destination address ranges, it may be preferable to use the single contiguous source address range as the target address range.

Returning to Figure 4A, in step 220 the processing element invalidates any TLB entries it has for the associated virtual addresses and also broadcasts a message to the other processing elements to do the same. Again, this assumes that the destination address range(s) is being used as the target address range. In an implementation in which the source address range(s) is used as the target address range, then the TLB entries will not be invalidated before the transfer operation is performed, but instead will be invalidated after the transfer operation is completed.

After steps 215 and 220, the process then continues to step 225 where the data transfer controller is activated to begin transferring the data from the source addresses to the destination addresses.

As shown next in Figure 4B, it is determined in step 230 whether the transfer operation has been completed, and as long as the transfer operation is not completed, the process continues to step 235, where it is determined whether a new access request has been received from the redirect controller 115 .The process loops through steps 230 and 235 until either the transfer operation completes or an access request is received.

When an access request is received, the redirect controller then determines in step 240 whether the physical address specified by the access request falls within the range of destination addresses specified within the control registers. If it does not, then the access request is simply transmitted to the memory system 40 in the usual manner at step 250.

However, if the physical address falls within the destination address range in the control registers then the redirection controller 115 applies a memory redirection operation in step 245 to determine the appropriate physical address or addresses to be transmitted. As will for example be discussed later with reference to Figure 5A, according to one implementation of the memory redirection function, when write access requests are received, the memory redirection function may cause a write to be performed on both the source address and the corresponding destination address , effectively causing two access requests to be generated in step 245 before proceeding to step 250.

After transmitting the access request or access requests to the load and store queues 120 in step 250 , the process returns to step 230 .

Once it is determined in step 230 that the transfer operation is complete, then the process continues to step 255, where the associated slot or slots in the control store are invalidated and any further redirection is then prohibited. By disabling the redirection function of the redirection controller 115, this means that any subsequent access requests issued to addresses within the destination address range will directly access the correct addresses in memory. No additional action is required since the page tables will already have been previously updated in step 215 to determine the correct mapping to use after the data transfer is complete.

The memory redirection operation performed in step 245 can be implemented in a number of ways. Figure 5A illustrates an example embodiment. In step 300, it is determined whether the access request is a read request, and if so, the address identified and given by the access request is matched to a corresponding source address within the source address range(s). The process then continues to step 250 of Figure 4B.

However, if the access request is not a read access request, i.e., it is a write access request, the process continues to step 310 where the implementation of the memory redirection function effectively causes two access requests to be generated. One access request has a specified address which corresponds to the source address, while the other uses the destination address as determined by the access request received in step 235. This therefore ensures that write operations occur at both the old address and the new one. address and thus ensures that the original version and the copy remain in sync. Although it does create duplicate write operations, the overhead of this approach is likely to be low if the source and destination regions undergoing the data transfer operation are not heavily used during the execution period of the data transfer operation. After step 310, the process then continues to step 250 of Figure 4B.

Figure 5B illustrates an alternative implementation for performing a memory redirection operation in step 245 of Figure 4B. In step 320, it is determined by the redirection controller 115 whether the data at the specified address of the access request has already been transferred. As discussed earlier, in one embodiment this determination may be made by the redirection controller 115 with reference to the contents of the control registers 105 and for example by looking at the current state field 165 within the relevant slot. If the specified address has already been transferred, then the process continues to step 330 where the specified address is mapped to the destination address. In the embodiment described in Figures 4A and 4B, the specified address is already the destination address, so in step 330 this destination address is simply retained as the access request address which is transmitted in step 250.

However, if the specified address has not yet been moved, the specified address is mapped to the source address in step 325 before proceeding to step 250. Therefore, according to this embodiment, the redirect controller forwards accesses to locations that have not yet copied in the source location and the accesses to locations they have copied to the destination location. Assuming that the data transfer operation is performed sequentially with respect to the addresses within the address range, only a small amount of state is required to keep track of which locations have and have not.

Figure 5C illustrates yet another alternative implementation of the memory redirection operation in step 245 of Figure 4B. In step 340, it is determined whether the specified address has already copied, and if it has, the process continues to step 345, which is equivalent to step 330 of Figure 5B discussed earlier. The process then continues at step 250 to step 350 of Figure 5C.

However, if the specified address has not yet copied, then in step 355 the redirect controller 115 contacts the data transfer controller 110 to initiate the transfer of a data layer which includes the data associated with the specified address of the access request. The size of the transferred data tier can vary by implementation, but in one implementation it is a cache line sized data tier, while the data transfer engine maintains within the control registers 105 a bitmap of the cache line sized data tiers that have been copied to determine which ranks have copied and which have not.

The process then continues to step 360 where the access request is processed in step 250. The access request can be processed in a number of ways. For example, in one implementation, the access request may be paused until the transfer of the data tier started in step 355 is completed and the bitmap of the cache line size tiers they have copied is updated. At this point, the access request may then be processed by implementing a step equivalent to step 345 to transmit the access request to the destination address.

However, in an alternative implementation further savings in performance can be achieved by essentially merging the access request processing with the tier transfer process. For example, in the case of a read access request, after the data transfer controller 110 has read the necessary data back into the buffer 125 of the load and store queues 120, the read access request can then be serviced using the contents within the cache without requiring a separate memory read access request to be issued. Similarly, if the access request is a write access request, once the data is read from the data transfer controller 110 into the buffer 125, the new write data from the write access request can be merged into this data tier, before the write of the buffered data to the destination memory locations to complete the data tier transfer.

Figures 6A through 6C schematically illustrate an example implementation of the process of Figures 4A and 4B for the example in which two smaller source pages a1, a2400, 405 are merged into a larger destination page b 410 within physical memory. Entries 415, 420 schematically depict the relevant descriptor information within the page tables that forces the mapping of the virtual-to-physical address translation to the respective source address zones 400, 405. As depicted in Figure 6A, adjacent entries 415, 420 depict that the two source zones 400, 405 have adjacent ranges of virtual addresses, while the purpose of the data transfer operation is to repeat the mapping of non-contiguous physical pages 400, 405 into a contiguous range of physical addresses 410. The copy machine is schematically illustrated by step 430, while entries 435, 440 represent the control information stored within two slots. within control registers 105, with each slot specifying one of the source address ranges and a corresponding portion of the destination address range.

Accordingly, after storing the control registers information, the copy engine knows the source areas 400, 405 and the destination area 410. At this point, the functions of the data transfer controller 110 and the redirection controller 115 can be activated to start the data transfer operation and redirect control. As illustrated in Figure 6B, and as discussed earlier with respect to step 215 of Figure 4A, the page tables will be updated to create a new entry 445 that maps the enlarged contiguous virtual address range to corresponding physical addresses within the destination address range 410 .As mentioned earlier with respect to step 220 of Figure 4A, the relevant TLB entries will also be invalidated so that any access request issued later while the data transfer operation is being performed, and which is related to the data being transferred, will cause the of the page table walking process to obtain the address translation data encapsulated within the page table descriptors represented by entry 445.

As shown by line 450, any access request issued that specifies a destination address within the destination address range 410 will be intercepted by the copy engine 430. The copy engine will then perform the memory redirection operation to determine which physical addresses it is made to access, using some of the approaches of Figures 5A to 5C discussed earlier. At the same time, the copy process will be performed by the copy engine, as schematically indicated by arrow 460. In one embodiment, exclusive read accesses are used for read operations performed with respect to the source address space, with write accesses being used thereafter to store the results in the new destination address range 410. Using exclusive read accesses invalidates cached copies of the data associated with the old source address range and thus effectively frees up cache space.

As shown in Figure 6C, once the copy operation is complete, the mapping within the copy machine is cleared, invalidating the associated control information in the control registers. This stops any further interception of access requests issued to destination addresses within the destination address range. Instead, such access requests are simply routed in a normal manner to the destination address range, since the page tables already contain the correct information to provide this mapping.

In the example of Figures 6A to 6C it is assumed that the destination address range is used as the target address range during the copy process and thus it is the addresses within the destination address range that are intercepted by the copy engine during the copy process. As discussed earlier, in an alternative implementation the source address range(s) could instead be used as a target address range, in which case page tables would not be updated and TLB entries would not be invalidated , until the copy process is complete.

In yet another alternative embodiment, as discussed earlier, a dedicated address range may be associated with copy engine 430, and this process is illustrated schematically in Figure 7, again for the example in which two source address ranges 400, 405 are merged into a destination address range 410 within the memory address space. As shown in Figure 7, a dedicated address range 470 is associated with the copier and is not used for any other purpose. According to this embodiment, when the page tables are updated before the copy operation begins, they change the mapping as indicated by step 1 480 in Figure 7 so that the associated virtual addresses are mapped to the exclusive address range 470 rather than the source address ranges 400, 405. Otherwise, the process continues as shown in Figures 6A and 6B, with any access directed to address range 470 intercepted by the redirect controller and mapped to source address ranges 400, 405 or destination address range 410 as appropriate criteria discussed earlier with respect to Figures 5A to 5C. Upon completion of the copy operation, the page tables are then updated again to change the virtual address mappings and now map to the destination address range 410 rather than the exclusive address range 470 as indicated by step 2490 .

Although the implementation described with reference to Figure 1 shows a Uniform Memory Access (UMA) system, the techniques can also be applied to Non-uniform Memory Access (NUMA) systems, a an example of which is shown in Figure 8. In this example, the NUMA system has two NUMA nodes 500, 510, each of which for the sake of illustration is assumed to have a structure similar to that shown in Figure 1. Each NUMA node 500, 510 has its own associated memory 505, 515 which is connected to a corresponding interface 520, 525. According to the described implementations, each interface has its own data transfer engine 530, 535, while the two interfaces 520, 525 are connected via the path 540. In such an arrangement, each processing element within any of the NUMA nodes 500, 510 may be arranged to access any of the individual memories 505, 515.

When a data transfer request is issued by one of the processing elements, one of the data transfer engines 530, 535 will take responsibility for performing that data transfer and arranging its control registers accordingly. In an embodiment, in which the destination address range(s) is(are) used as the target address range(s) during the copy process, the data transfer engine associated with the memory comprising the range(s) destination address(es) will usually be configured to handle the data transfer process. However, in implementations where the source address range(s) are used as the target address range(s) during processing, then it may be appropriate to define the data transfer engine associated with the memory that includes the source address range(s) as responsible for managing the data transfer function. If the implementation discussed earlier with respect to Figure 7 is used in cases where a dedicated memory address range is associated with each data transfer engine, then any of the data transfer engines could be configured to handle each particular data transfer process, regardless of which memory contains the source address range(s) and which memory contains the destination address range(s).

From the implementations described above, it will be apparent that such implementations provide a hardware mechanism that can be used to manage data migration operations in physical memory. The hardware mechanism used allows the data transfer operation to continue asynchronously to any access requests seeking access to the affected address ranges, preventing the need to block any such access and thereby improving performance. The proposed mechanism can also reduce the number of TLB cancellations required during the data transfer process when compared to known systems that perform such page migration under software control using the processing element's operating system. In addition, the proposed techniques can also improve cache utilization by ensuring that information no longer needed in caches is invalidated during the data transfer process.

In the present application, the words "configured for..." are used to mean that an element of a device has a configuration capable of performing the specified function. In these contexts, a "configuration" means an arrangement or mode of interconnection of hardware or software. For example, the device may have dedicated hardware that provides the specified function, or a processor or other processing device may be programmed to perform the function. The term “configured for” does not imply that the device element must be changed in any way to provide the specified function.

Although exemplary embodiments of the invention have been described in detail herein with reference to the accompanying drawings, it is to be understood that the invention is not limited to these exact embodiments and that various changes, additions, and modifications may be made therein by a person skilled in the art. without departing from the object and spirit of the invention as defined by the appended claims. For example, various combinations of the features of the dependent claims could be made with the features of the independent claims without departing from the scope of the present invention.

Claims (1)

1. An arrangement, which includes: a data transfer controller, responsive to a data transfer request received by the device from a processing element, to perform a transfer operation to transfer data from at least one source address range in memory to at least one destination address range in memory; and a redirection controller arranged, during execution of the transfer operation, to intercept an access request that specifies a target address within a target address range and to perform a memory redirection operation to cause said access request to be processed without waiting for the completion of transfer operation. 2. An arrangement as claimed in Claim 1, further comprising: an arrangement controller arranged to receive the data transfer request and issue a control signal that causes access requests issued while the transfer operation is being performed and associated with the transfer of data from the transfer operation to specify as the target address an address within of the target address range. 3 - A provision that is claimed in the A£i7.nd 9JLTGYP or c \i Irvyrn ip?.rii%or SinifliWfFnw is one of the following: the EV ends with a previous &mftftwrn?mv prae.i rtwqr said at least one destination address range, and j nn ttoriG>hi WVM i-iiphrti^Htpi j.r -rrpi nuAAym 4 An order as claimed by the controller — redirection — is ordered — so that the — being due — lithiturgy of recuperating memory with. way so? when the intercepted access request is a read access request, the target address is matched to a corresponding source address within said at least one source address range to cause the FV-TF) to be disabled. >Gi-|G beat her, GL? IigiL PL/tiitpihi Airythinpi origin, and when the intercepted access request; it is only a write access request, the &FiSftnvm^ ittichii pnipptpih^itii nr |ii p pptiptihi Kignftnvm] pri^pntis mrrnrj. her. in said at least one source address range and to a corresponding destination address within said at least one destination address range so that prOCO'-Tei the pyrclcmi mnr IgiTtmnyini; Fwiwimr tlLit<n>irnnr t<n>n PLAtiit<n<n>ftinSAnvrm of origin, as well as to the corresponding destination address & - A provision as claimed by; the claims;-! -to.3, provided said data-transfer controller is ordered to maintain a<,>progress-file for the transfer-operation, whereas said redirect-controller is ordered to perform said memory-redirection-operation by (toes: itpn the £lG·ithiniti ptigii rrm hinphpi'ti/ini.^nYi piti|ip·ign^ ·p·rL<tvp<tii·| For an address whose data has not yet been mapped to the transfer operation, the destination address is mapped to a corresponding source address to cause an access to that corresponding address to be performed. ^I Rintis kii when the destination address of the intercepted access request is related to an address whose data has already been transferred by the function >,port definition to cause an access to be -executed as -this -corresponding destination address.; An arrangement as claimed in any one of claims 1 to 3, wherein the said P.lrgtiG| said redirection controller is arranged-to perform said memory-redirection function in a-.way that?. when the target address of the intercepted access request is associated with an address of the opiate the ddrdirrn dy> ryrvnv pniri |iJuntpApfki mm LI| 1.IKI1)()for a transfer, the data transfer controller is ordered to initiate the transfer of-a data layer which includes the data associated with the target address, before-processing the intercepted access request'; and otbn — the — target — address — of — the — intercepted — access — request. phr.tisetei mr. a dicythiinpi of the pttiipG the dr-di|irnp rhiin already [irtpfrthri rurn.rq ) ritury; transport, the target address -is matched to a corresponding; address which wine a irpnpl Piim5? npi the pdiktpihi SiPiSftnvm-| destination, to cause an access to that corresponding address.— 7. An arrangement as claimed in any preceding claim, further comprising: control store for storing control information used to control the performance of the transfer operation by the data transfer controller, the control store storing an indication of said at least one source address range, an indication of said at least one range destination addresses and progress indicator data which identifies the progress of the transfer operation. & - An arrangement as claimed in Claim 7, wherein: The solution to the problem the said -at least one destination address range? and the controller c redirection is ordered to tL the Kirkps ti- p-t ^Ritoorgip^ mrtpGroros, ostr.. ni pnpfrrci f h<n»ro ppothik-Rinti^ inghiii to determine; whether a received access request is to be intercepted -and '<m>-<n>·™r< I>o-* -the 'lpitirgia anakatn^™™^ m^imi^ 9, - An arrangement as claimed in any preceding claim, -where the processing element is arranged to implement the translation; of home -addresses-into sfstich>- rpumv-A- SicnftiWcir irm rhri 7GrLsvssi__sr or, the x/frpn itGiAitri^piG Free addresses — for— ...the — storage of — address translation — data — used to convert a -home address- to a -physical address within a page of said memory, after said translation data addresses are derived from descriptor information stored in in-memory page tables while the data transfer request is issued to transfer data from at least one source page to at least one destination page in memory. - An arrangement as claimed in - Claim 9 when appended to Claim 2, —where— the said area of addresses is about) Pisani. tel? cv ) due to) undefined,n a^area of destination addresses, - The settlement auditor is ordered, before the execution of art. )by )itorg(p.s of transfer from the data transfer controller so that a control signal is issued and causes the page tables within the cv to be updated as )by memory as-rr ni rurranircr addresses that are_translated into physical addresses rd r of the ) at least half of the source address range will be translated instead to physical addresses within that range. of at least one destination address range, with the settlement controller issuing a control which. causes the invalidation within the address translation storage of -any; records that provide address translation data for the datamons to be subjected to the rthport operation - THE-; - An arrangement as claimed in Claim 10, wherein the arrangement is arranged to be configured with processing elements having access to memory with each processing element having an associated address translation store, and the arrangement controller is arranged so that It issues a control signal. causes the invalidation of any address translation storage of any documents providing; address translation data for the data that will assist the partition function 12 - An arrangement as claimed in Claim 10 or Claim 11, wherein upon completion of the transfer operation, the redirection controller is prevented from intercepting a subsequent access request that specifies a target address within the range target addresses. 13·. - An arrangement as claimed in any preceding claim, wherein the processing element has access to. at least . a cache structure-, for -the .storing of data in cache — memory — in which — that memory is accessed, a cache coherency protocol is used to ensure. the coherency between cached data, .and ..data stored in memory, and the cache coherency protocol used, in relation to access requests issued by the data transfer controller during the execution of the transport operation - so that . ensures that the data transfer controller has access to the most up-to-date . version-data .where Precious 44 - An arrangement ..as claimed in Claim 1·3, wherein the data transfer controller is arranged, when issuing access requests for -read during -execution of the ■transfer operation with. -purpose to read entity data due to at least — one — region, source addresses, — to — use — a specified type of read-access request which causes any cached ps to be invalidated. of copies, - of these data according to the Application rrm protikLeoiii mwnjpfc k-rinir^ memory- — 15. connects [IP. a multitude of athichrians rp^rgiGtipG ifAfli? the rvtrnfn or at least one associated cache structure, and the data transfer controller is arranged to use said designated access request location for of the said data in the specified memory structures jwrtim^Trvrr m τΛ m said-number of processing elements when implementing the hidden memory coherence protocol 16- - An arrangement as claimed in Claim 14 or Claim 15, wherein the being due to a specified Timer request toast for the read access time, ¥h - An arrangement as claimed in any preceding claim^ wherein said transfer function -is used to perform<■>one of the following types of data transfer? — an aggregation of data from — multiple source address ranges into a single destination address range; multiple destination address ranges, or, a [irtiferous Srftnjipvr.w nmS pirn ttrrieh KicuftmOTcmv -rpr>glcn^ rrc pm itririo; of destination addresses of the same size. 18 — A, arrangement from?. any preceding claim is claimed, wherein said transfer function comprises either a blurring function or a 19.<1>A system which includes: fyrc amount of nTni.xf:irnv.f processing, and mki fiui(ri)V§F.cni prndkdr.m£ni |if. the said plurality of processing elements-and for controlling access to a memory by the said plurality of processing elements, jlf. the flmrmvSgm-| Np ^hri Kmpnprpfnpcirq pm rih™or [inarn/pnpAr h* th pm as claimed by ittiipdipitr preigiu| irni pxioti^ for the cirrc^ Gti pmr 1 nrmnpyfnr transfer - on behalf of one of the Eii^bpyuulut elements, with the data meTHFdra - from at least ·. a source address range to at least one destination address range while allowing continued processing of access requests issued by the plurality of processing elements with respect to the data submitted to the transfer operation upon execution of the transfer operation 20 - One. A feature is claimed in Claim 10, wherein the transport engine is responsive to an indication of bandwidth usage within the interface -to- slow down the performance of the transport function. 24th -<'>A system -as-; claimed in Claim -19 or Claim<1>20, tu unofo comprises: an additional interface connected to said interface and for controlling access to an additional memory by ev due to a plurality of amphibious cells, the additional interface being an additional transfer engine configured by an arrangement such as— .is claimed at any&ever — i precedes a claim, to perform a transfer function; on behalf of one of m processing elements for the purpose of jj<g>rnmAnA 5e5th{-ienth)n i iin irninvn SicufliWcnw TTpricl ciyrnr m t<h>iiIAnipt<h>y jnn TTF. The root ftgnftiwfrrnv 7rpr>npm|irm rttrepL/ti^ titigrin the signification of the processing of the access requests are issued- by the number of processing elements with regard to the data submitted to the liiyymiiih my'iapsimyzTBhta, the duration of the execution of the transfer function. 23--·A mWiT||in when? nFiftwr-rm ptin Axinti Il , <Wm the ri^GiGi |ii:csfsrai vnn rtl 11 P7GG>1 r TP 1 VI P TP dipnriiti TTIG l nrnniwinr ucrnmnnAr the<n>»<n ■ ■■>" area of destination addresses is located within said memory, while the extra transfer engine is used to manage the transfer operation when the minimum destination address range is within it due to extra memory-^- 21 _ Mm methods of evaluating active ieta/Il pre,nial judgments in the new. in response to a data transfer request received by a processing device using a a data transfer controller for performing a transfer function for transferring data from at least one port M in memory, and (c) generating an access request specifying a target address within a target address range and performing a memory redirection operation to cause the resulting access request to be processed; without·. to; expected<,>completion of operation; transfer. 24, - A provision' which includes*. means of -controlling -the transfer of data to perform, in response to a -data transfer request received by the device from a processing element, of a function, transfer to transfer data from at least one array of source-addresses to the mime — at least a wcptoyj SicuOuvoceav destination in memory, can [requirement for intercepting, during the octet of the transport operation, an access request specifying a renfyrm address within a SignftiivfFrnv type irm .jnp; Fittp.