GR20170200059U - Storage circuitry - Google Patents

Abstract

Storage circuitry 64 comprises an array 32 of storage locations 34 arranged in rows and columns, a row buffer 36 comprising a plurality of entries 68 each to store information from a storage location at a corresponding column of an active row 46 of the array 32, ane comparison circuitry 70 responsive to a tag-matching command specifying a tag value 72 to compare the tag value with information stored in each of a subset of two or more entries 68 of the row buffer 36. The comparison circuitry 70 identifies which of the subset of entries, if any, is a matching entry storing information matching the tag value. This allows memory technologies such as DRAM to be used more efficiently as a set-associative cache.

Description

STORAGE CIRCUIT

The present technique relates to the field of storage circuits.

A number of technologies are available for implementing storage circuits for data processing systems, including for example SRAM (static random access memory), DRAM (dynamic random access memory), PRAM (phase-change random access memory), MRAM (magnetoresistive random access memory), etc. Some types of memory technologies, such as DRAM, provide a matrix of storage locations that are organized in rows and columns, while accessing a given storage location requires activating a specific row of the matrix and transferring the data from each location of that row to a row buffer. After a row is activated, it is possible to perform a number of reads/writes to various positions on the row by reading or updating the contents of the row buffer. It is possible to propagate any line cache updates to the corresponding storage locations in the matrix, and when the line is no longer needed, it is possible to close the line using a preload command.

At least some examples provide storage circuits which include:

a matrix of storage locations arranged in rows and columns,

a row buffer which includes a plurality of records, each for storing information from a storage location to a corresponding column of an active row of the matrix, and

comparison circuits responsive to a tag match instruction specifying a tag value for comparing the tag value with information stored in each subset of records of the line cache, and for determining which record from said subset of records, if any, the which is a match record that stores information that matches the value of the tag, that subset comprising two or more line cache records.

At least some examples provide an arrangement comprising: the storage circuitry described above, and

a cache controller to control accesses to the cache data stored in the storage circuit.

At least some examples provide storage circuits that include:

a matrix of information storage media arranged in rows and columns,

means for buffering information from an active row of the matrix, the buffer means comprising a plurality of records, each buffering information from a means for storage in a corresponding column of an active row of the matrix, and

means for comparing, in response to a tag matching command specifying a tag value, the tag value with information stored in each record from a subset of records of the buffer media, and identifying the record from said subset of records, if any, the which is an identity record that stores information identical to the tag value, said subset comprising two or more cache media records.

At least some examples provide a method of accessing information from a storage circuit comprising a matrix of storage locations arranged in rows and columns, the method comprising,

transferring information from storage locations in an active row of the matrix to a row buffer that includes a plurality of records, each record storing information from a storage location in a corresponding column of the active row, and

in response to a tag match command specifying a tag value, comparing the tag value with information stored in each record from a subset of the line cache records, and identifying the record from that subset of records, if any, that is a match record that stores information that matches the tag value, that subset comprising two or more line cache records.

Further aspects, features and advantages of the present technique will become apparent from the following description of the examples, which should be read in conjunction with the accompanying drawings, in which:

Figure 1 illustrates an example of the logical operation of a label lookup operation for a set-associative cache,

Figure 2 schematically illustrates an example of a DRAM-based storage matrix,

Figures 3 and 4 show two alternative approaches for a cache controller to locate target data in a cache implemented using a DRAM,

Figure 5 shows an example in which the DRAM stores both the data and its associated tag information, in which the DRAM supports a tag matching instruction,

Figure 6 shows an example storage circuit that includes a comparator circuit for comparing a tag value to a subset of entries of a line buffer,

Figure 7 shows various examples of label and data layout within a row of storage cells,

Figure 8 shows an example of a data storage circuit that includes multiple arrays of storage cells,

Figure 9 shows an example where pairs of tag data are split between different arrays,

Figure 10 is a flow chart illustrating a method of processing an activation command,

Figure 11 is a flow chart illustrating a method of processing a tag matching command;

Figure 12 illustrates the use of error detection codes,

Figure 13 is a flow chart illustrating a method of processing a write command to a previous hit, and

Figure 14 is a flow chart illustrating a method of processing a tag pool command.

The storage circuit may have a line cache to temporarily store information from an active line of storage locations during reads or writes to that line. The row buffer contains a number of records, with each record to store the information from a storage location in a corresponding column of the active row. The storage circuit may have a comparison circuit, which is responsive to a tag match instruction that specifies a tag value to compare the tag value with information stored in each record from a subset of line cache records (with the subset including at least two records), and to determine the record from that subset of records, if any, that is a matching record that stores information that matches the tag value. This allows tag lookup operations to be performed faster since multiple tags can be compared directly in the line buffer and it is not necessary to individually read each record into an external circuit to compare against the tag value. This means that the storage circuit can be used more efficiently as a set-associative cache, since the tags of a set of locations can be looked up in response to a single tag-match command, and a number of separate read operations are not required. This is useful since storage technologies using a line cache can be more area efficient for a given amount of storage capacity than alternative storage technologies, resulting in a more efficient use of this type of circuit. storage as a set associative cache may allow larger caches to be produced at lower production costs.

The comparison circuit may perform a plurality of parallel comparisons, each comparison comparing the tag value with the information in a corresponding record from that subset of line cache records. Therefore, multi-record tag lookups can be faster compared to sequentially reading each tag individually to compare against a target tag value.

In some cases, the comparison circuit may compare the tag value associated with the tag matching instruction to the entire contents of each record in the subset of line buffer records. When the storage circuit is used as a cache, the storage locations can be allocated in pairs, each pair including a storage location for a cached data value and another storage location for storing a corresponding label value, so that the subset of records of the line cache can be those records which store tag values rather than data values. In general, the value of a tag can specify part of the address of the data value at the other location in the pair. However, the tag value could also specify other control information to control caching of the data, e.g. relevance status information, which indicates whether the corresponding data value is clean or dirty, or eviction control information to control the eviction of the data from the cache (eg, a least recently used (LRU) enumeration, or other information to track recent stored data access plans). Therefore, in some implementations the comparison circuit may compare the tag value determined by the tag matching instruction with only a portion of the information stored in each record of the subset of line cache records.

A configuration storage element may be provided to store configuration information identifying the line cache entries which belong to the subset of entries to be compared using the comparison circuit. This allows the physical storage capacity of the storage circuit to be allocated to various storage configurations of tag values and data values when the storage circuit is used as a cache, since the comparator circuit can determine from the configuration storage element the cache entries lines which are intended to store tag values rather than data values. For example, the configuration information could specify control information such as the desired associativity, the size of the cache line, or the size of the tag used by the cache, from which the subset of entries by the comparison circuit could be determined. . Alternatively, the configuration information can explicitly specify which line cache entries are to be compared to the tag value (eg, using a bitmap with each bit specifying whether a corresponding entry should be considered part of the subset records or not).

When a record from said subset of records is identified as a match record in response to the tag match command (a “hit condition”), a read or write operation may be triggered to read or write information corresponding to a destination storage location that it is chosen depending on which row cache record is the matching record. For example, the destination storage location may be the associated storage location that stores the data value associated with the tag value stored in the storage location for which the hit was detected. For a read operation, the information read from the destination storage location may be returned in response to the match tags command.

In some cases, the destination storage location may be another storage location on the same matrix row as the storage location corresponding to the line cache match entry in question. With this approach, each tag-data pair can be assigned within the same line of the storage circuit, which can make control of the read operation less complex.

Alternatively, the destination storage location could be on a different line than the storage location for which the match was detected. Although it is possible to provide a storage circuit that includes a single array of storage locations, in many cases two or more arrays of storage locations may be provided, each array including a matrix of storage locations arranged in rows and columns, a row buffer, and a comparator circuit as discussed above. In practice, after a read from an active line in an array, it can often be faster to read information from a different array than to perform another read on the same line of the first array. Therefore, to improve performance in a multi-array implementation, when a data-label pair is allocated to the storage circuit, it can be useful to write the data value to a storage location in an array and the corresponding label value to a storage location in a different array. Therefore, when processing a tag match instruction, when the success condition is determined, the target storage location for which the read handle is enabled may be in a different array than the storage location corresponding to the line cache match entry.

In some examples, when the hit condition is determined, the comparison circuit may store a pointer to the line buffer record that is said matching record in a predetermined storage element. The storage circuit may have a control circuit which supports a write command to a previous hit, which activates a write operation to write information to the storage location associated with the line buffer write specified by said predetermined element storage. Often after reading a data value from a cache it may be desirable to update part of the corresponding tag value (eg, updating the relevance status or eviction control information mentioned above). Therefore, by writing the identification record to the predefined storage element, the subsequent tag write can be performed without a cache controller or other external controller that requires knowing the exact location of the tag or repeating the tag lookup operation.

Alternatively, the update of state information, such as relevance state information or cache replacement policy information, could occur in response to the tag matching command itself. Accordingly, when a hit condition exists and a match record is identified in response to the tag match command, the control circuitry may update the status information to a storage location selected based on which line buffer record is the match record. Typically the storage location chosen may be the storage matrix location corresponding to the matching record itself, but it could also correspond to another record of the same active row. By updating the cache state information on a cache hit in response to the tag match command, the need to issue a single write command from the cache controller to the storage circuit to update the state information is avoided.

In response to the match tag command, if no record from the subset of line cache records stores information matching the tag value (a “failure condition”), the comparator may return a failure indication. This can be output to a cache checker as an indication that the required data is not currently being cached. In some cases the failure indicator could be a visible signal indicating whether there was a hit or miss. However, this could require providing an additional output pin to communicate the pass/fail signal to other circuits.

However, in some cases the data stored in the storage circuit can be protected from errors by using error detection codes. Some types of error detection codes could simply make it possible to detect errors (such as bit reversals caused by a particle impact or other simple event perturbation), but not to correct them. E.g. parity codes or checksums could be used to determine when a bit reversal has occurred, but not which bit is the incorrect bit. Alternatively, the error detection codes could be error correcting codes which also make it possible to correct an error by providing some redundant information which can be used to determine the correct data value. Error correcting codes could be convolution codes or gradient codes for example. The error detection code could be a separate value from the corresponding data value, or alternatively the data could be coded to provide a single data value from which it is possible to determine both the original data value and the information determine whether an error exists.

In examples using error detection codes, when a failure is determined in response to the tag matching command, the failure indication may include a predetermined pattern of information associated with an invalid error detection code. Although the invalid error detection code would normally indicate that an error has occurred in the corresponding data, a cache controller or other circuitry that receives the failure indication can be configured so that when the data has the predetermined pattern, then the invalid detection code errors should be interpreted not as an indication of an error, but as an indication that the tag lookup indicated a failure. This makes it possible to signal the failure condition using the data channel used for the read operations, thus avoiding the need to provide an additional pin to communicate a separate pass/fail signal.

The storage circuit control circuit may also be responsive to a read-victim-write command to read data from a line-cache victim-write selected as a function of cache-overwrite policy information stored in the line-buffer and to invalidate data from a storage location associated with that victim record. On a cache miss, if there are no invalid locations in the relevant set, then it may be necessary to find a victim tier to evict the data and replace it with the new data that will be transferred from memory. Determining which record to select as a victim record may require reading cache replacement policy information from the relevant set (eg, information indicating which record was used the oldest). Instead of reading the replacement policy information into a cache controller and then having the cache controller determine which record should be selected as the victim record and issuing a subsequent read, the control circuit may support parsing the information replacement policy locally within the storage circuit itself. For example, if the replacement policy is pseudo-least-recently-used, the write-victim instruction can control the control circuit within the storage circuit to traverse a binary tree and find the least-recently-used element, return the tier data so that it can be rewritten to memory and the tier cancelled. In this way it is possible to save at least one instruction since both the read (and processing) of the replacement policy information and the read of the victim data can be performed within the storage circuit in response to a single instruction.

After an eviction from the victim record storage location, a subsequent write command may be issued to the storage circuitry to write the data transferred from memory to the victim record storage location. To speed up the handling of this record, in response to the read command of the victim record, the control circuit may store a pointer to the line cache record that was the victim record in a predetermined storage element. A write to previous hit command, as discussed above, can then be used to write the replacement data to the storage location associated with the write identified by the predefined storage element. This avoids the need to review the replacement policy information again when writing the replacement data to the victim record.

It is also possible to implement a tag pool instruction, which will trigger the control circuitry to perform a read operation to read information from each record from that subset of line cache records. Therefore, in response to the gather tags command, tag information from the active line can be gathered and returned faster than if separate read operations were required to read each tag in succession. This can be useful, for example, to allow a cache controller to make better replacement decisions when allocating new data to a cache. Since the data channel between the storage circuit and the cache controller may not be as wide as the total size of all tag information on the active line, multiple data transfers can be performed in succession in response to the tag pool command to transfer the tag information in the cache controller in large segments.

The technique discussed above can be used for storage circuits based on any memory technology that uses a line cache. However, it can be particularly useful for storage circuits based on DRAM technology memories. DRAM is a relatively surface-efficient memory technology, but it is typically relatively slow to access, making it difficult to effectively use as a set associative cache. Therefore, DRAM has traditionally been used for main memory, but not for cache memory. By providing the comparator circuit described above, DRAM becomes more attractive for use as a cache memory, allowing larger caches to be implemented with smaller circuit area and thus lower manufacturing costs compared to alternatives such as SRAM.

An arrangement (eg, a data processing system) may include the storage circuitry described above and a cache controller for controlling accesses to cache data stored in the storage circuitry. In response to a cache access request that specifies a destination address, either the cache controller or the storage circuitry may issue the match tag instruction that specifies a tag value determined as a function of said destination address. In some cases, the generation of the tag match instruction may occur in the cache controller, and the cache controller may then pass a line address and the tag value to the storage circuitry, which may compare the tag value with the subset of line cache records, trigger a read/write on the matching record, and then return the required data or a failure indication for a read or write acknowledgment signal for a record. Alternatively, the cache controller could issue a memory address to the storage circuit, which could then decode the line address and tag value internally and then process the tag matching instruction in a similar way to that discussed above . When a hit is detected in response to the match tag instruction, the storage circuitry may output to the cache controller at least one of the following: a data value corresponding to a destination storage location other than the storage location associated with the match record, and information to determine the storage location of the storage circuit which is the destination storage location. In practice, performance can be faster if the storage circuitry outputs the data value itself so that there is no need for a subsequent read instruction in addition to the tag matching instruction.

Figure 1 shows the logical operation of a tag lookup operation for a set-associative cache 2. Cache 2 has a number of cache entries 4 each comprising a tag-data pair, each pair comprising a data value 6 and a label value 8 which specifies a portion of the memory address corresponding to the data value and optionally specifies other information such as relevance status information or eviction control information. The cache entries 4 are logically organized into sets of 10, each containing a certain number of cache entries (e.g. Figure 1 shows a 4-way cache set associative 2 so that each set 10 contains four entries cache 4). The group of positions in corresponding positions within each set is referred to as a “direction” 12, e.g. direction 0 includes the first cache entry 4 of each set of 10, direction 1 includes the second cache entry 4 of each set of 10, etc.

When a read/write operation is performed, the memory address 14 of the required is provided, a pointer portion 16 of the destination address (or a hash of the pointer portion 16) is used to select the set 10 for access, a tag portion 18 of the destination address 14 is compared with the tag values 8 in each of the entries 4 of the tagged set 10. A hit signal is asserted for the direction 12 that includes the match tag, while the corresponding data value 6 can be read from the cache entry 4 in the match direction 12 of the indexed set 10. An offset portion 20 of the destination address may specify the position of the required data within the returned data value 6.

Although Figure 1 shows the logical operation desired for a set-associative cache, in the physical hardware implementation, this may be implemented in various ways depending on the memory technology used for the cache. It is relatively common to use SRAM for a cache since SRAM can be accessed quickly compared to alternative memories such as DRAM. However, increasingly there is a demand for relatively large caches, and SRAM can be relatively intensive in terms of circuit area, making it expensive to build larger SRAM caches.

DRAM can provide a cheaper technology for use in larger storage structures. Figure 2 shows an example of a DRAM memory based storage circuit 30. The storage circuit 30 includes a matrix 32 of storage locations 34 arranged in rows and columns, a row buffer 36, a column multiplexer 38 and a row decoder 40. For the DRAM memory, each storage location 34 includes a group of bit cells, each bit cell including a capacitor that can be selectively charged or discharged to represent a 1 or a 0 corresponding to one bit of the total value represented by corresponding storage location 34. Accesses to DRAM memory 30 are performed in two stages. First, an enable command is issued specifying a line address 42. The line decoder 40 activates the corresponding line 46 to transfer the information stored in each of the corresponding line's storage locations 34 to the line buffer 36. Second, a column address 44 accompanies the actual read/write command, which controls the column multiplexer 38 to select a record of the line buffer 36 corresponding to the specified column within the active line and either outputs the information read from that record as read data or updates the data in this record based on the record data supplied with the write command. For a write, as long as the connection between the sense amplifiers shaping the line buffer 36 and the corresponding DRAM storage location 34 can remain open, the writes to the line buffer 36 can be transmitted back to the corresponding storage location 34. Multiple Operations read/write operations can occur within the same active line, before the line is closed using a preload instruction, which closes the connection between line cache 36 and the active line 46, ensures that the active line's storage locations 46 have been updated to reflect any entries in line buffer 36 and again sets line buffer 36 ready for another line to be selected as the active line.

DRAM 30 is often used as main memory in a processing system since it can provide relatively large storage capacity at low cost, while for main memory the relatively small access delay of DRAM 30 is not a problem since main memory is intended for mass backup storage, rather than storing data for quick access.

However, increasingly there is a demand for larger caches than would be economical to build from SRAM. DRAM would be attractive to save money, but there are some performance issues associated with using DRAM as a cache.

In particular, for caches to provide an appropriate balance between performance and throughput, it is often desirable to implement the cache as a set-associative cache, as illustrated in Figure 1. However, the lookup implementation tags for set-associative caches can be difficult using DRAM-based storage technologies. Figures 3 and 4 illustrate two alternative ways in which DRAM could be used to implement a set-associative cache.

As shown in Figure 3, one approach is to store the data value from each tag-data pair in the DRAM memory 30, but to store the tag values in a separate SRAM-based storage structure 50. Therefore, when accessing the cache to obtain data for a given address, a cache controller 52 outputs the tag portion of the address to SRAM tag storage 50 which compares the tag value with the stored tags of the corresponding set, determines whether there is a hit or a miss, and on success provides a column address in DRAM memory 30 which identifies the DRAM destination location corresponding to the match tag. At the same time the line address of the destination DRAM location is provided by the cache controller 52. Therefore, the DRAM memory 30 can use the line address and the column address to determine the required storage location and return the required data. For writes, a similar search of SRAM tag storage 50 may be performed, but in this case the write data provided by cache controller 52 is written to the storage location identified by the row address and column address. One problem with this approach is that the SRAM memory used to store tags 50 is expensive in terms of circuit area, which is especially a problem as the cache capacity grows.

Figure 4 shows an alternative approach in which both the data and the tag of each tag-data pair are stored in the DRAM 30 itself, obviating any need for additional SRAM-based tag storage and thus reducing circuit area. However, with this approach, tag lookups require the cache controller to choose a particular way to lookup the set, issue a read operation that specifies the row and column address of the DRAM storage location that stores the tag value of that address, reading the tag value and comparing the read tag with the tag portion of the destination address to determine whether there is a hit or miss. If there is a hit, a subsequent read access can then determine the row/column address of the corresponding data value for the match tag, and then the data is returned. If there is a failure, it is necessary to issue another read access to access the next tag in the set menu pointer, when for the next tag the same process as for the first tag comparison is repeated, and so on until either a matching tag is determined or to specify a failure for all tags in the indexed set. It is possible to provide direction prediction 54 to track previously accessed directions and increase the probability of selecting the correct direction the first time. However, the direction prediction hardware 54 incurs a cost in area and power consumption, and even if the direction prediction is relatively accurate, there are still times when multiple sequential tag read accesses are required, performed in sequence, followed by the subsequent data read access. which is also a cascade of the previous tag search. Therefore, each cache access requires the serial processing of at least two instructions (a tag read instruction and a read/write instruction), but sometimes three or more instructions may be required if the first tag read does not match the destination address tag. Therefore, this approach lags in terms of performance.

Figure 5 shows a data processing device 60 which includes a cache controller 62 and a DRAM storage circuit 64 to address these issues. As in Figure 4, both the data and its associated tags are stored in DRAM 64, thereby eliminating the need for separate tag storage based on SRAM 50 as in Figure 3, saving circuit area. However, DRAM 64 supports a tag matching instruction which allows multiple tags within DRAM 64 to be compared in parallel in response to a single instruction issued by cache controller 62, improving performance. For a read operation, the cache controller 62 issues a tag match read command and provides the DRAM memory 64 with a line address identifying the required line of DRAM locations and a tag value to compare with the tags stored in that line of locations. DRAM. Both the line address and the tag value may be generated by the cache controller 62 as a function of the destination memory address of the data to be accessed. In response to the tag match read command, DRAM 64 compares the tag value with each of the tag values stored within the row identified by the row address, returns the data value corresponding to a match tag on a hit, and returns a failure indication in the event of a failure. For a write operation, cache controller 62 outputs the line address, tag value and write data, and again DRAM 64 compares the tag value with each of the tag values stored in the corresponding line, writes the data value to a location corresponding to the matching label on success, assigns the data value and its corresponding label to a new storage location on failure, and returns a write acknowledgment to the cache controller 62. This approach provides a better balance between performance and footprint circuit and is particularly useful for larger caches where SRAM is not cost-effective.

Figure 6 shows the DRAM 64 of Figure 5 in greater detail. As in Figure 2, DRAM memory 64 includes a matrix of 32 storage locations 34, line buffer 36, column multiplexer 38, and line decoder 40. Line buffer 36 includes a number of records 68, with each record 68 corresponding to a column of the storage matrix 32. Tag mismatch read and write commands, an enable command, and a precharge command are supported in the same manner as described for Figure 2. When an enable command is received, the information stored in each of storage locations 34 of the line identified by line address 42 are transferred to line buffer 36, with each record 68 being updated with the information from storage location 34 in a corresponding column of enabled line 46. As indicated in Figure 6, some of locations on active line 46 may store tag values (T) while other locations store values data (D), so line buffer 68 includes a mixture of tags and data.

The DRAM memory 64 has a comparator circuit 70 for comparing the contents of the entries 68 of the line buffer 36 with a tag value 72 provided by the cache controller 62 with a tag match instruction. The tag match command could be a tag match read command which triggers a tag lookup and an associated read, or a tag match write command which triggers a tag lookup and an associated write. Control circuitry 74 is provided to receive commands provided by cache controller 62 and activate appropriate control paths in DRAM module hardware 64 to control row decoder 40, column multiplexer 38, and comparators 70 to perform the required manipulations.

Accordingly, when a tag match command is received, the control circuit 74 checks the comparators 70 to compare the received tag value 72 with the tags stored in a subset of entries 68 of the line buffer. Comparisons between the received tag 72 and the tags stored in the line buffer 36 are performed in parallel, resulting in faster performance than the case illustrated in Figure 4 where the tags are compared one after the other. If any of the tags in the line buffer 36 matches the received tag 72, a hit signal is asserted which can trigger a read operation to read the corresponding data value from the DRAM array 32 and return the data to the cache controller 62. For example, in the arrangement shown in Figure 6, tags and data values are alternated in pairs and thus when a hit is determined for a given tag, the corresponding data value can be read from the adjacent entry of line buffer 36. If none of the compared tags match the specified tag value 72 , a failure indication is returned to the cache controller 62 .

As shown in Figure 6, the column address of the line cache entry 68 that matches the tag value 72 may be stored in a storage element 75 within the DRAM unit 64. This allows the match tag to be updated by a subsequent command ("write to previous hit" as discussed below for Figure 13) without the need to repeat the tag lookup or to inform the cache controller 62 about the identified tag. Although shown separately in Figure 6, the storage elements 75 identifying the previous hit tag could also be part of the line buffer 36 itself.

A configuration storage element 76 may be provided to control the particular entries of the line cache 36 which are compared to the tag value 72 by the comparators 70. This makes it possible to configure the same DRAM hardware in different allocations depending on the desired cache configuration . As shown in parts A) and B) of Figure 7, labels and data values can be arranged in various patterns on a given line, with example A) showing the labels and data alternating as in Figure 6, while the example B) shows all T tags stored contiguously followed by the corresponding D data values. Thus, the configuration data 76 could identify the records that store the tags and control the comparators 70 to compare these records with the tag value 72.

Different users may also wish to use cache lines of different sizes or different associativity. Therefore, the sizes of data and tag values could vary between different use cases. For example, a 128MB DRAM segment could be configured as a set-associative 16-way cache with 512-byte cache lines and 40-bit labels, while if there is 1 byte of status information then this might require 516 bytes per pair data tag and thus approximately 8 kB DRAM lines. However, the same segment could be used as a set associative 8-way cache with 1024 byte cache lines by reconfiguring the configuration data 76 so that the comparators 70 identify a different set of elements. For example, as cache lines become longer, a line may include fewer tags as shown in portion C) of Figure 7 and therefore comparators 70 may not need to compare the tag value 72 with as many line cache entries. 36.

In many cases, it may be more convenient to configure the cache so that a line of storage locations corresponds to a set 10 of the associative structure to a cache set. However, this is not necessary, and in some cases a line of the DRAM matrix 32 may correspond to multiple sets of 10. In this case, a portion of the address line 42 may be used to select the portion of the line cache 36 that is compared with the tag value 72, while the configuration data 76 may specify the particular records to be considered as the subset of records within the line buffer portion 36 (alternatively, a portion of the line address specifying the set could choose between to multiple sets of configuration data 76 which identify the various subsets of line cache entries 68 to be compared for each set within the same DRAM line).

As shown in Figure 8, often the DRAM unit 64 may include more than one storage array locations, with each array comprising a separate instance of a DRAM matrix of 32 storage locations arranged in rows and columns, a row buffer 36, a column multiplexer 38, a line decoder 40 and comparator circuit 70 as discussed above. The control circuit 74 for processing the incoming commands and activating the appropriate signal paths can be shared between the arrays. Accordingly, a portion of address line 42 received by cache controller 62 may select which array is accessed. Although Figure 8 shows an example with two DRAM arrays, there may often be more arrays, e.g. 4, 8 or 16 arrays. Therefore, each array can support tag matching using the comparator circuit described above.

In a multi-array DRAM implementation, it may be useful to switch the data values and tag values of a number of tag-data pairs between corresponding lines of separate arrays as shown in Figure 9. For example, for the tag-data pair T0-D0, the tag value TO may be stored in line x of array 0, but the corresponding data value of D0 is stored in line x of array 1. The tag data pair T1-D1 is similarly divided between the arrays, but this time tag T1 is stored in array 1, while D1 data is stored in array 0. This is useful because when a line is active and cached in the sense amplifiers of the line buffer 36, reads and writes to the line buffer 36 can temporarily disturb the values that they are latched in the 36-line buffer, so balancing takes some time read the contents of line 36 cache before another read/write access to the same line can be made. This means that after performing a read/write on a row of an array, it may be faster to perform the next read/write access to a different array than to perform the next access to the same array as the first read/write operation. By splitting the tag and data values of the same tag-data pair, better performance is possible because the read/write operation for data value D0, for example, can be performed faster in array 1 after tag TO is accessed in array 0. Therefore, when a read/write is triggered after a hit, the target storage location may actually be on a different array.

With the approach shown in Figure 9, the tag search can be divided into two stages, one to search for the tags in the indexed set which are stored in buffer lines 36-0 of array 0, and another to search for the tags in the indexed set which are stored in buffer lines 36-1 of array 1. If the match tag is specified in array 0, the second stage is not required and instead a read/write to the register in which it is stored the data for the identification tag. If no tag is matched in array 0, a second stage of tag matching is performed using array 1, while if a hit is determined there then a further read/write operation is triggered for the corresponding data in array 0. If tag value 72 also fails on array 1 then the failure indicator is returned. Therefore, the timing of the read data returned may depend on whether the tag value 72 matches the first array or the second array (alternatively, the read data returned at the earlier timing could be cached in DRAM so that the data is are provided to the cache controller 62 at the same timing regardless of which array the tag hits). However, regardless of whether one or two label lookup operations are required, performance can be improved by allowing a second array to initiate a subsequent operation after an operation performed on a first array without first having to wait for balancing time of the first array.

Figure 10 shows a method of processing an activation command. In step 100, the DRAM memory 64 receives an enable command specifying a row address 42 from the cache controller 62. In step 102 the control circuit 72 controls the row decoder 40 to select the row of storage locations 34 corresponding to address line 42 as the active line 46, while checking the line buffer 36 to retrieve the information stored in the corresponding storage locations of the active line 46.

Figure 11 shows a method of processing a tag matching command. In step 110, the DRAM memory 64 receives a tag matching instruction that specifies a line address 42 and a tag value 72 from the cache controller 62. The tag matching instruction may also specify a parameter that specifies whether it is an instruction read or write. In step 112, the control circuit 74 controls the comparison circuit 70 to compare the tag value 72 with each record from a subset of records 68 of the line buffer 36 (with the subset of records being determined by the configuration store 76). In step 114 the control circuit determines whether the comparator circuit 70 has detected a pass or a miss. In the event of a hit, in step 116 the control circuit 74 initiates a read or write operation that targets the storage cell associated with the tag record (which could be in the same array or a different array as discussed above); while the data read or write acknowledgment is returned to cache controller 62. In step 118 the column address of the row cache entry 68 containing the identified tag is stored in storage element 75 for use by subsequent tag update operations. If a failure is detected in step 114 , then a failure indication is returned to cache controller 62 in step 120 .

The failure indicator returned in step 120 could be a dedicated hit/miss signal set to the opposite value of that emitted on a hit. However, this may require an additional output port for the DRAM module, which can be prevented by signaling failures using the data channel instead (as long as the data channel is in any case unused when a cache failure occurs memory). In general, any predefined bit pattern could be used to represent a cache miss, where that pattern is one that could not be derived for normal data accesses. One way to accomplish this is to exploit error detection codes that may be provided to protect against errors. As shown in Figure 12, each data value 130 stored in DRAM 64 may be associated with an error detection code 132. After reading the data from DRAM 64, the data value 130 may be hashed using of a check function 134 and the resulting hash may be compared to the error detection code 132. If the hash matches the error detection code 132, then the data is correctly identified, while a failure to match may indicate that an error has occurred. If the error detection code is an error correcting code, then the error may also be corrected, e.g. based on redundant information included in the error correction code. Accordingly, a failure indication may be signaled to cache controller 62 by returning a predetermined bit pattern as data value 130 along with an invalid error detection code 132 that does not match the result of applying control function 134 to its predetermined bit pattern data value 130. After receiving the data in response to a cache lookup, the cache controller 62 can then determine from the combination of the predetermined data bit pattern 130 and the invalid error detection code 132 that a cache miss has occurred, without requiring a separate signal path to signal cache misses.

Figure 13 shows a method of processing a previous hit write command to update the tag value for which a hit occurred in response to a previous tag matching command. In step 140, the DRAM module 64 receives the write to previous hit command which specifies the updated tag value to write to the DRAM memory. In step 142, control circuit 74 reads the column address from storage element 75, which was previously stored in step 118 of Figure 11. In step 144, control circuit 74 enables a write operation to register 68 of line buffer 36 which is determined by the column address read in step 144, to write the updated tag value to that record. This will also trigger a corresponding update of the corresponding storage cell in the DRAM matrix 32. Thus, by storing the column address of the most recently identified tag in a storage element 75, a subsequent tag update can be performed more efficiently. This is useful for caches since in some implementations each cache read or write operation may require the corresponding tag to be updated (especially in caches that use a legacy or other victim selection algorithm to select the write to evict after allocating new data based on past cache access history).

Alternatively, instead of storing the column address in a hit in step 118, in Figure 11 the control circuit could instead update the cache state information in a storage location selected based on the entry that was the cache match entry lines. Therefore, as an access hits a cache, the DRAM controller 74 also updates the information corresponding to the set used for the replacement policy. The replacement policy bits would be on the same DRAM line as the data itself, which would be present in line 36 buffer. For example, if the replacement policy is pseudo-LRU (least recently used), in an access that hits, the corresponding bits of the binary tree are updated to reflect that the accessed element is in the most recently used (MRU). Therefore, for this feature, the DRAM cache has some additional logic near the DRAM line cache which, according to the replacement policy, updates the replacement information in case of a cache miss.

An advantage of the approach shown in Figures 11 and 13 is that the control circuit 74 in the DRAM storage does not need to know the replacement policy being used, and can support two or more different policies which could be selected by the cache controller. . On the other hand, by directly updating the cache state information in response to the tag match command, fewer commands are required in the event of a cache miss.

In the event of a cache miss when there are no backup invalid entries, a victim tier in the relevant pool is selected, and the data is ejected from that tier and replaced with the new tier that is fetched from the memory below. To speed up such evictions and replacements, a special type of read command (victim read command) can be provided which activates and reads the data based on the replacement policy information. For example, if the replacement policy is pseudo-LRU, the read victim command traverses the binary tree to find the LRU element. The command returns the gradient data and cancels the gradient. An indication of the write-victim can be stored in the previous hit column location 75, while a write command to the read-previous location (victim) writes the new-insertion tier (in the same way as for the write command to the previous hit of Figure 13) . Therefore, with this approach, the DRAM controller 74 has an additional instruction which can read a column (label and data) of the line buffer 36, where the read column is selected according to the replacement policy information read from the relative subset of positions of the active line as stored in line buffer 36.

Figure 14 shows a method of processing a tag pool command to make all tags available to the cache controller 62 from a given set of storage locations, which can be useful because it enables the cache controller 62 to make more reliable decisions about cache allocation and eviction for example. In step 150 the DRAM module 64 receives the tag pool command (it is not necessary to specify a line address since the command can naturally target the active line that was activated in response to a previous enable command). In response to the tag collection command, in step 152 the control circuit 72 controls the column multiplexer 38 to read all the tags stored in the subset of records identified by the configuration data 76 and returns the read tags to the cache controller 62. If the combined size of the read tags is greater than the data channel width, then the tags can be pushed to the cache controller 62 in multiple transports and then assembled in the cache controller 62. The cache controller 62 can then use the read tags to perform cache management operations.

Although the example discussed above relates to the DRAM memory-based storage circuit 64, it will be appreciated that the same technique can be used for any form of memory technology for which a line cache 36 is used to temporarily store information from the locations storage in an active line 46.

In this application, the words “configured for …” are used to mean that an element of an arrangement has a configuration capable of performing the specified operation. In this context, a “configuration” means an arrangement or way of interconnecting hardware or software. For example, the device may have dedicated hardware that provides the specified operation, or a processor or other processing device may be programmed to perform the function. The term “configured for” does not imply that the component of the device must is changed in any way to provide the specified handling.

Although exemplary embodiments of the invention have been described herein in detail with reference to the accompanying drawings, it is to be understood that the invention is not limited to these particular embodiments and that various changes and modifications may be made therein by those skilled in the art without departing from from the object and spirit of the invention as defined by the appended claims.

Claims (22)

1. A storage circuit comprising: a matrix of storage locations arranged in rows and columns, a row buffer which includes a plurality of entries, each for storing information from a storage location to a corresponding column of an active row of the matrix, and a comparison circuit responsive to a tag match command that specifies a tag value for comparing the tag value with information stored in each record from a subset of line cache records and determining which record from that subset of records if exists some, which is a match record that stores information that matches the tag value, that subset comprising two or more line cache records. 2. The storage circuit of claim 1, wherein the comparison circuit is configured to perform a plurality of comparisons in parallel, each comparison comparing the tag value with the information in a corresponding record from said subset of line cache records . 3. The storage circuit according to any one of claims 1 and 2, which includes a configuration storage element for storing configuration information identifying the records from the plurality of line cache records that are within said subset of records. 4. The storage circuit according to any preceding claim, which includes a control circuit configured, in response to a hit condition when a record from said subset of records is identified as said match record in response to the tag match command, to activate a read or write operation to read or write information stored in a destination storage location selected depending on which line cache record is the matching record. 5.         The storage circuit according to claim 4, wherein said destination storage location is still a storage location on the same line of the matrix as the storage location corresponding to said line cache match entry. 6. The storage circuit according to claim 4, comprising a plurality of arrays, each array including said matrix, said line buffer and said comparator circuit, wherein said destination storage location is a storage location in a different array than the array containing the storage location corresponding to said line cache match entry. 7. The storage circuit according to any one of claims 1 to 4, comprising a plurality of arrays, each array comprising said matrix, said line buffer and said comparator circuit, which includes a control circuit responsive to a write command to write a data value to a storage location in one of the plurality of arrays and to write a corresponding tag value to a storage location in another of the plurality of arrays. 8. The storage circuit according to any one of the preceding claims, wherein in response to a hit condition when a record from said subset of records is determined to be said match record in response to the tag match command, the comparison circuit is configured to store of an indication of which line cache record is said matching record in a predefined storage element. 9. The storage circuit according to claim 8, which includes a control circuit responsive to a write command in a previous hit to activate a write operation to write information to the storage location associated with the line buffer write specified by the storage preset in question. 10. The storage circuit according to any one of the preceding claims, comprising a control circuit responsive to a hit condition when a record from said subset of records is determined to be said match record in response to the tag match command, for updating of state information to a storage location selected based on which line cache record is the match record in question. 11. The storage circuit according to any one of the preceding claims, wherein in response to the tag matching command, the comparison circuit is configured to return a failure indication when no record from said subset of line cache records stores the matching information with the tag price. 12. The storage circuit according to claim 11, wherein each storage location is configured to store information associated with an error detection code, and said failure indication includes a predetermined pattern of information associated with an invalid DTC. 13. The storage circuit according to any one of the preceding claims, which includes a control circuit responsive to a read victim command to read data from a victim write of the line cache which is selected according to the cache replacement policy information which cached rows and invalidating the data from a storage location associated with that victim record. 14. The storage circuit of claim 13, wherein in response to said victim read command, the control circuit is configured to store an indication of which line cache record is said victim record in a predetermined storage element . 15. The storage circuit according to claim 14, which includes a control circuit responsive to a write command on a previous hit to activate a write operation to write information to the storage location associated with the line buffer write specified by the storage preset in question. 16.       The storage circuit according to any one of the preceding claims, which includes a control circuit responsive to a tag collection command to activate a read operation to read information from each record from said subset of line cache records. 17. The storage circuit according to any one of the preceding claims, wherein the storage locations comprise DRAM storage locations. 18.       A provision which includes: the storage circuit according to any of the preceding claims, and a cache controller to control accesses to cache data stored in the storage circuit. 19. The apparatus of claim 18, wherein in response to a cache access request specifying a destination address, either the cache controller or the storage circuitry is configured to enable said tag matching instruction specifying a value tag specified as a function of said destination address. 20. The apparatus according to claim 19, wherein in response to a hit condition when a record from said subset of records is determined to be said match record in response to the tag match command, the storage circuit being configured to output to said cache controller of at least one of the following: of a data value corresponding to a destination storage location other than the storage location associated with the identification record, and information to determine which storage circuit storage location is said destination storage location. 21. A storage circuit comprising: a matrix of information storage media arranged in rows and columns, means for temporarily storing information from an active row of the matrix, the temporary storage means comprising a plurality of records, each for storing information from a storage medium in a corresponding column of an active row of the matrix, and means for comparing, in response to a tag matching command that identifies a tag value, the tag value with information stored in each record from a subset of records of the cache media and identifying the record from that subset of records, if any , which is a match record that stores information that matches the tag value, that subset comprising two or more cache media records. 22. A method of accessing information from a storage circuit which takes micrometers of storage locations arranged in rows and columns, by the method of storing multiple entries from storage locations in the active row of the matrix into a string buffer that holds a plurality of records, with each entry storing information from a storage location in a corresponding column of the active row ^and In response to a tag match input that specifies a tag value, comparing the tag with information stored in each record from the temporary queue record set and determining which entry is said subset of records, if any, is a matching record that stores information matching a tag value with said subset including two or more line cache records.