GR20170200042U - Retention data rocessing via cache memory - Google Patents

Abstract

A data processing system 2 incorporates a first exclusive cache memory 8, 10 and a second exclusive cache memory 14. A snoop filter 18 located together with the second exclusive cache memory on one side of the communication interface 12 serves to track entries within the first exclusive cache memory. The snoop filter includes retention data storage circuitry to store retention data for controlling retention of cache entries within the second exclusive cache memory. Retention data transfer circuitry 20 serves to transfer the retention data to and from the retention data storage circuitry within the snoop filter and the second cache memory as the cache entries concerned are transferred between the second exclusive cache memory and the first exclusive cache memory.

Description

MANAGING RETENTION DATA THROUGH CACHE

This disclosure relates to the field of data processing systems. More particularly, the present disclosure relates to data processing systems that incorporate a cache and use retention data associated with cache entries to control the retention of cache entries within the cache.

It is known to provide data processing systems with cache hierarchies to improve the speed and efficiency of data processing. Within such cache hierarchies it is known, for example, to provide individual, dedicated small caches close to a processor core with one or more larger shared caches at a level further away from the processor cores and which are shared between processor cores. Within such cache hierarchies, it is possible to store a single cache entry within the small low-level caches close to the processor cores and/or within the larger, higher-level caches further away from and shared among the processor cores processor. To maintain agreement between different copies of a cache entry which may be stored in different parts of the cache hierarchy and in a main memory, it is known to provide cache agreement mechanisms including one or more lookup filters, which have the ability to indicate which cache entries are stored in which parts of a cache hierarchy or memory system.

At least some embodiments of the present disclosure provide a provision for processing data, which includes:

a first cache,

a second cache, said first cache communicating with said second cache via a communication interface;

a search filter co-located with said second cache on one side of said communication interface and serving to track cache entries stored in said first cache on another side of said communication interface, with said search filter including a retention data storage circuit for storing retention data for checking retention of cache entries within at least said second cache, and

hold data transfer circuit

for transferring hold data for a cache entry from said second cache to said hold data storage circuit when said cache entry is transferred from said

due second cache to said first cache, and

for transferring said hold data for said cache entry from said hold data storage circuit to said second cache when said cache entry is transferred from said first cache to said second cache .

At least some embodiments of the present disclosure provide a provision for processing data, which includes:

first cache media for storing cache entries,

second cache means for storing cache entries, said first cache means communicating with said second cache means via a communication interface;

probe filter means for performing cache probe operations and located together with said second cache means on one side of said communication interface and serving to trace cache entries stored in said first cache means to another side of said communication interface, said probe filter means including retention data storage means for storing retention data for checking retention of cache entries within at least said second cache means, and

retention data carriers

for transferring hold data for a cache entry from said second cache media to said first cache media when said cache entry is transferred from said second cache media to said first cache media, and for transferring said retention data for said cache entry from said retention data storage media to said second cache media when said cache entry is transferred from said first cache media to said second cache media memory.

At least some embodiments of the present disclosure provide a data processing method comprising:

storing cache entries within the first cache;

storing cache entries within the second cache;

communicating between said first cache and said second memory via a communication interface;

performing cache lookup operations with a lookup filter co-located with said second cache on one side of said communication interface and serving to trace cache entries stored in said first cache on one side of said communication interface, said probe filter including a retention data storage circuit for storing retention data for controlling retention of cache entries within at least said second cache, and

transferring hold data for a cache entry from said second cache to said hold data storage circuit when said cache entry is transferred from said second cache to said first cache, and

transferring said hold data for said cache entry from said hold data storage circuit to said second cache when said cache entry is transferred from said first cache to said second cache.

Exemplary embodiments will now be described, by way of example only, with reference to the accompanying drawings in which:

Figure 1 schematically illustrates a data processing system that includes a cache hierarchy,

Figure 2 is a flowchart schematically illustrating the handling when a cache entry is transferred from a second dedicated cache to a first dedicated cache;

Figure 3 is a flowchart schematically illustrating the processing when a cache entry is transferred from the first dedicated cache to the second dedicated cache;

Figure 4 is a block diagram schematically illustrating the definition of a hold value associated with a cache, and

Figure 5 schematically illustrates a further example implementation of a data processing system including a cache hierarchy.

Figure 1 schematically illustrates a data processing system 2 comprising a plurality of processor cores 4, 6 each of which has an associated first dedicated cache 8, 10. The first dedicated caches 8, 10 communicate via a communication interface 12, such as, for example, an agreement interface using a conformal memory access protocol (eg using a conformal architecture protocol), with a second dedicated cache 14, which in the present example embodiment is shared by the processor cores 4, 6 and the first dedicated caches 8, 10. A main memory 16 supplies data both to the second dedicated cache 14 and, via a bypass path, directly to any of the first dedicated caches 8, 10 when they perform a data load of a cache entry that is not within the second exclusive cache memory 14 (a miss within the second dedicated cache 14). It will be appreciated that in other example implementations, the first exclusive caches 8, 10 and the second exclusive cache 14 need not be exclusive and may instead be non-exclusive or pseudo-exclusive.

In the example embodiment of Figure 1, the first dedicated caches 8, 10 and the second dedicated cache 14 operate in a dedicated manner whereby a given cache entry is stored within one, but not both, of either the second dedicated cache 14 or one of the first dedicated caches 8, 10. It may be that a cache entry is shared and stored in both dedicated caches 8, 10, but will not be simultaneously stored in the second dedicated cache 14. Similarly, when a cache entry is stored within the second exclusive cache 14, it will not be stored within any of the first exclusive caches 8, 10. It will be appreciated that other modes of operation of cache hierarchies are possible, such as inclusive modes mode or the partially exclusive modes of operation. The present techniques can be applied to a wide range of different types of cache hierarchies and are not limited in application to cache hierarchies that operate in a strictly exclusive manner.

A probe filter 18 is connected to the second dedicated cache 14 on the same side of the communication interface 12 as the second dedicated cache 14. The probe filter 18 serves to trace the cache entries stored within the first dedicated caches 8, 10, so that when a memory access is to be made, it is possible to perform a check using the probe filter 14 whether a cache entry is stored within any of the first dedicated caches 8, 10 without the need to send a probe request over the communication interface 12 in these first dedicated caches 8, 10. The search filter 18 includes different types of data storage including tag data storage circuits, hold data storage circuits, and agreement data storage circuits.

The tag data storage circuit stores tag data indicative of the memory addresses of the corresponding cache entries stored within the first dedicated caches 8, 10. The agreement data storage circuit stores agreement data for tracking the agreement status of the entries stored within the first of exclusive caches 8, 10, such as whether a cache entry within a particular first exclusive cache 8, 10 is stored in a modified, exclusive, shared, or invalid state (eg, according to MESI agreement protocols). The search filter 18 further includes a retention data storage circuit that stores the retention data for controlling the retention of cache entries within at least the second dedicated cache memory 14. Since the retention data and agreement data are associated with particular cache entries, the tag data may be used to indicate the particular cache entry involved, and thus hold data and match data are stored within the lookup filter 18 for each tag data entry corresponding to a cache entry.

As illustrated in Figure 1, each cache entry within the second dedicated cache 14 incorporates hold data associated with that cache entry. This hold data within the second exclusive cache 14 is used by an eviction circuit 22 to control the selection of a candidate cache entry when a cache entry must be evicted from the second exclusive cache 14 to make room for a new entry cache to be stored in the second dedicated cache 14. The retention data can take a number of different forms, such as tracking data on how recently a cache entry was accessed, e.g. by using an eviction algorithm such as an eviction algorithm previously used. Another example of a form of hold data may be data indicative of whether a given cache entry has been loaded from the second dedicated cache 14 into one of the first dedicated caches 8, 10. When one of the processor cores 4, 6, requests to load data contained within a cache entry (cache line) that has not previously been moved from main memory 16, the cache entry involved bypasses storage within the second dedicated cache 14 and is loaded directly into the first exclusive cache 8, 10 which requested it. The hold data associated with this cache entry is set to indicate that it has not undergone a load from the second dedicated cache 14 to one of the first exclusive caches 8, 10. The hold data for this cache entry which have been loaded directly into one of the first dedicated caches 8, 10 are stored within the data hold circuit 18. The entry within the search filter 18 for the cache entry involved includes a tag indicative of the memory address for that cache entry ( and which allows recognition of the cache entry) as well as hold data and agreement data. The hold data for the cache entries within the first dedicated caches 8, 10 is stored within the hold data storage circuit of the search filter 18 on the same side of the communication interface 12 as the second dedicated cache 14 and is not transferred through the communication interface 12 to the first exclusive caches 8, 10 and are not stored in them either. This saves storage space within the first dedicated caches 8 , 10 and reduces the communication overhead and complexity of the communication interface 12 itself since it is no longer responsible for transferring the hold data to and from the first dedicated caches 8 , 10 .

When a cache entry is evicted from one of the first exclusive caches 8, 10 (using their own eviction mechanisms and eviction algorithms), it is returned to the second exclusive cache 14. If the cache entry involved was previously loaded directly from main memory 16 to the first dedicated cache 8, 10 in which it was needed, on its return to the second dedicated cache its hold data will still indicate that it has not yet been loaded from the second dedicated cache 14 into one of the first exclusive caches 8, 10. Then, if prior to evicting this cache entry from the second exclusive cache 14, a further load of data into this cache entry by one of the processor cores 4, 6 takes place, then the involved cache entry will be reloaded into the appropriate one of the first exclusive caches 8, 10 from second exclusive cache 14 and not from main memory 16. When such a further load occurs, the hold data for that cache entry is marked to indicate that the cache entry involved has undergone a load from the second exclusive cache memory 14 in one of the first dedicated caches 8, 10.

It has been found that there is a correlation between the utility of holding a cache entry within the second exclusive cache 14 and whether or not that cache entry has previously been subjected to a load from the second exclusive cache 14 to any of the first exclusive caches memories 8, 10.

If a cache entry is loaded directly from main memory 16 into one of the first dedicated caches 8, 10, pushed to the second dedicated cache 14, and then not loaded again from this second dedicated cache 14 into one of the first exclusive caches 8, 10, then it is likely to be of little potential utility to hold that cache entry within the second exclusive cache 14. Conversely, a cache entry that is evicted from one of the first exclusive caches 8 , 10 to the second exclusive cache 14 and then loaded again from the second exclusive cache 14 into one of the first exclusive caches 8, 10 is likely to have a high probability of reuse and thus likely to be worth holding ( its non-eviction) within the second exclusive cache 14. The eviction circuit 22 therefore uses the of the retention data indicative of whether or not a cache entry has been loaded from the second exclusive cache 14 into one of the first exclusive caches 8, 10 in determining which cache entry should be selected as candidate cache entry to evict from the second dedicated cache 14 when more space is required within the second dedicated cache 14 to accommodate the cache entries that are most likely to be reused.

The hold data transfer circuit 20 is associated with the second dedicated cache 14 and the search filter 18 and serves to transfer the transfer data for a cache entry to the hold data storage circuit of the search filter 18 when that cache entry is transferred from the second exclusive cache 14 in one of the first exclusive caches 8, 10. When the cache entry is returned from the first exclusive cache 8, 10 by building this cache entry in the second exclusive cache 14, then the data transfer circuit retention circuit serves to return the retention data associated with this cache entry to the second dedicated cache 14 where it is stored in association with the cache entry 14. The retention data transfer circuit 20 is responsible for transferring the retention data to and from the data storage circuit retention within search filter 18 as the corresponding cache entries are transferred via communication interface 12 to and from an appropriate one of the first dedicated caches 8, 10. When a cache entry is loaded directly from main memory 16 via the bypass path to one of the first dedicated caches 8, 10, a hold value for that cache entry is set at that time and stored by the hold data transfer circuit in the associated entry within the lookup filter for the cache entry loaded in appropriate from the first exclusive caches 8, 10. In this case the hold data is not transferred from the second exclusive cache 14, but is set directly within the hold data storage circuit of the search filter 18. When this cache entry is pushed from the first dedicated cache 8, 10 in which it is held to the second dedicated cache 14 , then the hold data transfer circuit 20 transfers its hold data to the write within the second dedicated cache 14 .

Figure 2 is a flow diagram schematically illustrating the process of transferring a cache entry from the second dedicated cache 14 to one of the first dedicated caches 8, 10. At step 24 processing waits until a cache entry is available for transfer from the second exclusive cache 14 to the first exclusive cache 8, 10. This condition is satisfied when there is a successful cache read within the second exclusive cache 14 following an unsuccessful cache read within the appropriate of the first exclusive caches 8, 10. When the need to perform a transfer is determined in step 24, processing proceeds to step 26 in which the hold data value for the cache entry to be transferred is read from the second dedicated cache 14. Step 28 writes then the value of the hold data read in step 26 in the store circuit of holding data within lookup filter 18 and is associated with the tag value held by lookup filter 18 which must track the presence of the cache entry within the first dedicated cache 8, 10 to which it is to be transferred. Step 30 writes the cache write via communication interface 12 to the first dedicated cache 8, 10. Step 32 invalidates the cache write within the second dedicated cache 14 according to the exclusive mode of this example embodiment.

Figure 3 is a flow diagram schematically illustrating the process of transferring a cache entry from one of the first dedicated caches 8, 10 to the second dedicated cache 14. Step 34 waits until there is a cache entry to transfer from one of the first exclusive caches 8, 10 to the second exclusive cache 14. The requirement to transfer such a record may result from an eviction from the first exclusive cache 8, 10, such as that resulting from the use of a mechanism and eviction policy within the first dedicated cache 8, 10 which can take a number of different forms, such as least reasonably used (LRU), round robin, random, etc. When specified a request to perform a transfer in step 34, processing continues to step 36 in which the hold value for the log to be transferred cache line is read from the hold value storage circuitry within probe filter 18 using the tag value associated with the cache entry to be transferred to determine the appropriate hold data value within probe filter 18. Step 38 writes the record to be transferred cache entry via communication interface 12 from the first exclusive cache memory 8, 10 to the second exclusive cache memory 14. The cache entry may have been modified when it was stored in the first exclusive cache memory 8, 10. Step 40 writes the value hold read in step 36 in the cache write within the second dedicated cache 14. Step 42 serves to invalidate the cache write in the first dedicated cache 8, 10 in accordance with the exclusive mode of operation of the example embodiment described above. It will be appreciated that the exclusive mode of operation is not necessary and other exemplary embodiments may operate partially exclusive or inclusive.

Figure 4 is a flow chart schematically illustrating the definition of a hold data value. Processing waits in step 44 until there is a request to load a cache entry into one of the first exclusive caches 8, 10. Such a request may arise due to an unsuccessful cache read within one of the first exclusive caches 8, 10. 10. When a load is required, processing continues to step 46 where a lookup is performed within the second dedicated cache 14 to determine whether or not the cache entry involved exists within the second dedicated cache 14. If there is a successful read in the second exclusive cache 14, then processing continues to step 48 in which the hold value for the cache entry involved is set to indicate relative immunity to subsequent evictions from the second exclusive cache 14. This does not mean that the cache entry involved memory cannot be pushed out of the second exclusive cache 14, but that it is less likely to be selected for eviction by eviction circuit 22 compared to a cache entry marked as relatively vulnerable to evictions. Step 50 then loads the cache line from the second dedicated cache 14 into the first dedicated cache 8, 10 in which the read failure occurred. At the same time, the hold data (value) for the cache line involved is loaded into the associated record for the cache line within the lookup filter 18.

If it is determined in step 46 that there has been a failed read in the second dedicated cache 14, then step 52 serves to set the hold value for the cache line to be loaded to indicate a relative vulnerability to evictions (see previous topic). Step 54 then loads the cache line from main memory 16 and stores the hold value (hold data) in the associated record for the involved cache record within lookup filter 18 .

Figure 5 schematically illustrates an additional exemplary embodiment of a data processing system 56 incorporating the present techniques. In this example embodiment, there are multiple second dedicated caches 58, 60. Each of these second dedicated caches 58, 60 has associated search filters 62, 64, associated eviction circuitry 66, 68, and associated hold data transfer circuitry 70, 72. The second dedicated caches 58, 60 communicate via a communication interface 74 with the first dedicated caches 76, 78. In this example embodiment there is a single first dedicated cache 76, 78 associated with each of the second dedicated caches memories 58, 60. The lookup filter circuit 62, 64 serves to track entries within the first dedicated cache 76, 78 that are associated with the second dedicated cache 58, 60 with which it is connected. The search filters 62, 64 include hold data storage circuits for storing the hold data relative to the cache entries held in the associated first dedicated caches 76, 78 of their respective second dedicated caches 58, 60. The data transfer circuit hold 70, 72 serves to transfer the hold data between the second dedicated cache 58, 60 and the search filter 62, 64 as the corresponding cache entry is transferred via the communication interface 74 to and from the first dedicated cache 76, 78.

Claims (10)

1. Arrangement for data processing which includes: a first cache, a second cache, said first cache communicating with said second cache via a communication interface; a search filter co-located with said second cache on one side of said communication interface and serving to track cache entries stored in said first cache on another side of said communication interface, with said search filter including a retention data storage circuit for storing retention data for controlling retention of cache entries within at least said second cache, and hold data transfer circuit for transferring hold data for a cache entry from said second cache to said hold data storage circuit when said cache entry is transferred from said due second cache to said first cache, and for transferring said hold data for said cache entry from said hold data storage circuit to said second cache when said cache entry is transferred from said first cache to said second cache. 2. An arrangement as claimed in claim 1, wherein said search filter includes a tag data storage circuit for storing a plurality of data tags indicative of the memory addresses of the corresponding ones of said cache entries stored within said first cache memory and said retention data for corresponding said cache entries stored within said first cache and associated with corresponding data tags. 3. An arrangement as claimed in any of claims 1 and 2, comprising evicting circuitry for evicting cache entries from said second cache, wherein said evicting circuit selects a candidate cache entry to evict from said said second cache dependent on said retention data for said cache entries stored in said second cache. 4. An arrangement as claimed in any one of claims 1, 2 and 3, wherein said search filter includes agreement data storage circuitry for storing agreement data for tracking the agreement status of said cache entries stored in said due first cache. 5. An arrangement as claimed in any of the preceding claims, wherein said retention data is indicative of whether a cache entry has been loaded from said second cache into said first cache. 6. An arrangement as claimed in any of the preceding claims, wherein when a given cache entry is loaded from a main memory into said first cache bypassing storage in said second cache, said hold data value for said given cache entry is defined within said hold data storage circuit. 7. An arrangement as claimed in any of the preceding claims, comprising a cache hierarchy comprising said second cache and a plurality of first caches, wherein said search filter tracks cache entries stored in said a plurality of first caches, and said retention data storage circuit stores the retention data for the cache entries stored within said plurality of first caches. 8. An arrangement as claimed in any of the preceding claims, wherein said first cache is a first dedicated cache. 9.         An arrangement as claimed in any of the preceding claims, wherein said second cache is a second dedicated cache. 10. Provision for data processing which includes: first cache media for storing cache records, second cache means for storing cache entries, said first cache means communicating with said second cache means via a communication interface; probe filter means for performing cache probe operations and located together with said second cache means on one side of said communication interface and serving to track cache entries stored in said first cache means on another side of said communication interface, said probe filter means including retention data storage means for storing retention data for checking retention of cache entries within at least said second cache means, and retention data carriers for transferring retention data for a cache entry from said second cache media to said retention data storage media when said cache entry is transferred from said second cache media to said first cache media, and for transferring said retention data for said cache entry from said retention data storage media to said second cache media when said cache entry is transferred from said first cache media to said second cache media memory.