GB9820430D0 - Apparatus for a computer system - Google Patents
Apparatus for a computer systemInfo
- Publication number
- GB9820430D0 GB9820430D0 GBGB9820430.8A GB9820430A GB9820430D0 GB 9820430 D0 GB9820430 D0 GB 9820430D0 GB 9820430 A GB9820430 A GB 9820430A GB 9820430 D0 GB9820430 D0 GB 9820430D0
- Authority
- GB
- United Kingdom
- Prior art keywords
- computer system
- computer
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Withdrawn
Links
Classifications
-
- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F13/00—Interconnection of, or transfer of information or other signals between, memories, input/output devices or central processing units
- G06F13/38—Information transfer, e.g. on bus
- G06F13/40—Bus structure
- G06F13/4004—Coupling between buses
-
- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F13/00—Interconnection of, or transfer of information or other signals between, memories, input/output devices or central processing units
- G06F13/38—Information transfer, e.g. on bus
- G06F13/40—Bus structure
- G06F13/4004—Coupling between buses
- G06F13/4027—Coupling between buses using bus bridges
- G06F13/4031—Coupling between buses using bus bridges with arbitration
Landscapes
- Engineering & Computer Science (AREA)
- General Engineering & Computer Science (AREA)
- Theoretical Computer Science (AREA)
- Computer Hardware Design (AREA)
- Physics & Mathematics (AREA)
- General Physics & Mathematics (AREA)
- Bus Control (AREA)
Priority Applications (10)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
GB9820430A GB2341772A (en) | 1998-09-18 | 1998-09-18 | Primary and secondary bus architecture |
AU58777/99A AU5877799A (en) | 1998-09-18 | 1999-09-16 | Apparatus for use in a computer system |
US09/787,353 US7054969B1 (en) | 1998-09-18 | 1999-09-16 | Apparatus for use in a computer system |
PCT/GB1999/003089 WO2000017759A2 (en) | 1998-09-18 | 1999-09-16 | Computer system comprising latency tolerant and intolerant modules |
EP99946365A EP1112539A2 (en) | 1998-09-18 | 1999-09-16 | Computer system comprising latency tolerant and intolerant modules |
US10/827,360 US7346722B2 (en) | 1998-09-18 | 2004-04-20 | Apparatus for use in a computer systems |
US10/827,361 US20040199706A1 (en) | 1998-09-18 | 2004-04-20 | Apparatus for use in a computer systems |
US10/827,356 US20040199704A1 (en) | 1998-09-18 | 2004-04-20 | Apparatus for use in a computer system |
US10/827,359 US20040199692A1 (en) | 1998-09-18 | 2004-04-20 | Apparatus for use in a computer systems |
US11/225,695 US20060010279A1 (en) | 1998-09-18 | 2005-09-13 | Apparatus for use in a computer systems |
Applications Claiming Priority (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
GB9820430A GB2341772A (en) | 1998-09-18 | 1998-09-18 | Primary and secondary bus architecture |
Publications (2)
Publication Number | Publication Date |
---|---|
GB9820430D0 true GB9820430D0 (en) | 1998-11-11 |
GB2341772A GB2341772A (en) | 2000-03-22 |
Family
ID=10839139
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
GB9820430A Withdrawn GB2341772A (en) | 1998-09-18 | 1998-09-18 | Primary and secondary bus architecture |
Country Status (1)
Country | Link |
---|---|
GB (1) | GB2341772A (en) |
Families Citing this family (1)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
WO2007029053A1 (en) | 2005-09-09 | 2007-03-15 | Freescale Semiconductor, Inc. | Interconnect and a method for designing an interconnect |
Family Cites Families (6)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US4979097A (en) * | 1987-09-04 | 1990-12-18 | Digital Equipment Corporation | Method and apparatus for interconnecting busses in a multibus computer system |
CA2007737C (en) * | 1989-02-24 | 1998-04-28 | Paul Samuel Gallo | Data transfer operations between two asynchronous buses |
US5369748A (en) * | 1991-08-23 | 1994-11-29 | Nexgen Microsystems | Bus arbitration in a dual-bus architecture where one bus has relatively high latency |
SG47015A1 (en) * | 1994-02-24 | 1998-03-20 | Intel Corp | Apparatus and method for prefetching data to load buffers in a bridge between two buses in a computer |
US5619661A (en) * | 1995-06-05 | 1997-04-08 | Vlsi Technology, Inc. | Dynamic arbitration system and method |
US5754807A (en) * | 1995-11-20 | 1998-05-19 | Advanced Micro Devices, Inc. | Computer system including a multimedia bus which utilizes a separate local expansion bus for addressing and control cycles |
-
1998
- 1998-09-18 GB GB9820430A patent/GB2341772A/en not_active Withdrawn
Also Published As
Publication number | Publication date |
---|---|
GB2341772A (en) | 2000-03-22 |
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Legal Events
Date | Code | Title | Description |
---|---|---|---|
WAP | Application withdrawn, taken to be withdrawn or refused ** after publication under section 16(1) |