GB9801943D0 - High density erasable programmable logic device architecture using multipllexer interconnections - Google Patents

High density erasable programmable logic device architecture using multipllexer interconnections

Info

Publication number
GB9801943D0
GB9801943D0 GBGB9801943.3A GB9801943A GB9801943D0 GB 9801943 D0 GB9801943 D0 GB 9801943D0 GB 9801943 A GB9801943 A GB 9801943A GB 9801943 D0 GB9801943 D0 GB 9801943D0
Authority
GB
United Kingdom
Prior art keywords
multipllexer
interconnections
high density
programmable logic
logic device
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Granted
Application number
GBGB9801943.3A
Other versions
GB2318668B (en
GB2318668A (en
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Altera Corp
Original Assignee
Altera Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Priority claimed from US08/123,435 external-priority patent/US5384499A/en
Application filed by Altera Corp filed Critical Altera Corp
Publication of GB9801943D0 publication Critical patent/GB9801943D0/en
Publication of GB2318668A publication Critical patent/GB2318668A/en
Application granted granted Critical
Publication of GB2318668B publication Critical patent/GB2318668B/en
Anticipated expiration legal-status Critical
Expired - Fee Related legal-status Critical Current

Links

Classifications

    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03K—PULSE TECHNIQUE
    • H03K19/00—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits
    • H03K19/02—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits using specified components
    • H03K19/173—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits using specified components using elementary logic circuits as components
    • H03K19/177—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits using specified components using elementary logic circuits as components arranged in matrix form
    • H03K19/17748—Structural details of configuration resources
    • H03K19/1776—Structural details of configuration resources for memories
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03K—PULSE TECHNIQUE
    • H03K19/00—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits
    • H03K19/02—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits using specified components
    • H03K19/173—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits using specified components using elementary logic circuits as components
    • H03K19/1733—Controllable logic circuits
    • H03K19/1737—Controllable logic circuits using multiplexers
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03K—PULSE TECHNIQUE
    • H03K19/00—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits
    • H03K19/02—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits using specified components
    • H03K19/173—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits using specified components using elementary logic circuits as components
    • H03K19/177—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits using specified components using elementary logic circuits as components arranged in matrix form
    • H03K19/17724—Structural details of logic blocks
    • H03K19/17728—Reconfigurable logic blocks, e.g. lookup tables
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03K—PULSE TECHNIQUE
    • H03K19/00—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits
    • H03K19/02—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits using specified components
    • H03K19/173—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits using specified components using elementary logic circuits as components
    • H03K19/177—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits using specified components using elementary logic circuits as components arranged in matrix form
    • H03K19/17736—Structural details of routing resources
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03K—PULSE TECHNIQUE
    • H03K19/00—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits
    • H03K19/02—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits using specified components
    • H03K19/173—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits using specified components using elementary logic circuits as components
    • H03K19/177—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits using specified components using elementary logic circuits as components arranged in matrix form
    • H03K19/1778—Structural details for adapting physical parameters
    • H03K19/17784—Structural details for adapting physical parameters for supply voltage
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03K—PULSE TECHNIQUE
    • H03K19/00—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits
    • H03K19/02—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits using specified components
    • H03K19/173—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits using specified components using elementary logic circuits as components
    • H03K19/177—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits using specified components using elementary logic circuits as components arranged in matrix form
    • H03K19/1778—Structural details for adapting physical parameters
    • H03K19/17792—Structural details for adapting physical parameters for operating speed

Landscapes

  • Physics & Mathematics (AREA)
  • Mathematical Physics (AREA)
  • Engineering & Computer Science (AREA)
  • Computer Hardware Design (AREA)
  • Computing Systems (AREA)
  • General Engineering & Computer Science (AREA)
  • Computer Networks & Wireless Communication (AREA)
  • Logic Circuits (AREA)
GB9801943A 1993-09-17 1994-09-13 High-density erasable programmable logic device architecture using multiplexer interconnections Expired - Fee Related GB2318668B (en)

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
US08/123,435 US5384499A (en) 1991-04-25 1993-09-17 High-density erasable programmable logic device architecture using multiplexer interconnections
GB9418435A GB2281993B (en) 1993-09-17 1994-09-13 High-density erasable programmable logic device architecture using multiplexer interconnections

Publications (3)

Publication Number Publication Date
GB9801943D0 true GB9801943D0 (en) 1998-03-25
GB2318668A GB2318668A (en) 1998-04-29
GB2318668B GB2318668B (en) 1998-06-17

Family

ID=26305619

Family Applications (2)

Application Number Title Priority Date Filing Date
GB9801942A Expired - Fee Related GB2318667B (en) 1993-09-17 1994-09-13 High-density erasable programmable logic device architecture using multiplexer interconnections
GB9801943A Expired - Fee Related GB2318668B (en) 1993-09-17 1994-09-13 High-density erasable programmable logic device architecture using multiplexer interconnections

Family Applications Before (1)

Application Number Title Priority Date Filing Date
GB9801942A Expired - Fee Related GB2318667B (en) 1993-09-17 1994-09-13 High-density erasable programmable logic device architecture using multiplexer interconnections

Country Status (1)

Country Link
GB (2) GB2318667B (en)

Family Cites Families (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5241224A (en) * 1991-04-25 1993-08-31 Altera Corporation High-density erasable programmable logic device architecture using multiplexer interconnections

Also Published As

Publication number Publication date
GB2318667B (en) 1998-06-17
GB2318667A (en) 1998-04-29
GB2318668B (en) 1998-06-17
GB2318668A (en) 1998-04-29
GB9801942D0 (en) 1998-03-25

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Legal Events

Date Code Title Description
PCNP Patent ceased through non-payment of renewal fee

Effective date: 20120913