GB9623297D0 - Electronic circuit and method of operation for monitoring signals and generating interrupts - Google Patents
Electronic circuit and method of operation for monitoring signals and generating interruptsInfo
- Publication number
- GB9623297D0 GB9623297D0 GB9623297A GB9623297A GB9623297D0 GB 9623297 D0 GB9623297 D0 GB 9623297D0 GB 9623297 A GB9623297 A GB 9623297A GB 9623297 A GB9623297 A GB 9623297A GB 9623297 D0 GB9623297 D0 GB 9623297D0
- Authority
- GB
- United Kingdom
- Prior art keywords
- comparator
- electronic circuit
- array
- input ports
- monitoring signals
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Withdrawn
Links
Classifications
-
- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F11/00—Error detection; Error correction; Monitoring
- G06F11/30—Monitoring
- G06F11/34—Recording or statistical evaluation of computer activity, e.g. of down time, of input/output operation ; Recording or statistical evaluation of user activity, e.g. usability assessment
- G06F11/3466—Performance evaluation by tracing or monitoring
- G06F11/349—Performance evaluation by tracing or monitoring for interfaces, buses
Landscapes
- Engineering & Computer Science (AREA)
- General Engineering & Computer Science (AREA)
- Theoretical Computer Science (AREA)
- Computer Hardware Design (AREA)
- Quality & Reliability (AREA)
- Physics & Mathematics (AREA)
- General Physics & Mathematics (AREA)
- Bus Control (AREA)
Abstract
The electronic circuit 10 for monitoring logic lines 12 and generating an interrupt signal comprises a latch 14 having a first array of input ports 18 which receive input signals, from the logic lines 12, and a first array of output ports 20. A comparator 24 has a first set of comparator input ports 26 coupled to the array of output ports 20 of the latch 14 and a second set of comparator input ports 28 coupled to the logic lines 12. The comparator 24 compares first and second comparator input ports and provides an interrupt signal when a difference exists between the inputs. The comparator can be constructed from a cascadable address decoder.
Priority Applications (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
GB9623297A GB2319363A (en) | 1996-11-08 | 1996-11-08 | Monitoring signals and generating interrupts |
Applications Claiming Priority (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
GB9623297A GB2319363A (en) | 1996-11-08 | 1996-11-08 | Monitoring signals and generating interrupts |
Publications (2)
Publication Number | Publication Date |
---|---|
GB9623297D0 true GB9623297D0 (en) | 1997-01-08 |
GB2319363A GB2319363A (en) | 1998-05-20 |
Family
ID=10802656
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
GB9623297A Withdrawn GB2319363A (en) | 1996-11-08 | 1996-11-08 | Monitoring signals and generating interrupts |
Country Status (1)
Country | Link |
---|---|
GB (1) | GB2319363A (en) |
-
1996
- 1996-11-08 GB GB9623297A patent/GB2319363A/en not_active Withdrawn
Also Published As
Publication number | Publication date |
---|---|
GB2319363A (en) | 1998-05-20 |
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Legal Events
Date | Code | Title | Description |
---|---|---|---|
WAP | Application withdrawn, taken to be withdrawn or refused ** after publication under section 16(1) |