GB948453A - Improvements in or relating to logical circuits - Google Patents

Improvements in or relating to logical circuits

Info

Publication number
GB948453A
GB948453A GB1941060A GB1941060A GB948453A GB 948453 A GB948453 A GB 948453A GB 1941060 A GB1941060 A GB 1941060A GB 1941060 A GB1941060 A GB 1941060A GB 948453 A GB948453 A GB 948453A
Authority
GB
United Kingdom
Prior art keywords
input
output
inputs
core
winding
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Expired
Application number
GB1941060A
Inventor
William Lawrence Stephenson
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Philips Components Ltd
Original Assignee
Mullard Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Mullard Ltd filed Critical Mullard Ltd
Priority to GB1941060A priority Critical patent/GB948453A/en
Publication of GB948453A publication Critical patent/GB948453A/en
Expired legal-status Critical Current

Links

Classifications

    • HELECTRICITY
    • H03ELECTRONIC CIRCUITRY
    • H03KPULSE TECHNIQUE
    • H03K19/00Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits
    • H03K19/02Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits using specified components
    • H03K19/08Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits using specified components using semiconductor devices
    • H03K19/082Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits using specified components using semiconductor devices using bipolar transistors
    • HELECTRICITY
    • H03ELECTRONIC CIRCUITRY
    • H03KPULSE TECHNIQUE
    • H03K19/00Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits
    • H03K19/02Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits using specified components
    • H03K19/16Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits using specified components using saturable magnetic devices

Landscapes

  • Engineering & Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • Computer Hardware Design (AREA)
  • Computing Systems (AREA)
  • General Engineering & Computer Science (AREA)
  • Mathematical Physics (AREA)
  • Power Engineering (AREA)
  • Measuring Magnetic Variables (AREA)

Abstract

948,453. Logic circuits employing transistors and remanent magnetic cores. MULLARD Ltd. May 25, 1961 [June 1, 1960], No. 19410/60. Headings H3B and H3T. A logical AND circuit has its inputs A1, A2, Fig. 1, connected through transistors T1, T2 to opposed input windings W1, W2 on a core C of material having a rectangular magnetization characteristic, and an alternating output is induced in a winding W3 only when (a) both inputs are energized simultaneously by respective D.C. signals modulated by A.C. of opposite phase, (b) the two inputs are interlaced D.C. pulses which act in opposite senses in the windings W1 and W2, or (c) one input is a D.C. signal modulated by A.C. and the other a D.C. bias, each input being of sufficient value by itself to saturate the core. The core is unsaturated when an output is produced by coincident input signals, and the conducting transistors are arranged to bottom so as to obtain a substantially constant winding voltage and rate of change of flux. When one input only is energized, on the other hand, the core becomes saturated and the conducting transistor operates at a limited current value. An additional output winding W3<SP>1</SP> may be used to provide an output of opposite phase useful, for example, in cascaded logical circuits. In a modification, Fig. 3; providing the logical OR operation, winding W2 has parallel inputs A2 and A3, and an A.C. output is produced when a D.C. signal modulated by A.C. is applied to either or both inputs A2, A3, the input A1 being continuously biased by D.C. In a further modification, Fig. 4, a rectified feedback path to A2 which includes a smoothing circuit L maintains an output as long as a D.C. signal modulated by A.C. is applied to A1.
GB1941060A 1960-06-01 1960-06-01 Improvements in or relating to logical circuits Expired GB948453A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
GB1941060A GB948453A (en) 1960-06-01 1960-06-01 Improvements in or relating to logical circuits

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
GB1941060A GB948453A (en) 1960-06-01 1960-06-01 Improvements in or relating to logical circuits

Publications (1)

Publication Number Publication Date
GB948453A true GB948453A (en) 1964-02-05

Family

ID=10128900

Family Applications (1)

Application Number Title Priority Date Filing Date
GB1941060A Expired GB948453A (en) 1960-06-01 1960-06-01 Improvements in or relating to logical circuits

Country Status (1)

Country Link
GB (1) GB948453A (en)

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