GB9417688D0 - An electrical circuit comprising a latch - Google Patents

An electrical circuit comprising a latch

Info

Publication number
GB9417688D0
GB9417688D0 GB9417688A GB9417688A GB9417688D0 GB 9417688 D0 GB9417688 D0 GB 9417688D0 GB 9417688 A GB9417688 A GB 9417688A GB 9417688 A GB9417688 A GB 9417688A GB 9417688 D0 GB9417688 D0 GB 9417688D0
Authority
GB
United Kingdom
Prior art keywords
latch
electrical circuit
electrical
circuit
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Withdrawn
Application number
GB9417688A
Other versions
GB2292855A (en
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Texas Instruments Ltd
Original Assignee
Texas Instruments Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Texas Instruments Ltd filed Critical Texas Instruments Ltd
Priority to GB9417688A priority Critical patent/GB2292855A/en
Publication of GB9417688D0 publication Critical patent/GB9417688D0/en
Publication of GB2292855A publication Critical patent/GB2292855A/en
Withdrawn legal-status Critical Current

Links

Classifications

    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03K—PULSE TECHNIQUE
    • H03K3/00—Circuits for generating electric pulses; Monostable, bistable or multistable circuits
    • H03K3/01—Details
    • H03K3/012—Modifications of generator to improve response time or to decrease power consumption
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03K—PULSE TECHNIQUE
    • H03K3/00—Circuits for generating electric pulses; Monostable, bistable or multistable circuits
    • H03K3/02—Generators characterised by the type of circuit or by the means used for producing pulses
    • H03K3/027—Generators characterised by the type of circuit or by the means used for producing pulses by the use of logic circuits, with internal or external positive feedback
    • H03K3/037—Bistable circuits
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03K—PULSE TECHNIQUE
    • H03K3/00—Circuits for generating electric pulses; Monostable, bistable or multistable circuits
    • H03K3/02—Generators characterised by the type of circuit or by the means used for producing pulses
    • H03K3/027—Generators characterised by the type of circuit or by the means used for producing pulses by the use of logic circuits, with internal or external positive feedback
    • H03K3/037—Bistable circuits
    • H03K3/0372—Bistable circuits of the master-slave type
GB9417688A 1994-08-31 1994-08-31 CMOS latch suitable for low voltage operation Withdrawn GB2292855A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
GB9417688A GB2292855A (en) 1994-08-31 1994-08-31 CMOS latch suitable for low voltage operation

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
GB9417688A GB2292855A (en) 1994-08-31 1994-08-31 CMOS latch suitable for low voltage operation

Publications (2)

Publication Number Publication Date
GB9417688D0 true GB9417688D0 (en) 1994-10-19
GB2292855A GB2292855A (en) 1996-03-06

Family

ID=10760745

Family Applications (1)

Application Number Title Priority Date Filing Date
GB9417688A Withdrawn GB2292855A (en) 1994-08-31 1994-08-31 CMOS latch suitable for low voltage operation

Country Status (1)

Country Link
GB (1) GB2292855A (en)

Families Citing this family (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US6456136B1 (en) * 2001-04-13 2002-09-24 Sun Microsystems, Inc. Method and apparatus for latching data within a digital system
US6501315B1 (en) * 2001-12-12 2002-12-31 Xilinx, Inc. High-speed flip-flop operable at very low voltage levels with set and reset capability
DE10250866B4 (en) * 2002-10-31 2009-01-02 Qimonda Ag D flip-flop
JP5176883B2 (en) * 2008-11-07 2013-04-03 富士通株式会社 Latch circuit and control method thereof

Family Cites Families (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
DE3684478D1 (en) * 1986-12-30 1992-04-23 Ibm GENERATION OF LOCKING CELLS FOR GATE MATRIX IN CMOS TECHNOLOGY.
US4939384A (en) * 1988-10-03 1990-07-03 Oki Electric Industry Co., Ltd Flip-flop circuit
JP2540934B2 (en) * 1989-03-09 1996-10-09 三菱電機株式会社 Logic circuit device
JPH0478215A (en) * 1990-07-18 1992-03-12 Sony Corp Master slave type flip-flop circuit

Also Published As

Publication number Publication date
GB2292855A (en) 1996-03-06

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Legal Events

Date Code Title Description
WAP Application withdrawn, taken to be withdrawn or refused ** after publication under section 16(1)