GB9410970D0 - Bit-focussed multiplier - Google Patents

Bit-focussed multiplier

Info

Publication number
GB9410970D0
GB9410970D0 GB9410970A GB9410970A GB9410970D0 GB 9410970 D0 GB9410970 D0 GB 9410970D0 GB 9410970 A GB9410970 A GB 9410970A GB 9410970 A GB9410970 A GB 9410970A GB 9410970 D0 GB9410970 D0 GB 9410970D0
Authority
GB
United Kingdom
Prior art keywords
focussed
multiplier
bit
focussed multiplier
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Withdrawn
Application number
GB9410970A
Other versions
GB2290156A (en
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Individual
Original Assignee
Individual
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Individual filed Critical Individual
Priority to GB9410970A priority Critical patent/GB2290156A/en
Publication of GB9410970D0 publication Critical patent/GB9410970D0/en
Publication of GB2290156A publication Critical patent/GB2290156A/en
Withdrawn legal-status Critical Current

Links

Classifications

    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F7/00—Methods or arrangements for processing data by operating upon the order or content of the data handled
    • G06F7/38—Methods or arrangements for performing computations using exclusively denominational number representation, e.g. using binary, ternary, decimal representation
    • G06F7/48—Methods or arrangements for performing computations using exclusively denominational number representation, e.g. using binary, ternary, decimal representation using non-contact-making devices, e.g. tube, solid state device; using unspecified devices
    • G06F7/52—Multiplying; Dividing
    • G06F7/523—Multiplying only
    • G06F7/53—Multiplying only in parallel-parallel fashion, i.e. both operands being entered in parallel
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F7/00—Methods or arrangements for processing data by operating upon the order or content of the data handled

Landscapes

  • Physics & Mathematics (AREA)
  • Engineering & Computer Science (AREA)
  • General Physics & Mathematics (AREA)
  • Theoretical Computer Science (AREA)
  • Computational Mathematics (AREA)
  • Mathematical Analysis (AREA)
  • Mathematical Optimization (AREA)
  • Pure & Applied Mathematics (AREA)
  • General Engineering & Computer Science (AREA)
  • Computing Systems (AREA)
  • Logic Circuits (AREA)
GB9410970A 1994-06-01 1994-06-01 Bit-focused multiplier Withdrawn GB2290156A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
GB9410970A GB2290156A (en) 1994-06-01 1994-06-01 Bit-focused multiplier

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
GB9410970A GB2290156A (en) 1994-06-01 1994-06-01 Bit-focused multiplier

Publications (2)

Publication Number Publication Date
GB9410970D0 true GB9410970D0 (en) 1994-07-20
GB2290156A GB2290156A (en) 1995-12-13

Family

ID=10756018

Family Applications (1)

Application Number Title Priority Date Filing Date
GB9410970A Withdrawn GB2290156A (en) 1994-06-01 1994-06-01 Bit-focused multiplier

Country Status (1)

Country Link
GB (1) GB2290156A (en)

Family Cites Families (7)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US3900724A (en) * 1974-02-11 1975-08-19 Trw Inc Asynchronous binary multiplier using non-threshold logic
US3914589A (en) * 1974-05-13 1975-10-21 Hughes Aircraft Co Four-by-four bit multiplier module having three stages of logic cells
JPS6022767B2 (en) * 1979-10-01 1985-06-04 株式会社東芝 binary multiplier cell circuit
US4706210A (en) * 1984-12-13 1987-11-10 The Johns Hopkins University Guild array multiplier for binary numbers in two's complement notation
US4768161A (en) * 1986-11-14 1988-08-30 International Business Machines Corporation Digital binary array multipliers using inverting full adders
US4839848A (en) * 1987-09-14 1989-06-13 Unisys Corporation Fast multiplier circuit incorporating parallel arrays of two-bit and three-bit adders
KR920007505B1 (en) * 1989-02-02 1992-09-04 정호선 Multiplier by using neural network

Also Published As

Publication number Publication date
GB2290156A (en) 1995-12-13

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Legal Events

Date Code Title Description
WAP Application withdrawn, taken to be withdrawn or refused ** after publication under section 16(1)