GB9003484D0 - Read/write ordering apparatus and method for a microprocessor - Google Patents

Read/write ordering apparatus and method for a microprocessor

Info

Publication number
GB9003484D0
GB9003484D0 GB909003484A GB9003484A GB9003484D0 GB 9003484 D0 GB9003484 D0 GB 9003484D0 GB 909003484 A GB909003484 A GB 909003484A GB 9003484 A GB9003484 A GB 9003484A GB 9003484 D0 GB9003484 D0 GB 9003484D0
Authority
GB
United Kingdom
Prior art keywords
microprocessor
read
ordering apparatus
write ordering
write
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Granted
Application number
GB909003484A
Other versions
GB2230120A (en
GB2230120B (en
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Intel Corp
Original Assignee
Intel Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Intel Corp filed Critical Intel Corp
Publication of GB9003484D0 publication Critical patent/GB9003484D0/en
Publication of GB2230120A publication Critical patent/GB2230120A/en
Application granted granted Critical
Publication of GB2230120B publication Critical patent/GB2230120B/en
Anticipated expiration legal-status Critical
Expired - Fee Related legal-status Critical Current

Links

Classifications

    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F12/00—Accessing, addressing or allocating within memory systems or architectures
    • G06F12/02—Addressing or allocation; Relocation
    • G06F12/08—Addressing or allocation; Relocation in hierarchically structured memory systems, e.g. virtual memory systems
    • G06F12/0802—Addressing of a memory level in which the access to the desired data or data block requires associative addressing means, e.g. caches
    • G06F12/0893—Caches characterised by their organisation or structure
    • G06F12/0897—Caches characterised by their organisation or structure with two or more cache hierarchy levels

Landscapes

  • Engineering & Computer Science (AREA)
  • Theoretical Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • General Engineering & Computer Science (AREA)
  • General Physics & Mathematics (AREA)
  • Memory System Of A Hierarchy Structure (AREA)
  • Advance Control (AREA)
GB9003484A 1989-04-07 1990-02-15 Read/write ordering apparatus and method for a microprocessor Expired - Fee Related GB2230120B (en)

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
US33493189A 1989-04-07 1989-04-07

Publications (3)

Publication Number Publication Date
GB9003484D0 true GB9003484D0 (en) 1990-04-11
GB2230120A GB2230120A (en) 1990-10-10
GB2230120B GB2230120B (en) 1992-12-02

Family

ID=23309498

Family Applications (1)

Application Number Title Priority Date Filing Date
GB9003484A Expired - Fee Related GB2230120B (en) 1989-04-07 1990-02-15 Read/write ordering apparatus and method for a microprocessor

Country Status (3)

Country Link
JP (1) JPH02293945A (en)
GB (1) GB2230120B (en)
HK (1) HK112894A (en)

Families Citing this family (6)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH077356B2 (en) * 1989-05-19 1995-01-30 株式会社東芝 Pipelined microprocessor
GB2244158B (en) * 1990-04-30 1994-09-07 Sun Microsystems Inc Cache memory arrangement with write buffer pipeline providing for concurrent cache determinations
JPH06168182A (en) * 1992-11-30 1994-06-14 Fujitsu Ltd Information processor
JP3024422B2 (en) * 1993-04-01 2000-03-21 三菱電機株式会社 Programmable controller and method of operating programmable controller
US5642494A (en) * 1994-12-21 1997-06-24 Intel Corporation Cache memory with reduced request-blocking
US8108584B2 (en) 2008-10-15 2012-01-31 Intel Corporation Use of completer knowledge of memory region ordering requirements to modify transaction attributes

Also Published As

Publication number Publication date
GB2230120A (en) 1990-10-10
HK112894A (en) 1994-10-27
JPH02293945A (en) 1990-12-05
GB2230120B (en) 1992-12-02

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Legal Events

Date Code Title Description
PCNP Patent ceased through non-payment of renewal fee

Effective date: 20010215