GB881288A - Programmed arithmetical adder - Google Patents

Abstract

881,288. Digital electric calculating circuits. INTERNATIONAL COMPUTERS & TABULATORS Ltd. Jan. 27, 1960 [Jan. 16, 1959], No. 1656/59. Class 106 (1). An adder for summing two numbers each represented by a serial train of pulses occurring in separate groups, each group representing a digit of the number, comprises an adding element providing an output pulse train representing the sum of two input numbers, and means for applying the sum output pulse train, after a delay, to one input of the adding element, and for concurrently applying to the other input of the adding element a pulse train representing a filler digit when the addition of a filler digit is required. Numbers to be added may be stored in tracks 24a, 11 on a magnetic drum store of the type described in Specification 851,742. Each digit of the numbers is, for example, represented by a serial combination of pulses representing values 1, 2, 4, 8. The two numbers to be added are re-timed so as to be synchronized with one of five clock pulse trains derived from tracks 20a-20e. The re-timing circuit for track 11 comprises AND gate 27 and flip-flop 28, and a similar circuit 32 is provided for track 24a. The setting of flip-flop 34 determines whether the numbers will be added or subtracted. In adding, pulses from track 11 are supplied to one input of element 26 through gates 31, 37, and pulses from track 24a are supplied to the other input of element 26. The sum output of element 26 is supplied over line 48 to a comparison circuit 45 which has as its other input the inverse of a filler digit obtained from track 12. For decimal numbers, the filler digit is 0110 (6) and the inverse of this is 1001 (9). Other filler digits, for example, for pence, shillings and pounds or for tons, hundredweights and quarters may be recorded on track 12 and selected by choice of clock pulse track. Circuit 45 provides an output if the sum output on line 48 is greater than the inverse of the filler digit. OR gate 49 receives the output of circuit 45 and also the carry output of element 26. Thus if the sum output is greater than or equal to the scale of the digit, flip-flop 44 is switched on and opens gate 56 whereby, in the period immediately following the input digit pair, the filler digit is applied to one input of element 26 through gates 40, 56, 37, and concurrently, the sum output of element 26, after passing through delay device 54, e.g. an ultrasonic delay line or a shift register, is applied to the other input of element 26. The corrected sum output is then obtained on line 57 through gate 58. Subtraction is performed by complementary addition; the digit from track 11 being added to the filler digit in complementor 38 and then inverted so that the complement of the input digit is applied to element 26 through gate 37. Specifications 678,427, 738,314 and 738,605 also are referred to.