GB866568A - Improvements in and relating to the protection of electrical power circuits - Google Patents

Improvements in and relating to the protection of electrical power circuits

Info

Publication number
GB866568A
GB866568A GB2831456A GB2831456A GB866568A GB 866568 A GB866568 A GB 866568A GB 2831456 A GB2831456 A GB 2831456A GB 2831456 A GB2831456 A GB 2831456A GB 866568 A GB866568 A GB 866568A
Authority
GB
United Kingdom
Prior art keywords
transistor
circuit
arrangement
emitter
conductive
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Expired
Application number
GB2831456A
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
JACK LEONARD DINELEY
Original Assignee
JACK LEONARD DINELEY
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by JACK LEONARD DINELEY filed Critical JACK LEONARD DINELEY
Priority to GB2831456A priority Critical patent/GB866568A/en
Priority to US682736A priority patent/US2977510A/en
Publication of GB866568A publication Critical patent/GB866568A/en
Expired legal-status Critical Current

Links

Classifications

    • HELECTRICITY
    • H04ELECTRIC COMMUNICATION TECHNIQUE
    • H04MTELEPHONIC COMMUNICATION
    • H04M19/00Current supply arrangements for telephone systems
    • HELECTRICITY
    • H02GENERATION; CONVERSION OR DISTRIBUTION OF ELECTRIC POWER
    • H02HEMERGENCY PROTECTIVE CIRCUIT ARRANGEMENTS
    • H02H3/00Emergency protective circuit arrangements for automatic disconnection directly responsive to an undesired change from normal electric working condition with or without subsequent reconnection ; integrated protection
    • H02H3/08Emergency protective circuit arrangements for automatic disconnection directly responsive to an undesired change from normal electric working condition with or without subsequent reconnection ; integrated protection responsive to excess current
    • H02H3/093Emergency protective circuit arrangements for automatic disconnection directly responsive to an undesired change from normal electric working condition with or without subsequent reconnection ; integrated protection responsive to excess current with timing means

Landscapes

  • Engineering & Computer Science (AREA)
  • Signal Processing (AREA)
  • Relay Circuits (AREA)

Abstract

866,568. Protective cut-out arrangements. ADAMSON, C., and DINELEY, J. L. Sept. 13, 1957 [Sept. 17, 1956; May 3, 1957], Nos. 28314/56 and 14138/57. Class 38 (5). [Also in Group XL (c)] A protective arrangement comprises a transistor 31 having a collector-emitter circuit energized from a D.C. supply source 32 and a base-emitter circuit energized from the protected A.C. circuit 33 through a rectifier 38 and a time delay circuit including a reactive impedance element, e.g. a capacitor 37, and a detector means 40 responsive to current in the collector-emitter circuit for performing a protective operation. In Fig. 2 the time delay circuit is supplied from a current transformer 30 and the detector means is an electromagnetic relay having contacts 40b connected in the circuit of a circuit-breaker trip coil 34a. As the current in the A.C. circuit 33 increases, the negative charge of the capacitor increases to render the transistor 31 more conductive as its base is carried negative with respect to the emitter. When sufficient current flows in the collector-emitter circuit the relay trips the circuit-breaker. This arrangement provides an inverse relationship between operating time and overload current. A voltage transformer or a transactor could be used instead of the current transformer and the detector means may comprise a transistor device, a transductor or an electronic device. The detector means may be connected in the collector circuit as shown, but alternatively it may be connected in the emitter circuit, Fig. 3 (not shown). To prevent the operating characteristic of the arrangement being too dependent upon the detector characteristics, a trigger circuit, including a further transistor 42, may be provided as shown in Fig. 5. In this arrangement the transistor 31 is normally non- conductive and the transistor 42 is conductive so establishing a bias voltage across a resistor 43 which ensures that the transistor 31 is non- conductive. As soon as the voltage applied to the base of the transistor 31 exceeds this bias voltage, the transistor 31 becomes conductive and establishes a relatively large potential drop across the detector with the result that the potential drop across a poteniometer 45 is reduced and transistor 42 becomes less conductive and reduces the bias voltage across resistor 43. Hence the circuit rapidly becomes stable with transistor 31 conducting and a large current flowing through the detector. To avoid hesitation in the final triggering due to the low input impedance of transistor 31 an emitter-follower transistor 46 may be connected between the time delay circuit and the transistor 31. To prevent incorrect operation due to unwanted charging of the capacitor through the transistor 31 a further transistor 48, Fig. 11, may be used as a starting and resetting device. The transistor 48 short-circuits the capacitor 37 until the input signal from the rectifier reaches a desired magnitude. A diode 56 when connected as indicated gives protection against over-voltages, but if connected to a tapping on the resistor 36 is causes the arrangement to have a definite minimum operating time, Fig. 10 (not shown). Fig. 11 also illustrates an arrangement in which instantaneous operation under heavy fault conditions is provided by a transistor 62 which by-passes the time delay circuit and the transistor 31, as shown, or which may by-pass the time delay circuit only, Fig. 15 (not shown). In Fig. 12 (not shown), the capacitor is charged from the D.C. supply under the control of an additional transistor connected to the transformer, this arrangement providing a definite time characteristic. The D.C. supply for the transistors may be derived from the transformer 30, voltage limiting non-linear resistors being provided. Non-linear resistors may also be used to give the protective arrangement " very-inverse " characteristics. The Complete Specification also describes an arrangement in which a constant time increment is added to the normal inverse characteristic to provide a relay arrangement for use on timegraded systems. The first Provisional Specification also refers to a directional relay arrangement.
GB2831456A 1956-09-17 1956-09-17 Improvements in and relating to the protection of electrical power circuits Expired GB866568A (en)

Priority Applications (2)

Application Number Priority Date Filing Date Title
GB2831456A GB866568A (en) 1956-09-17 1956-09-17 Improvements in and relating to the protection of electrical power circuits
US682736A US2977510A (en) 1956-09-17 1957-09-09 Protection of electrical power circuits

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
GB2831456A GB866568A (en) 1956-09-17 1956-09-17 Improvements in and relating to the protection of electrical power circuits

Publications (1)

Publication Number Publication Date
GB866568A true GB866568A (en) 1961-04-26

Family

ID=10273679

Family Applications (1)

Application Number Title Priority Date Filing Date
GB2831456A Expired GB866568A (en) 1956-09-17 1956-09-17 Improvements in and relating to the protection of electrical power circuits

Country Status (1)

Country Link
GB (1) GB866568A (en)

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
FR2164543A1 (en) * 1971-12-23 1973-08-03 Sait

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
FR2164543A1 (en) * 1971-12-23 1973-08-03 Sait

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