GB8515318D0 - Computer system - Google Patents

Computer system

Info

Publication number
GB8515318D0
GB8515318D0 GB858515318A GB8515318A GB8515318D0 GB 8515318 D0 GB8515318 D0 GB 8515318D0 GB 858515318 A GB858515318 A GB 858515318A GB 8515318 A GB8515318 A GB 8515318A GB 8515318 D0 GB8515318 D0 GB 8515318D0
Authority
GB
United Kingdom
Prior art keywords
computer system
computer
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Granted
Application number
GB858515318A
Other versions
GB2162406B (en
GB2162406A (en
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
UK Secretary of State for Defence
Logica UK Ltd
Original Assignee
UK Secretary of State for Defence
Logica UK Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by UK Secretary of State for Defence, Logica UK Ltd filed Critical UK Secretary of State for Defence
Publication of GB8515318D0 publication Critical patent/GB8515318D0/en
Publication of GB2162406A publication Critical patent/GB2162406A/en
Application granted granted Critical
Publication of GB2162406B publication Critical patent/GB2162406B/en
Expired legal-status Critical Current

Links

Classifications

    • GPHYSICS
    • G06COMPUTING; CALCULATING OR COUNTING
    • G06FELECTRIC DIGITAL DATA PROCESSING
    • G06F15/00Digital computers in general; Data processing equipment in general
    • G06F15/16Combinations of two or more digital computers each having at least an arithmetic unit, a program unit and a register, e.g. for a simultaneous processing of several programs
    • G06F15/163Interprocessor communication
    • G06F15/173Interprocessor communication using an interconnection network, e.g. matrix, shuffle, pyramid, star, snowflake
    • G06F15/17337Direct connection machines, e.g. completely connected computers, point to point communication networks
    • GPHYSICS
    • G06COMPUTING; CALCULATING OR COUNTING
    • G06FELECTRIC DIGITAL DATA PROCESSING
    • G06F1/00Details not covered by groups G06F3/00 - G06F13/00 and G06F21/00
    • G06F1/04Generating or distributing clock signals or signals derived directly therefrom
    • G06F1/08Clock generators with changeable or programmable clock frequency
    • GPHYSICS
    • G06COMPUTING; CALCULATING OR COUNTING
    • G06FELECTRIC DIGITAL DATA PROCESSING
    • G06F12/00Accessing, addressing or allocating within memory systems or architectures
    • G06F12/02Addressing or allocation; Relocation
    • G06F12/0223User address space allocation, e.g. contiguous or non contiguous base addressing
    • G06F12/0292User address space allocation, e.g. contiguous or non contiguous base addressing using tables or multilevel address translation means
    • GPHYSICS
    • G06COMPUTING; CALCULATING OR COUNTING
    • G06FELECTRIC DIGITAL DATA PROCESSING
    • G06F13/00Interconnection of, or transfer of information or other signals between, memories, input/output devices or central processing units
    • G06F13/10Program control for peripheral devices
    • G06F13/12Program control for peripheral devices using hardware independent of the central processor, e.g. channel or peripheral processor
    • G06F13/124Program control for peripheral devices using hardware independent of the central processor, e.g. channel or peripheral processor where hardware is a sequential transfer control unit, e.g. microprocessor, peripheral processor or state-machine
    • G06F13/128Program control for peripheral devices using hardware independent of the central processor, e.g. channel or peripheral processor where hardware is a sequential transfer control unit, e.g. microprocessor, peripheral processor or state-machine for dedicated transfers to a network
    • GPHYSICS
    • G06COMPUTING; CALCULATING OR COUNTING
    • G06FELECTRIC DIGITAL DATA PROCESSING
    • G06F13/00Interconnection of, or transfer of information or other signals between, memories, input/output devices or central processing units
    • G06F13/14Handling requests for interconnection or transfer
    • G06F13/36Handling requests for interconnection or transfer for access to common bus or bus system
    • G06F13/368Handling requests for interconnection or transfer for access to common bus or bus system with decentralised access control
    • G06F13/37Handling requests for interconnection or transfer for access to common bus or bus system with decentralised access control using a physical-position-dependent priority, e.g. daisy chain, round robin or token passing
    • GPHYSICS
    • G06COMPUTING; CALCULATING OR COUNTING
    • G06FELECTRIC DIGITAL DATA PROCESSING
    • G06F13/00Interconnection of, or transfer of information or other signals between, memories, input/output devices or central processing units
    • G06F13/38Information transfer, e.g. on bus
    • G06F13/42Bus transfer protocol, e.g. handshake; Synchronisation
    • G06F13/4204Bus transfer protocol, e.g. handshake; Synchronisation on a parallel bus
    • G06F13/4208Bus transfer protocol, e.g. handshake; Synchronisation on a parallel bus being a system bus, e.g. VME bus, Futurebus, Multibus
    • G06F13/4217Bus transfer protocol, e.g. handshake; Synchronisation on a parallel bus being a system bus, e.g. VME bus, Futurebus, Multibus with synchronous protocol
    • GPHYSICS
    • G06COMPUTING; CALCULATING OR COUNTING
    • G06FELECTRIC DIGITAL DATA PROCESSING
    • G06F9/00Arrangements for program control, e.g. control units
    • G06F9/06Arrangements for program control, e.g. control units using stored programs, i.e. using an internal store of processing equipment to receive or retain programs
    • G06F9/22Microcontrol or microprogram arrangements
    • G06F9/223Execution means for microinstructions irrespective of the microinstruction function, e.g. decoding of microinstructions and nanoinstructions; timing of microinstructions; programmable logic arrays; delays and fan-out problems
    • GPHYSICS
    • G06COMPUTING; CALCULATING OR COUNTING
    • G06FELECTRIC DIGITAL DATA PROCESSING
    • G06F9/00Arrangements for program control, e.g. control units
    • G06F9/06Arrangements for program control, e.g. control units using stored programs, i.e. using an internal store of processing equipment to receive or retain programs
    • G06F9/22Microcontrol or microprogram arrangements
    • G06F9/226Microinstruction function, e.g. input/output microinstruction; diagnostic microinstruction; microinstruction format
GB08515318A 1984-06-18 1985-06-17 Computer system Expired GB2162406B (en)

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
GB8415474 1984-06-18

Publications (3)

Publication Number Publication Date
GB8515318D0 true GB8515318D0 (en) 1985-08-07
GB2162406A GB2162406A (en) 1986-01-29
GB2162406B GB2162406B (en) 1988-03-09

Family

ID=10562593

Family Applications (1)

Application Number Title Priority Date Filing Date
GB08515318A Expired GB2162406B (en) 1984-06-18 1985-06-17 Computer system

Country Status (1)

Country Link
GB (1) GB2162406B (en)

Families Citing this family (11)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
GB2181578B (en) * 1985-10-09 1990-04-18 Sun Microsystems Inc Clock delay for a central processing unit
US4847750A (en) * 1986-02-13 1989-07-11 Intelligent Instrumentation, Inc. Peripheral DMA controller for data acquisition system
US4868739A (en) * 1986-05-05 1989-09-19 International Business Machines Corporation Fixed clock rate vector processor having exclusive time cycle control programmable into each microword
GB2196450B (en) * 1986-10-20 1991-02-13 Mars Inc Data-storing tokens
FR2615302B1 (en) * 1987-05-14 1991-11-08 Merlin Gerin DECENTRALIZED LOCAL INDUSTRIAL NETWORK WITH TOKEN CIRCULATION
EP0340901A3 (en) * 1988-03-23 1992-12-30 Du Pont Pixel Systems Limited Access system for dual port memory
US5428754A (en) * 1988-03-23 1995-06-27 3Dlabs Ltd Computer system with clock shared between processors executing separate instruction streams
US5056015A (en) * 1988-03-23 1991-10-08 Du Pont Pixel Systems Limited Architectures for serial or parallel loading of writable control store
US4993025A (en) * 1989-11-21 1991-02-12 Picker International, Inc. High efficiency image data transfer network
GB9014811D0 (en) * 1990-07-04 1990-08-22 Pgc Limited Computer
US5953510A (en) * 1991-09-05 1999-09-14 International Business Machines Corporation Bidirectional data bus reservation priority controls having token logic

Family Cites Families (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US4038644A (en) * 1975-11-19 1977-07-26 Ncr Corporation Destination selection apparatus for a bus oriented computer system

Also Published As

Publication number Publication date
GB2162406B (en) 1988-03-09
GB2162406A (en) 1986-01-29

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Legal Events

Date Code Title Description
PCNP Patent ceased through non-payment of renewal fee

Effective date: 19920617