GB8511592D0 - Electrical circuit arrangement - Google Patents
Electrical circuit arrangementInfo
- Publication number
- GB8511592D0 GB8511592D0 GB858511592A GB8511592A GB8511592D0 GB 8511592 D0 GB8511592 D0 GB 8511592D0 GB 858511592 A GB858511592 A GB 858511592A GB 8511592 A GB8511592 A GB 8511592A GB 8511592 D0 GB8511592 D0 GB 8511592D0
- Authority
- GB
- United Kingdom
- Prior art keywords
- electrical circuit
- circuit arrangement
- arrangement
- electrical
- circuit
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Withdrawn
Links
Classifications
-
- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03K—PULSE TECHNIQUE
- H03K3/00—Circuits for generating electric pulses; Monostable, bistable or multistable circuits
- H03K3/02—Generators characterised by the type of circuit or by the means used for producing pulses
- H03K3/027—Generators characterised by the type of circuit or by the means used for producing pulses by the use of logic circuits, with internal or external positive feedback
- H03K3/037—Bistable circuits
-
- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03K—PULSE TECHNIQUE
- H03K3/00—Circuits for generating electric pulses; Monostable, bistable or multistable circuits
- H03K3/02—Generators characterised by the type of circuit or by the means used for producing pulses
- H03K3/353—Generators characterised by the type of circuit or by the means used for producing pulses by the use, as active elements, of field-effect transistors with internal or external positive feedback
- H03K3/356—Bistable circuits
- H03K3/356104—Bistable circuits using complementary field-effect transistors
Priority Applications (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
GB08511592A GB2174856A (en) | 1985-05-08 | 1985-05-08 | Hysteresis latch arrangement |
Applications Claiming Priority (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
GB08511592A GB2174856A (en) | 1985-05-08 | 1985-05-08 | Hysteresis latch arrangement |
Publications (2)
Publication Number | Publication Date |
---|---|
GB8511592D0 true GB8511592D0 (en) | 1985-06-12 |
GB2174856A GB2174856A (en) | 1986-11-12 |
Family
ID=10578782
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
GB08511592A Withdrawn GB2174856A (en) | 1985-05-08 | 1985-05-08 | Hysteresis latch arrangement |
Country Status (1)
Country | Link |
---|---|
GB (1) | GB2174856A (en) |
Families Citing this family (6)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US4820939A (en) * | 1987-11-24 | 1989-04-11 | National Semiconductor Corporation | Finite metastable time synchronizer |
JP2621993B2 (en) * | 1989-09-05 | 1997-06-18 | 株式会社東芝 | Flip-flop circuit |
EP0567716A1 (en) * | 1992-04-30 | 1993-11-03 | STMicroelectronics S.r.l. | Static edgetriggered D flip-flop with a low power consumption |
US6002284A (en) * | 1996-04-24 | 1999-12-14 | Texas Instruments Incorporated | Split-slave dual-path D flip flop |
WO1999003202A2 (en) * | 1997-07-07 | 1999-01-21 | Sergei Kuzmich Luzakov | Level-controlled d-trigger |
US6433603B1 (en) * | 2000-08-14 | 2002-08-13 | Sun Microsystems, Inc. | Pulse-based high speed flop circuit |
Family Cites Families (3)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JPS5511022B2 (en) * | 1972-02-25 | 1980-03-21 | ||
CH590592A5 (en) * | 1973-07-30 | 1977-08-15 | Tokyo Shibaura Electric Co | |
US4277698A (en) * | 1979-06-01 | 1981-07-07 | Motorola, Inc. | Delay type flip-flop |
-
1985
- 1985-05-08 GB GB08511592A patent/GB2174856A/en not_active Withdrawn
Also Published As
Publication number | Publication date |
---|---|
GB2174856A (en) | 1986-11-12 |
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Legal Events
Date | Code | Title | Description |
---|---|---|---|
WAP | Application withdrawn, taken to be withdrawn or refused ** after publication under section 16(1) |