GB8419701D0 - Phase-lock loop circuits - Google Patents

Phase-lock loop circuits

Info

Publication number
GB8419701D0
GB8419701D0 GB848419701A GB8419701A GB8419701D0 GB 8419701 D0 GB8419701 D0 GB 8419701D0 GB 848419701 A GB848419701 A GB 848419701A GB 8419701 A GB8419701 A GB 8419701A GB 8419701 D0 GB8419701 D0 GB 8419701D0
Authority
GB
United Kingdom
Prior art keywords
phase
lock loop
loop circuits
circuits
lock
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Granted
Application number
GB848419701A
Other versions
GB2143408B (en
GB2143408A (en
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
SRI International Inc
Original Assignee
SRI International Inc
Stanford Research Institute
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by SRI International Inc, Stanford Research Institute filed Critical SRI International Inc
Publication of GB8419701D0 publication Critical patent/GB8419701D0/en
Publication of GB2143408A publication Critical patent/GB2143408A/en
Application granted granted Critical
Publication of GB2143408B publication Critical patent/GB2143408B/en
Expired legal-status Critical Current

Links

Classifications

    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11B—INFORMATION STORAGE BASED ON RELATIVE MOVEMENT BETWEEN RECORD CARRIER AND TRANSDUCER
    • G11B20/00—Signal processing not specific to the method of recording or reproducing; Circuits therefor
    • G11B20/10—Digital recording or reproducing
    • G11B20/14—Digital recording or reproducing using self-clocking codes
    • G11B20/1403—Digital recording or reproducing using self-clocking codes characterised by the use of two levels
    • G11B20/1423—Code representation depending on subsequent bits, e.g. delay modulation, double density code, Miller code
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11B—INFORMATION STORAGE BASED ON RELATIVE MOVEMENT BETWEEN RECORD CARRIER AND TRANSDUCER
    • G11B20/00—Signal processing not specific to the method of recording or reproducing; Circuits therefor
    • G11B20/10—Digital recording or reproducing
    • G11B20/14—Digital recording or reproducing using self-clocking codes
    • G11B20/1403—Digital recording or reproducing using self-clocking codes characterised by the use of two levels
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03L—AUTOMATIC CONTROL, STARTING, SYNCHRONISATION OR STABILISATION OF GENERATORS OF ELECTRONIC OSCILLATIONS OR PULSES
    • H03L7/00—Automatic control of frequency or phase; Synchronisation
    • H03L7/06—Automatic control of frequency or phase; Synchronisation using a reference signal applied to a frequency- or phase-locked loop
    • H03L7/08—Details of the phase-locked loop
    • H03L7/14—Details of the phase-locked loop for assuring constant frequency when supply or correction voltages fail or are interrupted
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03L—AUTOMATIC CONTROL, STARTING, SYNCHRONISATION OR STABILISATION OF GENERATORS OF ELECTRONIC OSCILLATIONS OR PULSES
    • H03L7/00—Automatic control of frequency or phase; Synchronisation
    • H03L7/06—Automatic control of frequency or phase; Synchronisation using a reference signal applied to a frequency- or phase-locked loop
    • H03L7/16—Indirect frequency synthesis, i.e. generating a desired one of a number of predetermined frequencies using a frequency- or phase-locked loop
    • H03L7/18—Indirect frequency synthesis, i.e. generating a desired one of a number of predetermined frequencies using a frequency- or phase-locked loop using a frequency divider or counter in the loop
    • H03L7/197—Indirect frequency synthesis, i.e. generating a desired one of a number of predetermined frequencies using a frequency- or phase-locked loop using a frequency divider or counter in the loop a time difference being used for locking the loop, the counter counting between numbers which are variable in time or the frequency divider dividing by a factor variable in time, e.g. for obtaining fractional frequency division
    • H03L7/199—Indirect frequency synthesis, i.e. generating a desired one of a number of predetermined frequencies using a frequency- or phase-locked loop using a frequency divider or counter in the loop a time difference being used for locking the loop, the counter counting between numbers which are variable in time or the frequency divider dividing by a factor variable in time, e.g. for obtaining fractional frequency division with reset of the frequency divider or the counter, e.g. for assuring initial synchronisation
    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04L—TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
    • H04L7/00—Arrangements for synchronising receiver with transmitter
    • H04L7/02—Speed or phase control by the received code signals, the signals containing no special synchronisation information
    • H04L7/033—Speed or phase control by the received code signals, the signals containing no special synchronisation information using the transitions of the received signal to control the phase of the synchronising-signal-generating means, e.g. using a phase-locked loop
    • H04L7/0331—Speed or phase control by the received code signals, the signals containing no special synchronisation information using the transitions of the received signal to control the phase of the synchronising-signal-generating means, e.g. using a phase-locked loop with a digital phase-locked loop [PLL] processing binary samples, e.g. add/subtract logic for correction of receiver clock

Landscapes

  • Engineering & Computer Science (AREA)
  • Signal Processing (AREA)
  • Computer Networks & Wireless Communication (AREA)
  • Stabilization Of Oscillater, Synchronisation, Frequency Synthesizers (AREA)
  • Signal Processing For Digital Recording And Reproducing (AREA)
  • Dc Digital Transmission (AREA)
GB08419701A 1981-11-16 1984-08-02 Phase-lock loop circuits and miller decoders Expired GB2143408B (en)

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
US06/321,542 US4456884A (en) 1981-11-16 1981-11-16 Phase-lock loop and Miller decoder employing the same

Publications (3)

Publication Number Publication Date
GB8419701D0 true GB8419701D0 (en) 1984-09-05
GB2143408A GB2143408A (en) 1985-02-06
GB2143408B GB2143408B (en) 1985-09-18

Family

ID=23251032

Family Applications (2)

Application Number Title Priority Date Filing Date
GB08232517A Expired GB2110894B (en) 1981-11-16 1982-11-15 Phase-lock loop circuits and miller decoders
GB08419701A Expired GB2143408B (en) 1981-11-16 1984-08-02 Phase-lock loop circuits and miller decoders

Family Applications Before (1)

Application Number Title Priority Date Filing Date
GB08232517A Expired GB2110894B (en) 1981-11-16 1982-11-15 Phase-lock loop circuits and miller decoders

Country Status (4)

Country Link
US (1) US4456884A (en)
JP (1) JPS5890829A (en)
DE (1) DE3240731A1 (en)
GB (2) GB2110894B (en)

Families Citing this family (16)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US4470082A (en) * 1982-07-06 1984-09-04 Storage Technology Corporation Digital clocking and detection system for a digital storage system
US4547738A (en) * 1983-06-10 1985-10-15 American Standard Inc. Phase shift demodulator
US4546486A (en) * 1983-08-29 1985-10-08 General Electric Company Clock recovery arrangement
US4743857A (en) * 1984-04-18 1988-05-10 Telex Computer Products, Inc. Digital/analog phase-locked oscillator
US4707842A (en) * 1985-04-03 1987-11-17 Siemens Aktiengesellschaft Apparatus and method for acquiring data and clock pulses from asynchronous data signals
US4769691A (en) * 1987-03-02 1988-09-06 Rca Licensing Corporation Burst locked oscillator with side-lock protection
US4845575A (en) * 1987-10-06 1989-07-04 Standard Microsystems Corporation Analog floppy disk data separator
JPH02156732A (en) * 1988-12-09 1990-06-15 Hitachi Ltd Demodulator
US5095498A (en) * 1989-02-06 1992-03-10 Motorola, Inc. Bit synchronizer
US5206885A (en) * 1989-02-06 1993-04-27 Motorola, Inc. Selective call receiver with fast bit synchronizer
JPH0831847B2 (en) * 1991-10-09 1996-03-27 株式会社ネットワークサプライ Digital signal relay transmission device
US5396522A (en) * 1993-12-02 1995-03-07 Motorola, Inc. Method and apparatus for clock synchronization with information received by a radio receiver
KR100203907B1 (en) * 1996-11-06 1999-06-15 김영환 A bit counter of parallel data
US6265919B1 (en) * 2000-01-28 2001-07-24 Lucent Technologies Inc. In phase alignment for PLL's
JP3989880B2 (en) * 2003-08-20 2007-10-10 松下電器産業株式会社 PLL circuit and video display device
CN101124849B (en) * 2005-01-17 2012-07-04 唯听助听器公司 Device and method for operating hearing aid

Family Cites Families (6)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US3631422A (en) * 1969-02-03 1971-12-28 Ibm System for detection of data time interval measurement
CA1063719A (en) * 1975-04-28 1979-10-02 Control Data Corporation Phase locked loop decoder
FR2361019A1 (en) * 1976-08-04 1978-03-03 Cit Alcatel MILLER CODE MESSAGE DECODING DEVICE
US4143407A (en) * 1977-06-17 1979-03-06 Trw Inc. Magnetic data storage and retrieval system
US4141046A (en) * 1977-09-14 1979-02-20 Exxon Research & Engineering Co. Floppy disc data separator for use with single density encoding
JPS55102930A (en) * 1979-02-02 1980-08-06 Toshiba Corp Pll circuit

Also Published As

Publication number Publication date
GB2110894A (en) 1983-06-22
DE3240731A1 (en) 1983-05-26
GB2110894B (en) 1985-09-11
GB2143408B (en) 1985-09-18
US4456884A (en) 1984-06-26
GB2143408A (en) 1985-02-06
JPS5890829A (en) 1983-05-30

Similar Documents

Publication Publication Date Title
DE3264564D1 (en) Phase-locked loop circuit
EP0085615A3 (en) Phase-locked loop circuit
DE3066285D1 (en) Phase-locked loop circuit
GB2104742B (en) Phase lock circuit
GB2100944B (en) Synchronisation circuits
DE3270002D1 (en) Pll control circuit
DE3268401D1 (en) Phase-locked loop circuit
DE3264676D1 (en) Phase-locked circuits
GB8419701D0 (en) Phase-lock loop circuits
GB2100077B (en) Phase locked loop circuit
GB2097211B (en) Oscillator circuits
GB2118382B (en) Tuning apparatus of phase-locked loop type
GB2098834B (en) Subscribers loop synchronisation
JPS57181233A (en) Digital phase locked loop circuit
GB2100543B (en) Chatter-prevention circuit
ZA84152B (en) Light-sensitive co-condensates
GB2114844B (en) Digital loop filter
GB2122441B (en) Phase-locked loop lock-detecting circuit
EP0149035A3 (en) Photographic roll-printer
ZA832525B (en) Digital phase-locked loop
GB2100296B (en) Loop forming device
DE3277434D1 (en) Reference time-detecting circuit
JPS57201360A (en) Undesired oscillation preventing circuit
JPS57169741A (en) Synchronizing circuit
GB2113929B (en) Oscillator circuits

Legal Events

Date Code Title Description
PCNP Patent ceased through non-payment of renewal fee