841,287. Circuits employing bi-stable magnetic elements. POSTMASTER GENERAL. June 16, 1958 [March 15, 1957], No. 8662/57. Class 40 (9). [Also in Groups XV, XIX and XL (c)] Trigger pair (Fig. 2).-Randomly timespaced negative pulses from transformer TR1 flow through the A windings of two ferrite cores X1, X2 having rectangular hysteresis loops. Initially one is set and the other reset by passing current through oppositely-connected E windings in series. A pulse thus changes the state of one, say X2, and an output pulse appears on T4, T5 and transistor VT2 conducts. The collector current of VT2 flows through the C winding of X2 to assist the change of state and also through the D winding of X1 to change its state. The next random pulse changes the state of X1, causing an output pulse to appear at terminals T2, T3 and the collector current of transistor VT1 assists this change and also changes the state of X2. Thus X1, X2 are alternately reset and set and alternate pulses appear at T2, T3 and T4, T5. Counters and combiners (Fig. 3). α1 and α2 pulses are fed from the T2, T4 terminals of the above trigger pair to the D windings of ferrite cores X3 ... of A counter and α3 and α4 pulses are fed from the T3, T5 terminals of a different trigger pair, supplied from a different random source, to the D windings of cores X13 ... of B counter. The counters are of the ring-type in which the cores are coupled by transistors VT3 . . . and, initially, all cores in each except one are re-set. Each α pulse causes the set condition to be transferred one core round the ring. At particular times the counters are stopped, and their difference is transferred to a store. For this purpose, a combiner comprises ferrite cores X23 ... , the D windings of which are supplied with α1 and α2 pulses and the A windings of which are in series with the A windings of cores X3 .... Thus the combiner cores are set and reset in step with those of A counter. The A windings of B counter cores are in series with the C windings of cores X23 ... so that a pulse in a core X13 . . . will cancel a set condition if present in a corresponding X23 ... core. To ensure one set core in the combiner when the counters are stopped, either B counter is stopped before A counter or they are stopped together and one pulse is fed to the latter. Then a series of time-spaced pulses are fed to the B counter. When the resulting set condition in B counter reaches the core corresponding to the set core in the combiner it cancels it and a pulse appears in line L1 containing the B windings of cores X23 in series. The delay in the issue of this pulse gives a measure of the difference between the numbers in the counters. Stores (Fig. 4b).-The pulse on lead L1 is fed to the emitters of transistors VT34 . . . and a series of time-spaced pulses, synchronized with the series of pulses supplied during reading to the B counter (see above), is supplied to their bases one by one. That transistor receiving coincident pulses conducts and the appropriate ferrite core X34 ... is set by the collector current. Cores X34 ... form the temporary store. After reading of the counters, a shift pulse α5 is applied to cores X34 ... and their condition is transferred via transistors VT34T . . . to cores X34P ... forming primary stores. Shift pulses α6 transfer from the primary stores to secondary store cores X34S ... via transistors VT34P ... but only if a pulse is simultaneously applied to the emitters of VT34P ... through contact T8 and transistor VT47. If this pulse be not forthcoming the α6 pulse erases the signal in the primary store. Gate (Fig. 4a).-Three ferrite cores X44, X45, and X46 are normally reset and a shift pulse α5 is applied to X46 which is thus set and a pulse is applied through transistor VT45 to core X45 tending to set it. Line L2 connected to the emitters of transistors VT34T (see above) includes windings of cores X44, X45 and, if no current be present in L2 (i.e. no signal in temporary stores X34, see above), core X45 is set and a warning device V4 is energized via line T7. If only one signal be in the temporary stores, the current in L2 opposes the setting pulse to X45 and no pulse flows to the warning- device V4. If no more than one signal be present in the temporary stores, the current in L2 not only prevents setting of X45 but is also sufficient to set X44 and thus the warning device V4 is energized through line T7. When the signals are transferred from the primary stores X34P ... to the secondary stores X345 ... by pulses α6, further α6 pulses reset cores X44, X45 and X46. Pulse generator (Fig. 6).-All cores X61 ... X74 are initially reset and a start pulse applied to terminal T23 sets core X61 through transistor VT57. Timed drive pulses are applied to terminal T24 and through transistor VT58 generate α8 pulses applied to cores X61 ... X74 in the resetting direction. Cores X59, X60 are biased towards set condition by current constantly flowing through R23. The first drive pulse resets core X61, causing transistor VT61 to conduct, the emitter current of which assists the resetting of core X61, sets core X62 and resets core X59. The last action produces a pulse at terminal T25 through transistor VT59. Core X59 is then set again by the steady current from resistor R23. The second drive pulse at terminal T24 resets core X62, causing VT62 to conduct and the emitter current causes a pulse to appear at terminal T62 via transistor VTF62, flows through the core X62 helping the resetting, sets core X63, and resets core X60. The last action produces a pulse at terminal T27 via VT60 a shade later than the pulse on terminal T62. Core X60 is then changed to set condition again by the steady current from R23. The next nine drive pulses at terminal T24 produce each a pulse at terminal T27 and a pulse at successive terminals T63 .... The next three drive pulses produce successive pulses one at each of terminals T72, T73 and T74.