GB841277A - Improvements relating to digital computing apparatus - Google Patents
Improvements relating to digital computing apparatusInfo
- Publication number
- GB841277A GB841277A GB2851556A GB2851556A GB841277A GB 841277 A GB841277 A GB 841277A GB 2851556 A GB2851556 A GB 2851556A GB 2851556 A GB2851556 A GB 2851556A GB 841277 A GB841277 A GB 841277A
- Authority
- GB
- United Kingdom
- Prior art keywords
- lines
- devices
- state
- storage devices
- multiplier
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Expired
Links
Classifications
-
- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F7/00—Methods or arrangements for processing data by operating upon the order or content of the data handled
- G06F7/38—Methods or arrangements for performing computations using exclusively denominational number representation, e.g. using binary, ternary, decimal representation
- G06F7/383—Methods or arrangements for performing computations using exclusively denominational number representation, e.g. using binary, ternary, decimal representation using magnetic or similar elements
-
- G—PHYSICS
- G11—INFORMATION STORAGE
- G11C—STATIC STORES
- G11C11/00—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor
- G11C11/21—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements
- G11C11/22—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using ferroelectric elements
Landscapes
- Engineering & Computer Science (AREA)
- General Physics & Mathematics (AREA)
- Theoretical Computer Science (AREA)
- Physics & Mathematics (AREA)
- Computing Systems (AREA)
- Mathematical Analysis (AREA)
- Mathematical Optimization (AREA)
- Pure & Applied Mathematics (AREA)
- General Engineering & Computer Science (AREA)
- Computational Mathematics (AREA)
- Computer Hardware Design (AREA)
- Semiconductor Memories (AREA)
- Hall/Mr Elements (AREA)
Abstract
841,277. Digital electric calculating-apparatus. ASSOCIATED ELECTRICAL INDUSTRIES Ltd. Sept. 11, 1957 [Sept. 18, 1956], No. 28515/56. Class 106 (1). A binary multiplier comprises a lattice of parallel multiplier digit lines Y1 ... Y4 extending in one direction with parallel multiplicand digit lines X1 ... X4 extending laterally across the multiplier lines, a plurality of two-stablestate storage devices X1Y1, Y1X4, Y3X3, &c., operatively located at appropriate intersections of the lines, which assume an " ON " state when operated by both intersecting lines to indicate a binary partial product, and lines P1 ... P8 connecting each diagonal row of storage devices to the appropriate stage of an accumulator. The storage devices are preferably saturable magnetic cores which require the combined effect of current in both the X-line and the Y-line to change their state from " 0 " to " 1." These settings are subsequently read out to the summing lines P1 . . . P8 by applying current pulses to horizontal reset lines in sequence. The reset lines may be energized two at a time. Instead of magnetic cores other two-stable-state devices including ferro-resonant devices, ferroelectric devices, transistors, thermionic valves, and mechanical relays, can be used. Serial accumulation can be obtained by inserting onedigit delays between the summing lines.
Priority Applications (2)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
GB2851556A GB841277A (en) | 1956-09-18 | 1956-09-18 | Improvements relating to digital computing apparatus |
FR1182936D FR1182936A (en) | 1956-09-18 | 1957-09-18 | Improvements to calculating machines |
Applications Claiming Priority (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
GB2851556A GB841277A (en) | 1956-09-18 | 1956-09-18 | Improvements relating to digital computing apparatus |
Publications (1)
Publication Number | Publication Date |
---|---|
GB841277A true GB841277A (en) | 1960-07-13 |
Family
ID=10276861
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
GB2851556A Expired GB841277A (en) | 1956-09-18 | 1956-09-18 | Improvements relating to digital computing apparatus |
Country Status (2)
Country | Link |
---|---|
FR (1) | FR1182936A (en) |
GB (1) | GB841277A (en) |
Cited By (2)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US3104317A (en) * | 1960-02-09 | 1963-09-17 | Ibm | Binary matrix multiplier utilizing coincident inputs and sequential readout |
US3191012A (en) * | 1961-08-24 | 1965-06-22 | Ibm | Memory readout and summing system |
Families Citing this family (1)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US3065423A (en) * | 1959-10-30 | 1962-11-20 | Herbert L Peterson | Simultaneous hybrid digital-analog multiplier |
-
1956
- 1956-09-18 GB GB2851556A patent/GB841277A/en not_active Expired
-
1957
- 1957-09-18 FR FR1182936D patent/FR1182936A/en not_active Expired
Cited By (2)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US3104317A (en) * | 1960-02-09 | 1963-09-17 | Ibm | Binary matrix multiplier utilizing coincident inputs and sequential readout |
US3191012A (en) * | 1961-08-24 | 1965-06-22 | Ibm | Memory readout and summing system |
Also Published As
Publication number | Publication date |
---|---|
FR1182936A (en) | 1959-07-01 |
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