GB8410032D0 - Demodulation circuit - Google Patents

Demodulation circuit

Info

Publication number
GB8410032D0
GB8410032D0 GB848410032A GB8410032A GB8410032D0 GB 8410032 D0 GB8410032 D0 GB 8410032D0 GB 848410032 A GB848410032 A GB 848410032A GB 8410032 A GB8410032 A GB 8410032A GB 8410032 D0 GB8410032 D0 GB 8410032D0
Authority
GB
United Kingdom
Prior art keywords
demodulation circuit
demodulation
circuit
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Withdrawn
Application number
GB848410032A
Other versions
GB2140255A (en
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Deutsche Thomson oHG
Original Assignee
Telefunken Fernseh und Rundfunk GmbH
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Telefunken Fernseh und Rundfunk GmbH filed Critical Telefunken Fernseh und Rundfunk GmbH
Publication of GB8410032D0 publication Critical patent/GB8410032D0/en
Publication of GB2140255A publication Critical patent/GB2140255A/en
Withdrawn legal-status Critical Current

Links

Classifications

    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11B—INFORMATION STORAGE BASED ON RELATIVE MOVEMENT BETWEEN RECORD CARRIER AND TRANSDUCER
    • G11B20/00—Signal processing not specific to the method of recording or reproducing; Circuits therefor
    • G11B20/10—Digital recording or reproducing
    • G11B20/14—Digital recording or reproducing using self-clocking codes
    • G11B20/1403—Digital recording or reproducing using self-clocking codes characterised by the use of two levels
    • G11B20/1407—Digital recording or reproducing using self-clocking codes characterised by the use of two levels code representation depending on a single bit, i.e. where a one is always represented by a first code symbol while a zero is always represented by a second code symbol
    • G11B20/1419—Digital recording or reproducing using self-clocking codes characterised by the use of two levels code representation depending on a single bit, i.e. where a one is always represented by a first code symbol while a zero is always represented by a second code symbol to or from biphase level coding, i.e. to or from codes where a one is coded as a transition from a high to a low level during the middle of a bit cell and a zero is encoded as a transition from a low to a high level during the middle of a bit cell or vice versa, e.g. split phase code, Manchester code conversion to or from biphase space or mark coding, i.e. to or from codes where there is a transition at the beginning of every bit cell and a one has no second transition and a zero has a second transition one half of a bit period later or vice versa, e.g. double frequency code, FM code

Landscapes

  • Engineering & Computer Science (AREA)
  • Signal Processing (AREA)
  • Dc Digital Transmission (AREA)
  • Signal Processing For Digital Recording And Reproducing (AREA)
GB08410032A 1983-04-21 1984-04-18 Demodulation circuit for a biphase signal Withdrawn GB2140255A (en)

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
DE19833314393 DE3314393A1 (en) 1983-04-21 1983-04-21 DEMODULATION CIRCUIT FOR A BIPHASE SIGNAL

Publications (2)

Publication Number Publication Date
GB8410032D0 true GB8410032D0 (en) 1984-05-31
GB2140255A GB2140255A (en) 1984-11-21

Family

ID=6196933

Family Applications (1)

Application Number Title Priority Date Filing Date
GB08410032A Withdrawn GB2140255A (en) 1983-04-21 1984-04-18 Demodulation circuit for a biphase signal

Country Status (4)

Country Link
JP (1) JPS59205859A (en)
DE (1) DE3314393A1 (en)
FR (1) FR2544937A1 (en)
GB (1) GB2140255A (en)

Families Citing this family (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH0740332B2 (en) * 1986-10-11 1995-05-01 ソニー株式会社 Data playback device

Family Cites Families (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US3863024A (en) * 1973-12-26 1975-01-28 Ibm Directional coupled data transmission system
IT1158893B (en) * 1978-07-28 1987-02-25 Sits Soc It Telecom Siemens CIRCUIT PROVISION FOR THE GENERATION OF SAMPLING PULSES OF PARTICULAR APPLICATION IN THE RECEIVING STATION OF A SYSTEM FOR DATA TRANSMISSION
GB2123258A (en) * 1982-06-25 1984-01-25 Philips Electronic Associated Digital duplex communication system

Also Published As

Publication number Publication date
FR2544937A1 (en) 1984-10-26
DE3314393A1 (en) 1984-10-25
JPS59205859A (en) 1984-11-21
GB2140255A (en) 1984-11-21

Similar Documents

Publication Publication Date Title
GB8402650D0 (en) Circuit
GB8430050D0 (en) Circuit arrangements
GB8422999D0 (en) Circuit arrangement
GB8401959D0 (en) Integrated circuit
GB8412737D0 (en) Circuit arrangement
GB8428805D0 (en) Circuit arrangement
GB8431766D0 (en) Circuit arrangement
GB8410849D0 (en) Circuit
GB8300732D0 (en) Circuit
GB8430687D0 (en) Circuit
GB8413349D0 (en) Circuit means
GB8412360D0 (en) Integrated circuit
GB8411891D0 (en) Circuit
GB2144283B (en) Demodulator
GB8310400D0 (en) Demodulator circuit
GB8404826D0 (en) Equaliser circuit
GB8324713D0 (en) Circuits
GB8411875D0 (en) Circuits
GB8401298D0 (en) Circuit
DE3474387D1 (en) Fm demodulation circuit
DE3364144D1 (en) Demodulator circuit
GB8430729D0 (en) Circuit arrangements
GB2192506B (en) Demodulation circuit
GB8319793D0 (en) Circuit arrangement
JPS57180208A (en) Demodulating circuit

Legal Events

Date Code Title Description
WAP Application withdrawn, taken to be withdrawn or refused ** after publication under section 16(1)