GB782262A - Improvements in or relating to devices for passing electric signals with time delay - Google Patents

Abstract

782,262. Pulse delaying circuits. GENERAL ELECTRIC CO., Ltd., and IMM, R. C. Nov. 25, 1954 [Nov. 30, 1953], No. 33273/53. Class 40 (6). A pulse delaying circuit comprises a cathodecoupled pair of electric discharge-tubes to the grid of the first of which the input pulse train to be delayed is applied and the anode of the second tube of the pair is connected to a positive supply line via a capacitor. A positive-going pulse train is supplied via a unidirectional conducting device to the anode of the second tube of the pair and a second train having the same pulse repetition frequency as the first but delayed in time with respect to it is applied to the control grid of the second tube of the pair so that upon the occurrence of each pulse of the second train the anode voltage of the second tube is dependent upon the voltage value of the input signal. Fig. 1 shows two stages of a pulse delaying device in which the input pulse train, Fig. 2c, is applied to the control grid of a first tube 2 of a cathode-coupled pair of tubes 2, 3. The input train is a pulse code modulation signal which is divided up into a number of adjacent intervals in each of which there may be a positive-going pulse in dependence upon the modulating signal. A train of positive-going pulses, Fig. 2a, is applied to the anode of a diode 15 and a similar train of pulses, Fig. 2b, but slightly delayed with respect to the first is applied to the control grid of tube 3 of the cathode-coupled pair. In the absence of a positive input signal when a pulse such as 18, Fig. 2a, is applied at point A capacitor 12 is charged to a voltage level 19, Fig. 2d. When the next of the pulses applied to the control grid of tube 3, for example 17, Fig. 2d, occurs, tube 3 conducts and capacitor 12 is discharged to a voltage level 21, Fig. 2d. When, however, a positive-going pulse such as shown at 22, Fig. 2c, is applied at input C tube 2 conducts and due to the current flow in resistor 4 tube 3 is cut off so that pulse 17<SP>1</SP> applied at control grid of tube 3 has no effect on the conductivity of this tube and capacitor 12 remains charged. When the next pair of pulses 18<SP>11</SP> and 17<SP>11</SP> appear the voltage drops to level 21, thus as will be seen at point D a pulse train occurs which after the first pair of pulses 17, 18 is a delayed version of the pulse occurring at the input C. An integrating network 24, 25 is provided between the output of one delay stage comprising tubes 2, 3 and the input of a further similar stage. The voltage on the control grid 26 of tube 23 as shown in Fig. 2e, is clamped by diode 27 to the same level as is the voltage on the grid of tube 2, thus upon the occurrence of pulses 17<SP>1</SP>, 18<SP>1</SP> the voltage on grid 26 is insufficient for the voltage on anode 27 to be raised to its higher value although pulses 17<SP>11</SP>, 18<SP>11</SP> do cause that to occur. The voltage on anode 27, as shown in Fig. 2f, is a delayed version of that occurring at the anode of tube 3.