GB760239A - Improvements in or relating to computing systems - Google Patents

Improvements in or relating to computing systems

Info

Publication number
GB760239A
GB760239A GB30095/53A GB3009553A GB760239A GB 760239 A GB760239 A GB 760239A GB 30095/53 A GB30095/53 A GB 30095/53A GB 3009553 A GB3009553 A GB 3009553A GB 760239 A GB760239 A GB 760239A
Authority
GB
United Kingdom
Prior art keywords
instruction
instructions
drum
annex
digits
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Expired
Application number
GB30095/53A
Inventor
Esmond Philip Goodwin
Joseph Rice
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
STC PLC
Original Assignee
Standard Telephone and Cables PLC
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Priority claimed from GB12060/51A external-priority patent/GB744352A/en
Priority claimed from GB783453A external-priority patent/GB765072A/en
Application filed by Standard Telephone and Cables PLC filed Critical Standard Telephone and Cables PLC
Priority to GB30095/53A priority Critical patent/GB760239A/en
Publication of GB760239A publication Critical patent/GB760239A/en
Priority claimed from GB1941057A external-priority patent/GB845216A/en
Expired legal-status Critical Current

Links

Classifications

    • HELECTRICITY
    • H04ELECTRIC COMMUNICATION TECHNIQUE
    • H04QSELECTING
    • H04Q3/00Selecting arrangements
    • H04Q3/42Circuit arrangements for indirect selecting controlled by common circuits, e.g. register controller, marker
    • GPHYSICS
    • G06COMPUTING; CALCULATING OR COUNTING
    • G06FELECTRIC DIGITAL DATA PROCESSING
    • G06F13/00Interconnection of, or transfer of information or other signals between, memories, input/output devices or central processing units
    • G06F13/14Handling requests for interconnection or transfer
    • G06F13/16Handling requests for interconnection or transfer for access to memory bus
    • G06F13/1668Details of memory controller
    • G06F13/1689Synchronisation and timing concerns
    • GPHYSICS
    • G06COMPUTING; CALCULATING OR COUNTING
    • G06FELECTRIC DIGITAL DATA PROCESSING
    • G06F15/00Digital computers in general; Data processing equipment in general
    • G06F15/04Digital computers in general; Data processing equipment in general programmed simultaneously with the introduction of data to be processed, e.g. on the same record carrier
    • GPHYSICS
    • G06COMPUTING; CALCULATING OR COUNTING
    • G06KGRAPHICAL DATA READING; PRESENTATION OF DATA; RECORD CARRIERS; HANDLING RECORD CARRIERS
    • G06K17/00Methods or arrangements for effecting co-operative working between equipments covered by two or more of main groups G06K1/00 - G06K15/00, e.g. automatic card files incorporating conveying and reading operations
    • GPHYSICS
    • G11INFORMATION STORAGE
    • G11CSTATIC STORES
    • G11C11/00Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor
    • G11C11/21Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements
    • G11C11/22Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using ferroelectric elements
    • HELECTRICITY
    • H04ELECTRIC COMMUNICATION TECHNIQUE
    • H04LTRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
    • H04L13/00Details of the apparatus or circuits covered by groups H04L15/00 or H04L17/00
    • H04L13/02Details not particular to receiver or transmitter
    • H04L13/08Intermediate storage means
    • HELECTRICITY
    • H04ELECTRIC COMMUNICATION TECHNIQUE
    • H04LTRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
    • H04L25/00Baseband systems
    • H04L25/02Details ; arrangements for supplying electrical power along data transmission lines
    • H04L25/20Repeater circuits; Relay circuits
    • H04L25/24Relay circuits using discharge tubes or semiconductor devices
    • H04L25/242Relay circuits using discharge tubes or semiconductor devices with retiming
    • H04L25/245Relay circuits using discharge tubes or semiconductor devices with retiming for start-stop signals

Abstract

760,239. Digital electric calculating-apparatus. STANDARD TELEPHONES & CABLES, Ltd. Oct. 22, 1954 [Oct. 30, 1953], No. 30095/53. Class 106 (1). Intelligence handling equipment comprises a plurality of individual instruction stores and a binary store for a selecting instruction having as many digit positions as there are individual instruction stores, each digit position being associated with a corresponding instruction store, and means for utilizing such of said instructions as are specified by a selecting instruction stored in said binary store. As described, the equipment can operate in two basic ways, (a) in which alternate instructions and data are sent from a tape reader 1, Fig. 6, to the equipment, each instruction applying only to the data that immediately follows it and (b) in which first, a set of instructions is fed from the tape to the equipment and is stored on a drum 13, second a selecting construction is fed to the apparatus and registered in a shifting-register staticisor 18, and thirdly data is fed to the equipment and successive portions are operated upon by instructions selected, in accordance with the selecting instruction, from those previously recorded on the drum. Which of the two ways of operating is used is determined by the first two digits of the first instruction word. These first two digits are always entered via an input switch IS, 3, and registered in the first two stages of a flip-flop staticisor-decoder 4, which as a result of sensing these digits either opens a gate 8 or does not. If (a)-type operation is indicated, gate 8 remains closed and the rest ofthe instruction is staticised in the decoder. At the end of this an electronic switch 3 is transferred to pass the next following input which will be data, direct to an arithmetic unit which operates in a manner directed by the instruction staticised in the decoder and discharges the processed data via a lead 7. A " not ready " signal is passed from the arithmetic unit during its operation via a lead 12A to an input control device 2, which signal prevents further input until the present staticised instruction has been implemented. When the arithmetic circuit is finished switch 3 is transferred back and the equipment is ready to receive the next instruction which can specify either (a) or (b)- type operation. If the next instruction is for (b)-type operation then its first two digits will indicate that it is the first of a sequence of instructions. These two digits are put in the decoder, which, sensing that the instruction is the first of a sequence of instructions, opens gate 8, and simultaneously transfers these first two digits direct to a stepping register annex 1, the remaining digits of the first instruction are then stepped into annex 1 via gate 8 and electronic switch 10. The stepping pulses for this read-in will, of course, be in synchronism with the input from the tape and will generally be at a slower rate than the digit-clock pulses produced by the drum. When this first instruction has been read into annex 1 switch 10 will be transferred. Two operations then take place simultaneously, (1) a second instruction word is stepped via switch 10 into annex 2 under the control of input-clock pulses and (2) the instruction word in annex 1 is stepped by digit-clock pulses derived from the drum via switch 15 and a combined read/write head into compartment 1 on a track 12 of the drum, this second operation being controlled by coincidence between two chain counters, one of which counts the instructions as they arrive and is stepped on one stage after each instruction is put on the drum, and a second which counts the compartments on the drum as they pass the reading head, and usually taking less time than is taken for annex 2 to be filled, and being followed by the transference of switch 15 in preparation for writing the second instruction in compartment 2 on the drum. This process continues, annexes 1 and 2 being alternately filled by input instructions and each being entered on to the drum while the other fills, until an instruction whose first two digits specify that it is the last instruction of a sequence of instructions arrives. When this last instruction arrives it is recognised by,the decoder (each instruction goes into the decoder even though it passes also to some other register) which, after the instruction has entered an annex zeroizes the counter that counted the instruction as they came in. This counter is now ready to count out the instructions from the drum. The next input of the equipment will be an instruction which may be one of three kinds (1) a " normal " instruction which specifies (a)-type operation and applies to the next following data only, (2) a " select instruction which specifies which of the instructions recorded on the drum are to be used in conjunction with the data immediately following it or (3) it may specify that it is the first instruction of a sequence of instructions. If the instruction is of type (3), which is unlikely at this stage, a new set of instructions will be sent to the drum replacing those already there. If the instruction is of type (1), (a)-type operation, as described above, will ensue. If the instruction is a " select " instruction, which will be indicated by the first two digits, this fact will be sensed by the decoder which will cause the subsequent digits to pass to a select instruction register 18 and at the end of this will transfer switch 3 and open gate 8. Following input data will then go direct to the arithmetic circuit 5 to be operated upon by instructions selected from the drum in accordance with the staticised select instruction. Immediately the select instruction is staticised, the first instruction specified by it, say that in compartment 3 (which means that the digits of the select instruotion will be 001 ... ) is read from the drum and entered via a device 19 and gate 2 into annex 1. Switch 10 then changes over so that the second instruction specified by the select instruction can be entered into annex 2 and simultaneously the instruction in annex 1 is put into the decoder by gating arrangements 21. Input data can then be received at any time after this and when it does arrive the first portion is operated upon under the control of the instruction in the decoder in the arithmetic circuit. When this first portion has been processed it is discharged via lead 7 and the second instruction, which is in annex 2, is transferred to the decoder. Simultaneously with this, the third instruction specified by the select instruction is passed from the drum to annex 1, displacing the first instruction as it is stepped in. This process is repeated until all the instructions specified by the select instruction have been used when the equipment returns to its initial condition to await a further input instruction. The instructions previously recorded on the drum remain there until different instructions are recorded on top of them and can of course be used by further select instructions. Specification 732,341 is referred to.
GB30095/53A 1951-05-23 1953-10-30 Improvements in or relating to computing systems Expired GB760239A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
GB30095/53A GB760239A (en) 1951-05-23 1953-10-30 Improvements in or relating to computing systems

Applications Claiming Priority (5)

Application Number Priority Date Filing Date Title
GB12060/51A GB744352A (en) 1953-03-20 1951-05-23 Improvements in or relating to intelligence storage equipment
GB783453A GB765072A (en) 1953-03-20 1953-03-20 Improvements in or relating to data processing equipment
GB30095/53A GB760239A (en) 1951-05-23 1953-10-30 Improvements in or relating to computing systems
NL794126X 1954-06-25
GB1941057A GB845216A (en) 1957-06-20 1957-06-20 Improvements in or relating to electrical calculating circuits

Publications (1)

Publication Number Publication Date
GB760239A true GB760239A (en) 1956-10-31

Family

ID=32996441

Family Applications (1)

Application Number Title Priority Date Filing Date
GB30095/53A Expired GB760239A (en) 1951-05-23 1953-10-30 Improvements in or relating to computing systems

Country Status (1)

Country Link
GB (1) GB760239A (en)

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