GB737498A - Testing arrangements for intelligence storage equipment - Google Patents
Testing arrangements for intelligence storage equipmentInfo
- Publication number
- GB737498A GB737498A GB823253A GB823253A GB737498A GB 737498 A GB737498 A GB 737498A GB 823253 A GB823253 A GB 823253A GB 823253 A GB823253 A GB 823253A GB 737498 A GB737498 A GB 737498A
- Authority
- GB
- United Kingdom
- Prior art keywords
- section
- track
- recording
- counter
- test
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Expired
Links
Classifications
-
- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F11/00—Error detection; Error correction; Monitoring
- G06F11/07—Responding to the occurrence of a fault, e.g. fault tolerance
- G06F11/0703—Error or fault processing not based on redundancy, i.e. by taking additional measures to deal with the error or fault not making use of redundancy in operation, in hardware, or in data representation
- G06F11/0766—Error or fault reporting or storing
- G06F11/0772—Means for error signaling, e.g. using interrupts, exception flags, dedicated error registers
-
- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F11/00—Error detection; Error correction; Monitoring
- G06F11/07—Responding to the occurrence of a fault, e.g. fault tolerance
- G06F11/0703—Error or fault processing not based on redundancy, i.e. by taking additional measures to deal with the error or fault not making use of redundancy in operation, in hardware, or in data representation
- G06F11/0706—Error or fault processing not based on redundancy, i.e. by taking additional measures to deal with the error or fault not making use of redundancy in operation, in hardware, or in data representation the processing taking place on a specific hardware platform or in a specific software environment
- G06F11/0727—Error or fault processing not based on redundancy, i.e. by taking additional measures to deal with the error or fault not making use of redundancy in operation, in hardware, or in data representation the processing taking place on a specific hardware platform or in a specific software environment in a storage system, e.g. in a DASD or network based storage system
-
- G—PHYSICS
- G11—INFORMATION STORAGE
- G11C—STATIC STORES
- G11C11/00—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor
- G11C11/02—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using magnetic elements
- G11C11/06—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using magnetic elements using single-aperture storage elements, e.g. ring core; using multi-aperture plates in which each individual aperture forms a storage element
- G11C11/06007—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using magnetic elements using single-aperture storage elements, e.g. ring core; using multi-aperture plates in which each individual aperture forms a storage element using a single aperture or single magnetic closed circuit
- G11C11/06014—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using magnetic elements using single-aperture storage elements, e.g. ring core; using multi-aperture plates in which each individual aperture forms a storage element using a single aperture or single magnetic closed circuit using one such element per bit
-
- G—PHYSICS
- G11—INFORMATION STORAGE
- G11C—STATIC STORES
- G11C29/00—Checking stores for correct operation ; Subsequent repair; Testing stores during standby or offline operation
-
- G—PHYSICS
- G11—INFORMATION STORAGE
- G11C—STATIC STORES
- G11C29/00—Checking stores for correct operation ; Subsequent repair; Testing stores during standby or offline operation
- G11C29/02—Detection or location of defective auxiliary circuits, e.g. defective refresh counters
-
- G—PHYSICS
- G11—INFORMATION STORAGE
- G11C—STATIC STORES
- G11C29/00—Checking stores for correct operation ; Subsequent repair; Testing stores during standby or offline operation
- G11C29/04—Detection or location of defective memory elements, e.g. cell constructio details, timing of test signals
- G11C29/08—Functional testing, e.g. testing during refresh, power-on self testing [POST] or distributed testing
- G11C29/12—Built-in arrangements for testing, e.g. built-in self testing [BIST] or interconnection details
- G11C29/38—Response verification devices
- G11C29/40—Response verification devices using compression techniques
-
- H—ELECTRICITY
- H04—ELECTRIC COMMUNICATION TECHNIQUE
- H04Q—SELECTING
- H04Q3/00—Selecting arrangements
Landscapes
- Engineering & Computer Science (AREA)
- Theoretical Computer Science (AREA)
- Quality & Reliability (AREA)
- Physics & Mathematics (AREA)
- General Engineering & Computer Science (AREA)
- General Physics & Mathematics (AREA)
- Computer Hardware Design (AREA)
- Computer Networks & Wireless Communication (AREA)
- Recording Or Reproducing By Magnetic Means (AREA)
Abstract
737,498. Digital electric calculating-apparatus. STANDARD TELEPHONES & CABLES, Ltd. March 25, 1953, No. 8232/53. Class 106 (1). Intelligence storage equipment comprises a memory device subdivided into a number of separate storage sections and a test section, recording and reading means associated with the memory device and arranged to co-operate with the sections, a control circuit associated with the recording and reading means and arranged to perform a sequence of operations in co-operation with the respective storage sections, means responsive to the bringing of the test section into operative relation with the recording and reading means to initiate a test sequence of operations by the control circuit, means for checking the test sequence and means for indicating if the test sequence is not correctly performed. In a first embodiment the equipment comprises a magnetic drum memory 1, Fig. 1, having read/record heads 5, 6, 7 cooperating with tracks 2, 3, 4. Each track is divided into a number of individual sections which need not be of equal length, the beginning of each section being defined by signals on a marker track 9, which signals are fed to a counter MPC. Each possible element position is defined by signals on a clock track 10, which signals step on a counter CPC to register the number of elements in each section before being zeroized by a signal from track 9 marking the beginning of the next section. In the present example the eleventh (last) section of each information track 2, 3, 4, &c., is used for testing purposes. The energization of the eleventh section of the counter MPC opens a gate G12 to allow the reading of this section of the track to pass to a testing device 13. Information is recorded in each section in binary code and, after being picked up by the reading head, is either returned to the record surface unchanged or, if a signal is present on the incoming line associated with the section under examination, the binary value is increased by one by recording the reverse of each binary digit received up to and including the first zero and thereafter recording the digits unchanged. The test section, however, provides only one binary digit position, and since a signal T, representing an incoming line signal, is provided permanently at a gate G11, the binary digit in the test section alternates between " 1 " and " 0 " continuously. These alternations may be compared with the alternations of a trigger circuit operated by the zeroizing pulse of the counter MPC. Any disagreement would give an output to operate an alarm 14. A single common control circuit 8 may be associated with a number of tracks in turn by employing an additional " track counter " (Fig. 2, not shown). Other embodiments are described in which the memory unit consists of (1) a mercury delay line, (2) a CRT-type memory, (3) a matrix of saturable magnetic cores, and (4) a matrix of ferroelectric elements.
Priority Applications (12)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
US417189A US2936443A (en) | 1953-03-25 | 1954-03-18 | Testing arrangements |
CH334160D CH334160A (en) | 1953-03-25 | 1954-03-22 | Information storage equipment |
NL186175A NL104026C (en) | 1953-03-25 | 1954-03-24 | Apparatus for recording messages with a memory device, provided with a special recording section for examining the proper operation of a circuit controlling the memory device |
DEI8436A DE951636C (en) | 1953-03-25 | 1954-03-24 | Control device for multiple memories in telecommunications, especially telephone systems |
FR1098805D FR1098805A (en) | 1953-03-25 | 1954-03-24 | Recording device control arrangements |
BE527586A BE527586A (en) | 1953-03-25 | 1954-03-25 | Recording device control arrangements |
GB37419/55A GB786469A (en) | 1953-03-25 | 1955-12-30 | Improvements in or relating to intelligence storage equipment |
US621361A US2904778A (en) | 1953-03-25 | 1956-11-09 | Intelligence storage equipment |
DEI12608A DE1079355B (en) | 1953-03-25 | 1956-12-22 | Testing device for ferromagnetic and ferroelectric memory arrays |
FR70881D FR70881E (en) | 1953-03-25 | 1956-12-28 | Recording device control arrangements |
GB8805/59A GB904335A (en) | 1953-03-25 | 1959-03-13 | Improvements in or relating to alarm and test equipment |
FR821095A FR77337E (en) | 1953-03-25 | 1960-03-11 | Recording device control arrangements |
Applications Claiming Priority (2)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
GB37419/55A GB786469A (en) | 1953-03-25 | 1955-12-30 | Improvements in or relating to intelligence storage equipment |
GB8805/59A GB904335A (en) | 1953-03-25 | 1959-03-13 | Improvements in or relating to alarm and test equipment |
Publications (1)
Publication Number | Publication Date |
---|---|
GB737498A true GB737498A (en) | 1955-09-28 |
Family
ID=26242434
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
GB823253A Expired GB737498A (en) | 1953-03-25 | 1953-03-25 | Testing arrangements for intelligence storage equipment |
Country Status (1)
Country | Link |
---|---|
GB (1) | GB737498A (en) |
Cited By (1)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US3081451A (en) * | 1956-08-28 | 1963-03-12 | Int Standard Electric Corp | Serial number issuing equipment |
-
1953
- 1953-03-25 GB GB823253A patent/GB737498A/en not_active Expired
Cited By (1)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US3081451A (en) * | 1956-08-28 | 1963-03-12 | Int Standard Electric Corp | Serial number issuing equipment |
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