GB730672A - Improvements in delay circuits for electronic digital computing apparatus - Google Patents

Abstract

730,672. Pulse delaying circuits. ELLIOTT BROS. (LONDON), Ltd. Nov. 25, 1953 [Nov. 25, 1952], No. 29845/52. Class 40 (6). A pulse delay circuit comprises two discharge tubes to the grid of the first of which the pulse signal to be delayed is applied and the second of which is connected as a cathode - follower, the intertube coupling circuit comprising an inductor, capacitor and semi-conductor device connected in a. closed loop so that the capacitor is charged by the input pulses and is periodically discharged by reset pulses applied to the second tube. Fig. 1 shows two delay circuits connected in tandem. Positive going input pulses, Fig. 2 (c), are applied at either terminal 1 or 3 and gate positive going clock pulses, Fig. 2 (a) applied to crystal diode XI so that selected clock pulses, Fig. 2 (d) are applied to the control grid of tube VI. The inductive load L1 " rings " when a pulse is applied, so that a waveform as shown at Fig. 2 (e) is produced across L1. Capacitor C2 is charged during the positive portions of this waveform and is discharged by the negative pulses of a resetting voltage, Fig. 2 (b) which is applied via crystal diodes. X4, X5 so that a voltage as shown in Fig. 2 (f) is produced at the grid of cathode-follower stage V2. An output pulse, Fig. 2 (g) appears at the cathode of tube V2 the individual pulses of which are delayed with respect to those of the input waveform of Fig. 2 (c) by one digit period.