GB2619906A - Autonomous ambient energy management system - Google Patents

Abstract

Random Ambient Energy requires energy storage for long periods. In physically small consumer products this presents significant problems due to limited space restricting inbuilt storage capacity. We solve the zero-energy cold start issue then target multi-decade maintenance-free end-product lifetime through use of source load-pull estimation to efficiently sink energy from solid-state P-N junction harvesters typical of Electromagnetic, Photoelectric, Thermoelectric and Dielectric Elastomer Generators whilst compensating aging over time. A High-Voltage bi-directional interface services near-zero-loss dielectric storage using COTS capacitor arrays to address storage-cell aging. A flexible PMMIC architecture supports multiple energy sources whilst multiple PMMICs arrayed in parallel deliver much higher output power and storage capacity. We retain input efficiency whilst increasing maintenance-free life targeting mobile autonomous Personal Area Networks, Wireless Sensor Networks and Wireless Body Networks. Limits for these arrays shifts to space, thermal loading and current carrying capability of the host product and how that is applied.

Description

Autonomous Ambient Energy Management System

DESCRIPTION

This invention relates to additions and improvements to a Power Management Monolithic Integrated Circuit to increase efficiency and serviceable life of products using solid-state P-N junction ambient energy harvesters. These enable solid-state Dielectric Energy Storage and Dielectric Elastomer Energy Storage to be used with Solid-State Energy Harvesters and Dielectric Elastomer Generators in long-life autonomous end-products.

Large-scale ambient energy harvesters have existed for thousands of years in the form of wind or hydro generation. Energy Harvesting extended into electric systems with the advent of thermocouples and photoelectric cells in the nineteenth century then into electronic systems using piezo-electric energy harvesters in the twentieth century. Whilst there have been many attempts to create suitable autonomous Power Management Integrated-Circuits for physically small electronic products particularly for micro-generation in personal mobile applications in recent years, most have failed to deliver the decades of useable life-time promised by ever present ambient environmental-energy.

The random nature of ambient environmental energy gives rise to the need to store energy for long periods. In physically small consumer products this presents significant problems where limited space and therefore capacity of their inbuilt energy storage systems. Some very good primary cells that can last ten years or more are available however their shelf-life and capacity remain time limited. However, Ambient Environmental Energy will be available far beyond our lifetimes. Even at micro-power levels, ambient energy from our immediate personal environment is in the 100mW/cre2 down to luW/cm"2 level in the form of light, heat, radio, TV, mobile-phone and WLAN transmissions. Light, whether in the form of solar or artificial, stands out from the others in terms of energy density and available lifetime -the sun shines everywhere for six months per year and we seem to like to turn-on at least one light per person per night.

Simplified, the challenge becomes: how large can the antenna aperture be on the end product? How low can the leakage in your storage facility be made? Knowing those two things we can "right-size" the storage capability to maximise storage standby time and then determine when we have to shut-down the application -this can mean: what is the active to dormant duty cycle of our application and can the end-product tolerate running at a minimum rate but still appear to be immediately responsive? The key to a functional product remains a question of the percentage loss of harvested energy into the storage facility or the dormant product and how does this compare to that of the above long-life primary cell? Given that an environmental energy source should be no worse than that primary cell, the 4.5k3 of storage for say a 3.6V/350mAhr button-cell calculates out to be a ten-year averaged power of 13uW leaving 106 remnant charge Lc) power Ihe applica Lion. This Se La Ihe minimum usable payload for the physical product at 454J being 250 days of operation for a state-of-the-art BuW microprocessor distributed over the whole lifetime of the button-cell. Put another way, we can run the microprocessor for 68.5ms every second of that ten years or an 8.6mJ load at an 8Hz rate. So, if our PMMIC can accumulate 181mJ per day we can power the microprocessor forever no button-cells needed.

Autonomous Ambient Energy Management System DESCRIPTION (continued) Extended-life Micro-generation precludes the use of mechanical harvesters such as those in vibration or inductive movement-based systems due to maintenance issues around material fatigue. However, we are still seeing that solid-state P-N junction harvesters such as photoelectric cells, thermoelectric cells or electromagnetic (RE "Rectenna") arrays have not reached their full potential for three basic but challenging reasons: i) Total loss of sufficient energy to restart system after extended blackout periods.

ii) Leakage in readily available storage cells and their degradation due to ageing of their internal chemical processes exceeds the total energy harvested when averaged over long periods.

iii) Dependable, robust start-up under random conditions disadvantage microprocessors in mission-critical operations such as cold-start, minimal input or input fade. Total depletion of primary and/or secondary cell aging also determine maintenance-free life-time.

We have embedded our solution for these in three Power Management Monolithic Integrated Circuits: the first the SDC2021, a Cold-Start Maximum Power-Point Track-and-Hold Boost Converter PMMIC numbered 11001 in the following DESCRIPTION, DRAWINGS and CLAIMS. The second is the 5DC2022, a Single-Inductor Charge-Storage and Recovery Regulator which is numbered [200] in the following DESCRIPTION, DRAWINGS and CLAIMS. The third PMMIC is the 5DC2023 which is the Ambient Energy Management System PMMIC being an integration of the above two devices into one System-on-Chip ASIC and numbered [300] in the following DESCRIPTION, DRAWINGS and CLAIMS.

The CSMPPTBC [100] addresses i) the restart on zero energy issue above and iii) identifying initial run conditions correctly. It also measures the input harvesters open circuit voltage then returns a reference voltage equivalent to ln(2) or 0.963 times that open circuit voltage as this is the maximum-power transfer-point for a solid-state semiconductor source such as a solar cell or Seebeck device.

The SICSnRreg [200] addresses ii) the storage, aging and leakage issues. Since our design re-uses the primary switch device as an active rectifier in the energy recovery phase of its operation and we provide a floating active rectifier stage that can be used as a secondary switch in energy recovery mode. The storage voltage range is flexible and depending on the flying inductor used and can support standard Lithium rechargeable cells singly or in stacks for bulk storage at high input powers or at moderate to high voltage for near-zero loss dielectric cells which are particularly interesting for Wireless Body Networks as the cells can be made from low toxicity materials such as Dielectric Elastomers and are suited to body implantation. It also becomes possible to "right-size" a cell's storage capaciloy versus iIs leakage Lime ounsIanI whilsio ensuring Llia L tile cells' loss remains small compared to the averaged energy being harvested.

The AIMS SoC [300] is a super-set of [100] and [200] and addresses all three issues above in one autonomous package and is the first of new kind of PMIC that solves the issue of zero-power start-up and the issue of near-zero loss storage issues of i) and ii) concurrently.

Autonomous Ambient Energy Management System

DESCRIPTION (continued)

As all three parts can be applied as stand-alone autonomous PMMICs they avoid the need software upgrades, field maintenance or cell replacement on total depletion as well as addressing the mission-critical start-up and run issues. Figures 1 to 10 illustrate our Autonomous Ambient Energy Management System.

DESCRIPTION OF THE DRAWINGS:

Figure 1: Figure 2: Figure 3: Figure 4: Figure 5: Figure 6: Figure 7: Figure 8: Figure 9: Figure 10: Example Application circuit of the Embodied Devices. Partitioning of the Top Level AEMS SoC [300] Embodiment. Part 1 of CSMPPTBC [100] PMMIC System Functional-Diagram. Part 2 of CSMPPTBC [100] PMMIC System Functional-Diagram. STCSnRreg [200] PMMIC System Functional-Diagram.

ZBCSBC [14] System Diagram and off-chip Support Circuit. Active Rectifier [16] System Diagram and Support Circuit. RxPwrIrk [18] and SLPA [122] Concept Functional-Diagram. MPPTnHref [17] and SLPA [122] Concept Functional-Diagram. SICSnRreg [200] Ott-Chip -HV and +HV Support Options.

TOP-LEVEL DESCRIPTION OF THE ENERGY MANAGEMENT SYSTEM: With reference to Figure 1: The 5DC2021 CSMPPTBC [100] can service multiple solid-state P-N Junction Energy Harvesters [01] such as Photo-Electric Generators (PEGs) with Solar-cells being an example and/or Thermo-Electric Generators (TEGs) of which Seebeck-cells are one example. Frequently PEGs and TEGs are used together in systems of greater than one sun to capitalise on the increase in efficiency that can be won at high input levels to the PEG as well as reusing its heat by sandwiching a TEG between it and a heatsink.

The CSMPPTBC [100] can service RE Rectennae [29] such as those used in WLAN systems. The rectenna output can be connected in parallel with the PEG and TEG arrays then into the same input. Multiple CSMPPTBC [100] may be applied in parallel to drive a Common DC Power Buss [307] for increased output power. WLAN RE energy scavenging sets the minimum sensitivity for our system and we can calculate that by considering a IW point-source at 2.5GHz will illuminate the inside of a 1m radius sphere with just under 8uW/cmp2. The antenna aperture of a 2.5Gz patch antenna is approximately 4cmf2 and zero-bias RE-diodes are 30% efficient when well matched, so we see that delivering 3uW into our AEMS SoC at 2m might be an optimistic expectation from a physically small end-product. However, something the size of a computer mouse might prove practical.

The 5DC2022 SICSnRreg [200] may be applied as a sLand-alone auLonomous PMMIC to receive power from multiple CSMPPTBC [100] PMMICs by accepting excess energy above that consumed by the load [09] from the Common DC Power Buss [307]. Multiple SICSnRreg [200] units can source stored energy back into that same DC Power Buss [307] to service one to many load [09] devices.

The SICSnRreg [200] may be applied in parallel with other SICSnRreg [200] devices to support a higher power output capability with respect to a single SICSnRreg [200] unit. Similarly, the 5DC2023 AEMS SoC [300] may be used singularly or in concert with each other and/or each of the SDC2021 and SDC2022 as appropriate to their host application requirements.

Autonomous Ambient Energy Management System DESCRIPTION (continued) Both the 5DC2022 SICSnRreg [200] PMMIC and the 5DC2023 [300] ARMS SoC can service Dielectric Elastomer Generators (DEG) via their Cstore [13] port as presented in Figure 1 where Cstore [13] has been replaced by a DEG [28] which is a flexible solid-state harvester, along with a standard DEG self-priming circuit [60] (see Figure 5 in Reference 1) which takes over from the AEMS SoC once the DEC's energy source starts walking.

In this application the DEC functions as the energy storage element for both energy from the TEG and from the DEC itself. The AEMS SoC predominantly recovers that energy from the DEC and returns it to the Vdd Buss after providing the initial priming charge to the DEC. With the addition of an 5D2022 SICSnRreg [200] to the Vdd Buss and provided the load is removed or minimized, this hybrid system may be used for recharging small Li-Cell batteries on very, very long walks.

A typical "Heel-Strike" DEC of 10nE integrated into a shoe can deliver about 200uW with the basic AEMS SoC at walking speed and around 10nW with an external set of 2.5kV MOSFETs fitted to the PMOS drive port [320, 322] and the MMOS drive port [315, 317] along with a suitably rated NV Flying Inductor [12] isolation capacitors [26, 27] and NV diodes in the DEC self-priming multiplier. All need to be suitably rated and insulated for safety.

We noted that bulk energy storage is an issue for small-scale environmental energy harvesters as the energy harvested is of a similar magnitude to the losses in typical long-term storage cells. The solution is to "right-size" the storage capability against loss over time, where "time" is the period of energy black-out rather than shelf-life for a primary cell or Charge Capacity and its leakage time for a secondary cell.

The SDC2022 SICSnRreg [200] addresses this by isolating a fully charged or fully depleted storage cell to isolate the energy sink presented by those respective storage elements from the Common Vdc Buss. This ensures that multiple cells can work Independently whilst operating in parallel to each other. If the Vdd Over-Voltage and Under-Voltage trip-points on individual 5002022 PMMICs are selected to set the trigger-points for a bulk store such as a super-cap or lithium cell to accumulate at a higher voltage than the long-life dielectric store, then return to bulk-store depletion at a higher voltage for the long-life store depletion, the different switch-in and cutout levels enables two or more 5DC2022 units to operate in parallel with disparate storage cells such that their change-over becomes autonomous. For this storage strategy to function, both store types need to isolate themselves from the Common Vdd Buss when they have become either fully charged or entirely depleted.

With reference to Figures 2 to 5 in the DRAWINGS: we present the top-level partitioning of the two base Power Management Monolithic Integrated Circuilus [100] and [200] being minimum examples in which our inyeniciun musl. be embodied to be integrated as pac of the larger System-on-Chip PMMIC [300] as in Figure 2.

We see that the AEMS SoC [300] consists of 12 functional blocks numbered from 14, 15, 16 17, 18 and 19 for the [100] section and 20, 21, 22, 23, 24 and 25 for the [200] section. These PMMICs are necessary frameworks within which the circuits we claim can function. Many functional blocks and sub-cells comprise cells from pre-existing bespoke libraries of IF cells such as comparators, operational-amplifiers, oscillators, voltage-references, current-references mono-stables, Flip-flops or logic gates.

Autonomous Ambient Energy Management System DESCRIPTION (continued) However, some of the functional blocks such as 14, 15, 16, 17 and 20 have been developed specifically for the Ambient Energy Management System SoC itself. These five functional blocks or IF cells contain the Intellectual Property we wish to protect and will be described after the framework and its interconnections have been described in detail.

When partitioned into the two subset PMMICs the first PMMIC [100] manages the energy harvesting sources and applies the Zero-Bias Cold-Start circuit then outputs that energy to the designated load [09]. The second PMMIC [200] can sense when the first PMMIC [100] is delivering more energy than is required by the load [09] and can regulate the load voltage by sinking that excess power into an external storage facility. The second PMMIC [200] can also sense when the first [100] is delivering insufficient energy to the load [09] and can source that stored energy back into the load to maintain the load voltage and output power level.

Next, we trace through Figures 3, 4 and 5 to define connectivity between the IP cells and their host functional blocks within each PMMIC.

DETAILED DESCRIPTION OF THE AMBIENT ENERGY MANAGEMENT SYSTEM: Figures 3 and 4 show the functional blocks for the SDC2021 CSMPPTBC or Cold-Start Maximum Power-Point Track-and-Hold Boost Converter PMMIC numbered [100] which holds four key IP cells: the Zero-Bias Cold-Start Boost Converter IP cell [14] the Maximum Poer-Point Real-Time Tracking Boost Converter [15] which contains the linearised Fixed Pulse-Width Variable Position Modulator circuit, the Active Rectifier IP cell [16] which contains the Commutation-Driven Active Rectifier trigger circuit and the Receive Power Tracking cell [10] which holds the Frequency Deviation Detector circuit and shares the Source Load-pull Analyser construct with the Maximum Power Point Track and Hold Reference cell [17] all of which are described as follows: The first functional block is the Zero-Bias Cold-Start Boost-Converter [14] of Figure 3 which by definition must be both oscillatory and impedance converting to change the input DC energy into AC energy then chrough a low to high impedance match lift its working voltage level sufficiently to deliver an increased DC level to its output once the requisite AC to DC conversion takes place. This stage, the ZBCSBC [14] has to be able to deliver sufficient charge to the DC filter capacitor [05] on the Vdc line [302] to reach operative levels in a reasonable time.

We return to [14] the Zero-Bias Cold-Start Boost-Converter in the PREFERRED ENBODIEMENT section to further describe its underlying connectivity and function as revealed in Figure 6 being the subject of Claim 6.

The First Comparator cell [102] to the lower left of the CNTRI, block [19] in Figure 3, senses the Vdc output [302] from the ZBCS core [101] within the ZBCSBC block [14] then rases the CFen line [131] enabling a Secondary Oscillator [103] which drives a negative voltage rectifier [104] and the said external filter capacitor Cneg [06]. The ZBCS core [101] De-bias Switch [106] controlled by the First Comparator [102] via a Level Shifting Network [105] puts the ZBCS core [101] into its low-power state. The ZBCSBC block [14] is a key part of our patent and performs the most vital function within the whole Ambient Energy Management System by ensuring it recovers in a robust way every time from a fully discharged state.

Autonomous Ambient Energy Management System DESCRIPTION (continued) The second functional block is the Maximum Power-Point Real-Time Tracking Boost-Converter [15] in the upper part of Figure 4 which is enabled by the First Comparator [102] via the CFen line at the same time the ZBCSBC Block [14] is powered down by the said CFen line [131]. The MRRRETBC [15] contains a Second Comparator [107] a First Monostable [108] an NMOS Switch Driver Stage [109] an Inductor Switching NMOS Device [110] with a reverse polarity Avalanche Diode [111] across the NMOS Device [110] drain-source.

We explain the use of the Fixed Pulse-Width Variable Position Modulator within the Maximum Power-Point Rear-Time Tracking Boost-Converter [15] in the following PREFERRED ENBODIEMENT section to further describe its underlying connectivity and function as revealed in the lower part of Figure 7 being one of our key IP cells and the subject of Claim 7.

The third functional block is the PMOS Active Rectifier stage [16] at the top of Figure 3 which serves the MPPRTTBC [15] block only and behaves as a near perfect ideal diode. The device that does the rectification is a P-channel MOSFET [117] which has an Inverse Body Diode [112] across its source to drain nodes. The anode of the PMOS Inverse Body Diode is connected to the drain labelled as the Vflyl [305] node connecting to an external Flyback Inductor [04]. The cathode of the Inverse Body Diode [112] is connected to the Vdc node [302] into the Vdc filter Capacitor [05]. The Inverse Diode [112] then limits Vflyl [305] to Vdc plus one diode drop.

If the Primary Booster's Switch device [110] in the upper right of Figure 4 is rapidly switched off, then the Vflyl [305] node on [110]'s Drain commutes as the Inductor current looks for a path to continue to flow through. This current forces Vflyl [305] to rise until the PMOS inverse diode [112] of Figure 3 conducts. This overshoot of Vdc trips the third Comparator [116] which has its input connected across the PMOS's Inverse Drain-Source diode [112] and clocks the PMOS control Flip-flop [113] on. This activates the PMOS actives rectifier device [117] channel conduction which pulls the voltage across [117] and its inverse Body Diode [112] down to a few mV above Vdc [302] and diverts the Inductor [04] current through the PMOS [117] device's channel instead of the inverse Body Diode [112].

As the channel of the PMOS [117] is only limited by the current through it and its own channel resistance, its conductivity is much larger than that of the Inverse Body Diode [112] which is limited by its own intrinsic bandgap voltage. The power loss through the Active Rectifier device [117] will therefore, be much less than through a similar rated Schottky diode.

The Active Rectifier [16] functional block is reset by the first Amplifier [114] and the following Fourth Comparator [115] when that comparator detects the zero-current cross-over voltage on the Inductor Current-Sensing ResisLor [03], swiLeEing Lhe AcLiye RecLifier off by reseLLing Lhe FirsL Flip-Flop [113].

We return to [16] the Active Rectifier device and the use of its Inverse Body Diode to self-trigger the Active Rectifier's control circuitry in the following PREFERRED ENEODIEMENE section to further describe its underlying connectivity and function as revealed in the upper part of Figure 7 being one of our key IP cells and the subject of Claim 8 and Claim 9.

Autonomous Ambient Energy Management System DESCRIPTION (continued) The fourth functional block is the Maximum Power Point Track and Hold Reference [17] in the lower part of Figure 4. This block plus its functionally previous one, the Receive Power Track [18] functional block to the right of [17] in Figure 4 replaces the external reference [07] and provides an internal sampled reference voltage stored on the Cref capacitor [08] being the reference-hold device.

The second Comparator [107] in the upper-left part of Figure 4 within the MPPRTTBC block [15] is driven by the reference input Vref [304] which when derived from one element 1071 of the Energy Harvester input array 1011 of Figure 3 will make the simplest fast-tracking Maximum Power-Point Tracking System available to us as it avoids the power-loss and electrical delay associated with the extra functional blocks in the following active in-channel MPPTnH system described next. However, in applications where it is inconvenient to sacrifice one element of the harvester array, or we only have one harvester in the input array, we then need an in-channel capability. Similarly, if we are to mix the input harvester array types then in-channel sampling is our only option. It also minimises the influence of shadows across the array and avoids the potential blocking of a single reference cell.

The fifth functional block the Receive Power Track [18] and the above fourth functional block [17] work in parallel: the MPPTnHref [17] monitors the Vpd input [301] voltage whereas the fifth block the RxPwrTrk [18] block monitors the frequency of the MPPRTTBC [15] block internally through the SWdrv [127] node. When the fifth functional block the RxBwrTrk [18] detects a change in frequency it outputs a SMPL [125] Flag to the Source Load-Pull Analyser [122] SLPA circuit. The SLPA activates the two switches [110] and [119]. This switches in a resistive divider across the Vpd input [301].

The divider charges the external Cref [03] to the value set by that resistive divider, providing sufficient time is allowed for any transient on the Vpd [301] line to decay. When the SPLA [122] detects that the dVdt on Vpd [301] has settled to near zero, it de-asserts the BLNH [123] node opening the resistive divider leaving 0.693x the value of Vpd [301] on the Vref [08] node.

The BLNK node [123] from the SPLA [1221 also cuts off the second Comparator [107] blanking out the MPPRTTBC [15] block's switching activity. This allows the voltage on the PMMIC's Vpd input [301] from the primary Energy Harvester [01] to settle to near the harvester's open-circuit output voltage provided all other energy sinks from the Vpb [304] input have been neutralised.

However, because we are dealing with environmental effects including host movement which for photoelectric generators and data carrying RE WIAN systems may be orders of magnitude of change if the energy sources are mobile wiLli respect IQ Ihe harvesIing arrays, or conversely eleeIrieally drifting slowly as in the case of a high latitude sunrise we have to deal with very large and very small changes in input energy equally well.

The MPPRTTBC [15] P422TnHref [17] and the Rx2wrIrk [18] functional blocks form a feedforward and feedback dual-handshake loop making up a significant part of this work which we will return to in the following PREFERRED ENBODIEMENT section to further describe their combined function and underlying connectivity centred on the Frequency Deviation Detection System of Figure 8 being one of our key IP cells and the subject of Claim 10.

S

Autonomous Ambient Energy Management System DESCRIPTION (continued) The Track and Hold Reference Sampler and its hand-shake with the Reference Hold of Figures 8 and 9 is an encompassing key IS cell and the subject of Claim 11.

The Replica Input Filter of Figure 9 is a dependent key IF cell and the subject of Claim 12.

The Source Load-Pull Analyser described by Figures 7, 8 and 9 is a dependent key IF cell and the subject of Claim 13.

The sixth and last functional block of the SDC2021 [100] is the CNRTL [19] functional block to the lower-right of Figure 3 and right of Figure 4. Once the Vdc line [302] in the CNTL [19] block goes above Refdd feeding the negative input to the Fifth Comparator [128] of Figure 3 the Vdc [302] to Vdd [307] PMOS Device [129] switches on then sets an internal to PwrOK [130] counter running. Once the PwrOK counter times-out the PwrOK [130] cell raises the PwrOK flag [308] to inform an external application load [09] that Vdd [307] power is now "OK to use".

The primary function of the fifth comparator [128] and its slave PMOS device [129] is to isolate the load in the event of a load fault such as an overload or short-circuit occurs. They isolate Vdc [302] from Vdd [307] and preserves the internal operation of the RMMIC for the period that Cdc [05] can hold up for as set by internal leakage. This feature is important as it avoids the delay in waiting for the system to completely deplete then rely on the ZBCSBC [14] to restart the CSMPPTBC [100] which then repletes the whole system at the next energy input event.

The 8Hz sub-cell [126] in Figure 4 at the lower part of the CNTRL [19] functional block generates an 8Hz clock output [309] for the external load [09] timing and/or synchronisation use. The 8Hz clock [309] is derived from the 32Hz oscillator [103] within the ZBCSBC [14] functional block at the lower part of Figure 3.

Autonomous Ambient Energy Management System DESCRIPTION (continued) The second part of our System-on-Chip [300] is the SDC2022 SICSnRreg or Single-Inductor Charge-Storage and Recovery Regulator numbered [200] and is presented in Figure 5. Numbering for the 5DC2022 [200] block continues from block six of the SDC2021 [100] and similarly migrates through the SDC2023 AEMS SoC [300].

The SICSnRreg [200] of Figure 5 functions as the interface between the Energy Harvester PMMIC [100] and the external Energy Storage [13] (or an alternate Dielectric Elastomer Generator [28] of Figure 1) and is labelled Cstore throughout the DRAWINGS section. Odd [10] is the Common Vdd Buss [307] filter capacitor that supplies the load [09] and behaves as the energy reservoir into and out of the SICSnRreg [200] and AEMS SoC [300] instances of Figure 1.

The seventh functional block for the SDC2023 [300] or first functional block for the 5DC2022 [200] is the SW-AP Directional Multiplexer [20] to left part of Figure 5. The seventh functional block [20] and twelfth functional block [23] form the body of Claim 14 where we claim the use of a Bidirectional Drive to time-share a single inductor terminated by a dual switch/active-rectifier construct. As the intervening blocks [21] and [24], [22] and [25] are necessary support blocks we trace through their inter-connectivity with blocks [20], [23] and their combined function as follows: Internally, Resistors [201] and [202] bring Vdd [307] within the common-mode range of the window-comparator formed by the sixth Comparator [203] and seventh Comparator [204]. When the divided-down Vdd goes above the +Ref node of the upper sixth Comparator [203] the SDC2022 SICSnRreg PMMIC [200] or SDC2023 AIMS Soc [300] would enter its energy storage or accumulation mode. When the divided-down Vdd goes below the -Ref node of the lower seventh Comparator [204] the 5DC2022 SICSnRreg PMMIC [200] or SDC2023 AIMS Soc [300] would enter its energy recovery or Cstore [13] depletion mode.

The output of the sixth Comparator [203] triggers the second Monostable [205] when the Comparator's output goes high. The Q output of the second Monostable [205] bypasses the upper fourth Flip-Flop [207] to drive the SWp input to the upper second OR gate [209] which drives the seventh functional block the PMOS Drive [21]. However, the nQ output of the second Monostable [205] drives the lower fifth Flip-Flop [208] rising-edge clock input when the second Monostable [205] times out or gets reset by the sixth Comparator [203] going low.

Similarly, the output of the seventh Comparator [204] triggers the third Monostable [206] when the Comparator's output goes high. The Q output of the third Monostable [206] bypasses the lower fifth Flip-Flop [208] to drive the SWn input to the lower third OR gate [210] which drives the eighth functional block the NMOS Drive [22]. however, the nQ output of the fifth Monostable [206] drives the upper fourth Flip-Flop [207] rising edge clock input when the third Monostable [206] times out or gets reset by the seventh Comparator [204] going low.

The eighth functional block the PMOS Drive block [21] drives the ninth functional block the PMOS SW+AR [24] during Cstore [13] accumulation and HV Flyback Inductor [12] positive current ramp-up when the PMOS output device [215] functions as the positive going inductor switch.

Autonomous Ambient Energy Management System DESCRIPTION (continued) The PMOS Drive block [21] also drives the PMOS SW+AR [24] block during the Cdd [10] recharge and Load [09] drive phase during HV Flyback Inductor [12] positive current ramp-down where the PMOS output device [215] functions as the positive going active rectifier.

The tenth functional block the NMOS Drive block [22] drives the eleventh functional block NMOS AR SW [25] during Cstore [13] accumulation and HV Flyback Inductor [12] negative absolute current ramp-down when the NMOS output device [220] functions as the negative going Active Rectifier.

Also, the NMOS Drive block [22] drives the NMOS ARMSW [25] during odd [10] recharge and Load [09] drive phase during HV Flyback Inductor [12] negative absolute current ramp-up where the NMOS output device [220] functions as the negative going inductor switch.

The upper monostable [205] sets up the maximum conduction time for the PMOS output device [215]. The lower monostable [206] sets up the maximum conduction time for the -HV NMOS output device [220]. These two set the maximum charge currents for the Flyback Inductor [12] in the positive direction for the upper monostable [205] and the negative direction for the lower monostable [206].

As the two supply voltages Vdd and Vstore are vastly different, maximum on times for both mono-stables are proportionally different during their inductor-charge phase or inductor discharge phase and may be used to determine the ratio of the two voltages making a non-intervention method for determining the Vstore value possible. Based on that knowledge a calculation of external store capacitance Cstore [13] stored-charge may also be made.

Both the sixth and seventh comparators have internal hysteresis such that when the falling edge of their outputs are used to reset each monostable the ripple on the Vdd line [307] controls the Inductor charging pulse width of the PMOS in Accumulation mode inductor charging. The NMOS pulse width remains substantially fixed so its frequency or rate of switching changes during Vstore depletion mode.

The twelfth and last functional block for the SD02022 [200] and the SDC2023 [300] being the Isns2 Trip-Point Detect [23] functional block monitors the state of the Rsns2 Resistor [11]. Rsns2 [11] scales both the accumulation and depletion currents through the HV flyback Inductor [12]. During Cstore [13] accumulation the inductor current is positive into Isns2 [12] from node [313] such that the voltage on Isns2, node [312] goes positive. The voltage difference between the Isns2 node [302] and the GND2 line [310] is amplified by Lhe second amplifier A2 [221] and Lhizd amplifez AS [223]. The use of these amplifiers lowers the I°2R loss due to the sensing resistor [11]. The gain of A2 is positive whereas A3 is inverted such that A2 output --A3 ountput. The voltage equivalent for the positive Accumulation current through Rsns2 [11] is presented to the eighth comparator [222]. The inversion in AS separates the inductor current measurement for Cstore [13] when in Depletion then presents its voltage equivalent to the ninth comparator [224]. Both comparators detect their mapped current's zero-crossing point, then trigger their respective Active Rectifier controlling Flip-flops [207] and [208] in Vstore accumulation then Vstore depletion mode.

Autonomous Ambient Energy Management System DESCRIPTION (continued) Whilst the lower Flip-Flop [208] sets the NMOS [220] on period during the Inductor fly-back period for Vstore Accumulation, the Isns2 [312] negative current zero-crossing detected by the ninth Comparator [224) resets that lower Flip-flop [200] turning the NMOS "Active Rectifier" [220] off.

Similarly, whilst the upper Flip-Flop. [207] sets the PMOS [215] on period during the Inductor fly-back period for Vstore Depletion, the Isns2 [312] positive current zero-crossing detected by the eighth comparator [222] resets the upper flip-flop [207] turning the PMOS "Active RecTifier" [215] oft.

Thus, the upper PMOS output device is used for the flying-inductor charge-phase of Cstore accumulation whilst the lower NMOS is used as an Active Rectifier. The roles of the MOS devices swap over for Cstore depletion where the lower NMOS device charges the inductor negatively, depleting Cstore and the PMOS is re-used as the Active Rectifier to charge Cdd.

In effect the two MOS devices [215] and [220] each behave as a multiplexed hi-directional switch: the PMOS variant at the low-voltage end of the inductor's output range whereas the NMOS variant is at the high-voltage end of the inductor's output range as drawn in Figure 5. The sense of these can be swapped over for a positive going HV output and we deal with this further in the PREFERRED EMBODIEMENT section of this DISCUSSION.

The inverted PMOS Drive [211] is passed off-chip by the PMOS Drive [21] block's negative output [322] across the host PCB then back into the PMOS SW-AR [24] block's negative input [323] to the Main PMOS output device's gate resistor [213] then into the PMOS output device [215] itself as drawn in Figure 5. This connection could be via an isolation capacitor. This capability enables external higher voltage PMOS devices to be used in place of the whole PMOS SW-AR [24] functional block. The PMOS Drive [21] block's positive drive [320] is also passed off-chip via the host PCB then back on-chip through the PMOS SW-AR [24] block's positive input [3211 directly into the PMOS output device's gate clamping PMOS [214] to clamp the PMOS Output Device [215] gate hard off to Vdd [337] to minimise sub-threshold leakage in the main PMOS switch device [215]. If the PCB link across [320] to [321] is also capacitively coupled then a baseline restoration diode [225] must be added across [321] to [307] with its anode to [321] to stabilise the PMOS output device's gate clamping PMOS [214] device's gate node [321].

Similarly, the NMOS drive from the lower third OR gate [210] is taken off-chip as the NMOS Drive [22] functional block's positive output [315] is DC isolated via a capacitor [26] then back on-chip through the NMOS AR-SW [316] block's positive input [316] into a gate stabilisation Resistor [216] into the gate of the output NMOS switch [220] device's gate. The inverted NMOS drive [212] is also taken off-chip at [317] DC isolated by a capacitor [27] ihen back on-chip [318] inIo an NMOS clamp device [218] Lc clamp ihe ouipui NMOS [218] device's gate to Vstore to minimise sub-threshold leakage in the NMOS output device [220]. Two DC restoration diodes [217] and [210] ensure the NMOS devices switch on and off correctly under variable duty-cycles.

The seventh functional block [20] through to the twelfth block [23] form the body of Claim 14 where we claim the use of a Bidirectional Drive to time-share a single inductor terminated by a dual switch/active-rectifier construct. We examine the use of external higher than PMMIC implementation process voltage maximum HV supplies both positive and negative going in the PREFERRED EMBODIEMENT section and claim these as part of Claim 14.

Autonomous Ambient Energy Management System DESCRIPTION -PREFERRED EMBODIMENTS Here we give further detail for the Intellectual Property Cells numbered 14, 15, 16, 16 and 17 of the SDC2021 [100] along with the two off-chip replacement cells for the functional blocks 24 and 25 from Figure 2. These five IF( cells were specifically developed for the AEMS SoC [300] and can he found in the two contributing PMMICs being the MPPTnHBC [100] and SICSnRreg [200] as well.

[14] The ZBCSBC or Zero-Bias Cold-Start Boost-Converter of Figure 6 operates when the system has totally depleted and is emerging from a zero-available energy state. To overcome initial sub-threshold start-up issues when implemented on-chip an "always-on" or zero-biased device such as a native NMOS or depletion mode Field-Effect Transistor is used. For our purposes we need a device with as near to zero-threshold as possible to ensure that electrical activity between the controlling node and the controlled nodes of the Zero-Biased device occurs as soon as minute amounts of energy are present. The initial configuration investigated was a modified Vakar oscillator presented in the top circuit of Figure 6. Conveniently we can re-use the feedback Pi-Network's output L2 inductor [35] as the flyback inductor in the MPPRTTBC [15] provided the ZBCSBC's resonant tank [34, 32,35] runs at a sufficiently high-frequency to minimise the loading on the VFLY1 node [305] by the Pi-network's series capacitor Cl [32]. This permits a two-inductor design for the SDC2021 CSMPPTBC [100] PMMIC and a three-inductor design for the SDC2023 AEMS [300] SoC.

The second ZBCSBC option, a Hartley oscillator, mandates the use of an extra separate inductor L3 [36] in the middle circuit of Figure 6 due to the need for a large inductor Li [34] in the Hartley oscillator when used as a two-inductor 5DC2021 [100] design. At minimum input the ZBCSBC [14] of the three-inductor 5DC2021 [100] design reaches a stable output much quicker than the two-inductor variant does. The C2 capacitor [33] provides AC coupling and the necessary DC isolation for the input of the -gm [400] cell to enable the zero-bias cut-off switch [106] to de-bias the zero-bias transconductance stage [400] when the primary MPPRTTBC [15] starts up to remove the DC load the transconductance stage would place on the input array [01] via L2 [35] if the zero-bias cold-start core [101] (of Figure 3) was left active.

The core transconductance represented by -gm [400] of the upper two circuits of Figure 6 is revealed in the lower construct of Figure 6 which consist of a depletion mode or zero-bias MOSFET [401] with an enhancement mode standard threshold MOSFET [402]. Initially the oscillator core functions on the depletion-mode device until the AC level at the Vac node [324] builds to a level that the base-line restoration diode [404] conducts and creates a positive going AC waveform on the gate of the enhancement mode device. The gate coupling capacitor [403] provides DC isolation and srores 'she DC charge as the oseillarion level builds. Once the peak of rile gate waveform exceeds the threshold of the enhancement mode device [402] that device conducts and due to its much larger transconductance than the depletion mode device, takes over providing the switched energy to the DRV2 [325] node. The efficiency of the construct goes from a few percent when the depletion mode device [401] dominates to a few tens of percent when the enhancement mode device [402] dominates due to the operating mode of each device: at low resonant levels the construct operates in Class A then progressively this moves to Class AB then Class E as the resonant voltage builds.

Autonomous Ambient Energy Management System DESCRIPTION -PREFERRED EMBODIMENTS (continued) As we need to charge the external Cdc [05] capacitor with the ZBCSBC [14] output to initiate primary converter start-up as soon as we can, we need to place the whole ZBCS core [101] of Figure 3 into its most efficient mode as soon as we can, that is: class-E, as fast as possible and it is for this purpose that we add the AC-DC switch device [405] to the right of the top schematic in Figure 6 and the load switch device [409] to the right of that same schematic.

To minimise the forward-voltage drop of the AC to DC conversion diodes [406] and [407] these devices will probably be low-threshold MOS, Schottky or zero-bias square law devices which have significant reverse bias leakage. This can consume a large port of the harvested input when the devices are non-conducting so the AC-DC switch device [405] is added to stand-off leakage when the AC-DC converter is inactive. When in Class-E the compound zero-bias transconductance stage [400] needs to see a stabilised drive waveform to remain in its Class-E operating mode. This stabilisation is provided by the load switch device [409] as its source node [326] functions as a virtual ground at one threshold voltage above its gate -that is: above GND [310]. The drain node of the load switch device [409] behaves as a current source up until the Vdc node [305] almost reaches the Vstup [326] node voltage at which point the Vdc [305] node tracks the Vstup [326] node. When Vdc [305] is powered externally and the ZBCS core [101] has powered down the load switch will reverse bias as standard PMOS devices are reciprocal -their drains and source nodes are interchangeable, so the ZBCS core relies on the de-biasing switch [106] the coupling capacitor [403] the gate junction of the depletion device [401] and the external tank C2 coupling capacitor [33] to be very low leakage to preserve the charge on Vdc during periods of inactivity. To optimise the Class-A to Class-E idle-up of the ZBCS core the point at which the AC-DC converter switches on and when the Vstup [326] node begins to feed charge into the Vdc [305] node, the characteristics of the enhancement mode MOSFET [402] the AC-DC switch device [405] and the load switch device [409] should all track each other.

We claim the function and behaviour of the whole ZBCSBC [14] along with both the Vakar external circuit [33, 34, 32, 35, 401, 402, 403, 404, 405, 406, 407, 408, 37, 409, 106 and 06] and its Hartley variant with [33, 32, 34, 35 and 36] in Claim 6.

[15] The MPPRTTBC or Maximum Power-Point Real-Time Tracking Boost-Converter of Figure 7 presents the use of a Fixed Pulse-Width Variable-Frequency Modulator within the MPPRTTBC to linearise the switch-rate versus input power of the MPPRTTBC [15].

The core of the MPPRTTBC is a comparator-based relaxation sawtooth osoillaror comprising rile second cempararor [107] tile indueror's NMOS switch [110] the inductor itself [04] the inductor's current sensing resistor [03] the harvester's integration capacitor [02] and ehe harvester itself [01]. The solid-state harvesters we have targeted can be modelled as a current source, so the base switch rate is set by the integration period of the harvester's output current, the integration period of Cpd between the comparator's switch points. The inductor and the current-sense resistor behave to a first approximation as a short circuit. The comparator [107] toggles high when its input [301] rises above its reference input [304].

Autonomous Ambient Energy Management System DESCRIPTION -PREFERRED EMBODIMENTS (continued) This triggers the oscillator's output switch [110] which draws current through the primary inductor L3 [04] of Figure 7 or Lflyl of Figure 3. As the current through the inductor rises, this pulls current out of the input filter capacitor Cpd [02] which discharges through that inductor and switch device until the comparator's input reaches (in its simplest form) the comparator's lower threshold. Generally, there is a level of hysteresis between the comparator's positive and negative inputs which sets up the basic frequency of oscillation.

The sawtooth voltage on the input capacitor has a slower rising edge due to the input array [01] current charging the input integration capacitor [02] and a faster falling edge due to the much large current flowing through the inductor [04] and switch [110]. The upper and lower points of inflection are set by the reference input [304] and upper and lower hysteresis trip points in comparator [107]'s input. The difference in the voltage of these points of inflection along with the integrated input current and the input integration capacitor [021's value set the frequency of oscillation.

Whilst being simple, this type of sawtooth relaxation oscillator has the disadvantage that when being used over the very large range of frequency needed to service typical indoor to outdoor light levels that photoelectric harvesters experience being in excess of three orders of magnitude, the sawtooth oscillators control input to output transfer-function becomes nonlinear to the point of being non-monotonic for some input levels and devices. Any non-monotonicity of the transfer function makes the application of an active or synchronous rectifier system, difficult at best.

One solution for linearising this transfer-function is to insert a fixed period monostable into the comparator, switch device, Inductor, integration capacitor loop. This sets the L3 inductor [04] current to a fixed period no matter what the dynamics of the input port Vpd [301] is. Therefore, the integration capacitor [02] the inductor [04] and the power flow from the input array [01] to a second order, now set the frequency of the oscillator as the upper point of inflection is now set by the refence input [304] with the lower point of inflection being set by the Ipk(L3)/dt on the integration capacitor where Ipk is set by the Inductor and the final capacitor voltage. Now we can tune dt to suit the inductance of L3 [04] and the energy source's averaged output power. The final circuit now functions as a fixed-pulse-width, variable pulse position modulator which changes frequency when the reference voltage is varied. That is: our modification has altered the whole construct to become a Voltage Controlled Oscillator or VCO. A typical switching-frequency versus input power to the array [01] plot looks linear to a few percent if plotted on a log-log graph but more importantly it is now monotonic over at least the three orders of magnitude we need for a working system as this enables both a simple active-rectifier construct of Claim 8, the Flyback Inductor zero-current deIection conzlemm82 of Claim 9 as well as lineaiising our inpuI-power tracking frequency deviation system of Claim 10.

Autonomous Ambient Energy Management System DESCRIPTION -PREFERRED EMBODIMENTS (continued) [16] The Active Rectifier in the upper section of Figure 7 starts with the primary inductor [04] current sensing resistor Rsns [03] where the Isns node [306] is pulled below Vpd [301] tripping the third comparator [116] whose rising edge resets the already quiescent first Flip-Flop [113] in the upper-right of Figure 7. This ensures that the Active-Rectifier device [117] is off at start-up. The Active Rectifier [117] control is passive during the Inductor-Switch device [110] conduction period which is the CV to Ipk.RDS(ON) period at the bottom of the lower plot in Figure 7 where the NMOS switch device [110] is conducting and the voltage across that device rises by an amount determined by the inductor current and the channel resistance of the Switch device [110] itself. Once The sawtooth oscillator's monostable times-out and switches the Inductor-Switch [110] off, the Active-Rectifier's control system becomes active when Vflyl [305] node commutes then over-shoots Vdc [302] and forward biases the upper PMOS Active Rectifier [117] inverse diode [112] and switches the current mirror output device [411] on.

The current mirror output device [411] raises the voltage on resistor [412] and drives the clock input to the first Flip-Flop [113] high via the dual inverter buffer [413]. This activates the PMOS Active-Rectifier [117]. A short period where the overshoot current flows through the inverse body diode [112] results in a short Voltage transient of one Diode drop as shown in the plot at the bottom of Figure 7. Once the Active Rectifier device conducts the overshoot voltage is pulled down to the remnant source to drain voltage due to the PMOS channel resistance whilst in conduction.

When the L3 Inductor [04] current crosses zero the output of the third comparator [116] falls and that falling edge resets the Active Rectifier's control Flip-Flop [113] turning the Active-Rectifier Device [117] off. Any residual energy in the system due to capacitive strays resonating with the main inductor gets snubbed during the second voltage peak as the Active Rectifier switches off. This double-horned impulse is a common response from Active Rectifier circuits.

We claim the use of a MOS body Diode configured as a current mirror to detect the Inductor commutation and its use to initiate the conduction of the MOS channel along with the detection of the inductor's zero-crossing to terminate the Channel conduction in Claim 8 and Claim 9.

[18] The RxPwrTrk or Receive Power Track of Figure 8 tracks the input power to the MPPRTTBC [15] by detecting any change in the switch rate of that converter. The Frequency Deviation Detection System to the left of Figure 8 is based on the measurement of the derivative of a dual phase envelope depimalor.

The principle of operation is to set up a reference dV/dt that is reset at the MPPRTTBC switch-rate. If the ramp's reset rate changes then the point of inflection at the ramp's tip changes level due the change in its timing on the constant slope of the ramp between the reset to zero points due to the ramp-s reset changing position in time -that is, it a level change is detected then the input frequency must have changed.

Autonomous Ambient Energy Management System DESCRIPTION -PREFERRED EMBODIMENTS (continued) To detect such a change in level a dual-phase clock is derived from a divide two stage driven by the SWdry input [127] from the MPPRTTBC [15] and is used by a dual sampler to alternately sample the ramp. In effect, we compare the present sample with its previous sample. If the input frequency remains stable the output envelope is also stable. If the input changes frequency, then the output envelope alters up or down in sympathy with the change in input period. To detect any the change in that envelope we pick off its derivative through a capacitor then pass the resultant impulses through a window comparator to detect the presence or absence of an upward or downward pulse train caused by any change in the input frequency. The span of frequency detection is about 30:1 which is insufficient to cover the whole range of MPPRTBC operation, so we implement two instances of the RxPwrTrk system in parallel running with different ramp dV/dt rates to cover the 450:1 range needed to service the full switch rate range of the MPPRTTBC [15].

The SWdry node [127] on the left of Figure 8 derived from the MPPRTTBC [151 functional block drives the RxPwrTrk [18] functional block via the ramp reset switch [134]. This resets the ramp capacitor [135] to zero which is charged at a fixed rate by the resistor [133]. Althogh drawn as a resistor for convenience, on-chip this ramp pull-up resistor [133] might be replaced by a dedicated current source to improve the linearity of the frequency deviation sensitivity across its frequency range. The dual-phase clock is generated by the divide two formed by the second Flip-Flop [L36] which is also driven from the SWdrc input [127]. This second Flip-Flop's Q output drives the first sampler [137] and die Flip-Flop's nQ output drives the second sampler [143]. The two hold capacitors [138] and [142] are smaller than the ramp cap to minimise switching errors disturbing the ramp's dV/dt.

The charge held on each of the two hold capacitors [130] and [142] from each of their first periods is passed to a third hold cap [148] that integrates any differences in the charge held by the first and second hold capacitors as they are switched into and out of circuit. This generates a signature envelope for the incoming SWdrv [127] frequency. The other end of the envelope integrate-and-hold cap is connected to an integration-cap current-sensing resistor [144] which provides a pulse train to the input section of the Source Load-Pull Analyser [122] which contains a window comparator comprising a sixth comparator [145] and a seventh comparator [146]. These two comparators monitor the third hold-capacitor's positive and negative voltage deviation determined by the differences in their switching-point timing and the value of resistance and capacirance chosen. Either comparator output is passed by the first OR gate [147] to a second monostable [148] which extends any dFsw pulses detected by the comparators to allow the following MPPTnHref [17] functional block to catch the output SMPL flag [125].

We claim Lhe Frequency Devia Lion DeLeoLion Sys Lent using a Dual-Phase Envelope Decimator in Claim 10.

Autonomous Ambient Energy Management System DESCRIPTION -PREFERRED EMBODIMENTS (continued) [17] The MPPTnHref or Maximum Power-Point Track and Hold Reference of Figure 9 shows output section of the SLPA [122]feeds-back the RxPwrTrk's SMPL flag [125] via the third Flip-Flop [153] by setting its Q output to brings up the BLNK flag to activate the Vpd [301] input sampler switches [118] and [119] into their track mode to form a feed-back handshake via the BLNK control line [123] into Vref [304] into the MPPRTTBC's primary comparator [107] which perturbs the Vpd input and excites the dVdt transient decay detector within the SLPA [122] via the dVdt capacitor [124] which picks off any residual transients on Vpd and pass these to a current-sensing resistor [149] that drives the eighth Comparator [150] and the ninth comparator [151].

The two form a window comparator that detects when the Vpd's dVdt approaches zero as set by the +Refl input to the eighth comparator and -Ref1 input to the ninth comparator. At the first comparator reference crossing into the near-zero window that comparator resets the third Flip-flop [153] and de-asserts the BLNK flag [123]. At the falling edge of the BLNK flag the Vpd input divider is removed from the Cref [08] leaving it with an exact replica of the Vpd input [301] voltage as scaled by the resistive divider [120, 121]. Removing the PINK flag also restarts MPPRTBC [15] internal activity.

The BLNK flag out of the SLPA [122] output section in Figure 9 also cuts-off the second comparator [107] (in Figure 4) disabling any MPPRTTBC [15] activity which allows the Vpd input 301 to settle to the input array's open-circuit voltage. The BLNK flag also connects the Cref capacitor [08] across the Vpd input [301 via two voltage divider resistors [120] and [119]. These two resistors charge Cref to 0.693x Vpd as Vpd settles.

We claim the Track and Hold Reference driven by the feed-forward SMPL, feed-back BLNK loop reset by an Input Derivative Settle Detection Window system in Claim 11.

We claim the split-capacitor replica arrangement for integrating the harvester input current whilst taking a sample of that input then present a scaled replica to the primary boost-converter as its reference in Claim 12.

We also claim the Source Load-Pull Analyser [122] consisting of part of the functional blocks [15] [17] and [18] in Claim 13.

Autonomous Ambient Energy Management System DESCRIPTION -PREFERRED EMBODIMENTS (continued) Figure 10 presents two alternate off-chip configurations for the SICSRreg [200] outputs.

The SICSnRreg or Single Inductor Charge Storage and Recovery Regulator [200] of Figure 5 has already been presented, here we give additional information for the connectivity and function of the [200, 300] HV interface to an off-chip Energy Store. On-chip this consists of functional blocks [24] and [25] however it can have off-chip alternatives that raise the storage voltage past what the base PMMIC Process Technology can support. The SDC2022 [200] and 5DC2023 [300] target a -MV store however, with additional external components both a much higher than process technology +HV or a much higher than process technology -NV can be supported as may be needed to recover energy from a Dielectric Elastomer Generator when used as an energy store.

The three functional blocks on the left of Figure 10 being the PMOS drive [21] the NMOS Drive [22] and the Isns2Trip-Point Detect [23] are as per the SICSnRreg [200] functional block of Figure 5.

The off-chip -fly PMOS SW-AR Drive replaces cell [24] and consists of the -NV PMOS Gate Resistor [43] the -MV PMOS Gate Bias Diode [44] the -NV PMOS Gate Clamp Device [45] The -NV PMOS Output Bias Diode [46] and the -NV PMOS Output Device [47] to the upper centre of Figure 10.

The off-chip -MV LIMOS AR-SW Drive replaces cell [25] and consists of the -NV NMOS Gate Resistor [38] the -NV NMOS Gate Bias Diode [39] the -NV NMOS Gate Clamp Device [40] The -NV LIMOS Output Bias Diode [41] and the -NV LIMOS Output Device [42] to the lower centre of Figure 10.

The off-chip +HV PMOS AR-SW Drive replaces cell [25] and consists of the +HV PMOS Gate Resistor [48] the +HV PMOS Gate Bias Diode [49] the +NV PMOS Gate Clamp Device [50] The +HV PMOS Output Bias Diode [51] and the +HV PMOS Output Device [52] to the upper right of Figure 10.

The off-chip +HV LIMOS SW-AR Drive replaces cell [24] and consists of the +HV NMOS Gate Resistor [53] the +HV NMOS Gate Bias Diode [54] the +HV NMOS Gate Clamp Device [55] The +HV HMOS Output Bias Diode [56] and the +HV HMOS Output Device [57] to the lower right of Figure 10.

Notice that for the +HV variant the sense of the current-sensing voltage developed across Rsns2 [11} must be swapped over before connecting to the Isns+ [312] input node and the Isns-:327] input node leading to the second Amplifier [221 and the third amplifier [23] as the current direction through Lfly2 [12] and Rsns2 [11] has reversed with respect to those in the -NV variant.

We claim Ube Bi-directional Multiplexer SW-AR [20] functional block and the dual switch/active-rectifier construct to time share a single inductor to both charge and discharge an energy store in Claim 14.

We also claim the whole AEMS or Ambient Energy Management System as a necessary framework for each of our earlier claims with the unique feature of being a completely stand-alone and maintenance free unit suited to embedded applications when implemented with a solid-state dielectric energy storage for Cstore [13] in Claim 1, 2 and 17.

Claims (1)

1. Autonomous Ambient Energy Management SystemCLAIMSClaim 1: We claim an apparatus [300] in Figure 2 of the DIAGRAMS which implements an Autonomous Ambient Energy Management System for use in conditioning the energy output from one or many Environmental Ambient Energy Harvesters wherein that energy may be stored in one or many solid-state Dielectric Energy Storage elements such that stored energy may then be recovered and conditioned for use by standard electronic equipment.Claim 2: We claim the said Ambient Energy Management System apparatus of Claim 1 comprising: a Zero-Bias Cold-Start Boost-Converter [14] of Figure 2 and Claim 6; a Fixed Pulse-Width Variable-Position Modulator of Figures 4 and 7 and Claim 7; a SMPS comprising the Maximum Power-Point Real-Time Tracking Boost Converter [15] of Figure 2 and Claim 7; an Active-Rectifier [16] of Figures 2, 3 and 7 containing the Metal-Oxide Semiconductor Inverse Diode Overshoot Trigger of Claim 8 and Claim 9; a Receive Power Tracking System [18] of Figures 2, 4 and 8 containing the Frequency Discriminating Envelope Decimator of Claim 10; the Track-and-Hold Reference Sampler [17] of Figures 2, 4 and 9 and Claim 11, the Input Derivative Setcle Detection Window Comparator [124, 149, 150, 151 and 152] of Figure 9 and Claim 11, the Source Load-Pull Analyser [122] of Figures 8 and 9 and Claim 11; the Single Inductor Charge Storage and Recovery Regulator comprising a Bidirectional Multiplexer [20], [23] and its dual-purpose HV Switch/ActiveRectifier terminators [21], [22], [24] and [25] of Figures 2, 5 and 10 and Claim 14.Claim 3: We claim the Ambient Energy Management System apparatus of Claim 1 containing: interconnectivity and functional block interconnectivity comprising functional-block or functional-blocks within that Ambient Energy Management System as described in the DESCRIPTION and numbered 100, 200, 300, 14 to 25 in Figures 1, 2, 3, 4 and 5 of the DRAWINGS and DESCRIPTION further comprising: sub-circuits numbered 100 to 106 and 112 to 117 and 126 and 128 to 131 in Figure 3 of said DRAWINGS and described in said DESCRIPTION then numbered 107 to 111 and 118 to 125 and 127 in Figure 4 of said DRAWINGS and described in said DESCRIPTION then numbered 200 to 220 in Figure 5 of said DRAWINGS and described in said DESCRIPTION further comprising: the structure of the interconnections numbered 300 to 327 in the DESCRIPTION and Figures 1 to 10 in said DRAWINGS.Claim 4: We claim an apparatus numbered [100] in Figures 1 to 4 and Figures 6 to 9 of the DIAGRAMS which implements an autonomous independent Cold-Start Maximum Power-Point Track-and-Hold Boost Converter for use in conditioning the energy output from one to many Environmental Ambient Energy Harvesters containing interconnectivity and functional-block or functional-blocks comprising: any or all sub-circuits as described in the DESCRIPTION and numbered 100, 14 to 19 in Figures 2, 3 and 4 of the DRAWINGS and DESCRIPTION comprising sub-eireuiLs numbered 100 Lo 106 and 112 to 117 and 126 and 128 to 131 in Figure 3 of said DRAWINGS and described in said DESCRIPTION then numbered 107 to 111 and 110 to 125 and 127 in Figure 4 of said DRAWINGS and described in said DESCRIPTION further comprising: the structure of the interconnections numbered 301 to 311 and 324 to 326 in the DESCRIPTION and Figures 1 to 4 and 6 to 9 in the said DRAWINGS.Autonomous Ambient Energy Management System CLAIMS (continued) Claim 5: We claim an apparatus numbered [200] in Figures 1, 2, 5 and 10 of the DIAGRAMS which implements an autonomous independent Single Inductor Charge Storage and Recovery Regulator for use in storing energy in one or many solid-state Dielectric Energy Storage elements then recover that stored energy and condition it for use by standard electronic equipment: containing interconnectivity and functional-block or functional-blocks further comprising: sub-circuits as described in the DESCRIPTION and numbered 200, 20 to 25 in Figures 1, 2, and 5 of the DRAWINGS and DESCRIPTION comprising sub-circuits numbered 200 to 220 in Figure 5 of said DRAWINGS and described in said DESCRIPTION further comprising: the structure of the interconnections nunbered 307, 312 to 323 and 327 in the DESCRIPTION and Figures 1, 2, 5 and 10 in the said DRAWINGS.Claim 6: we claim a Zero-Bias Cold-Start Boost-Converter device (ZBCSBC) [14] as presented in Figure 6 comprising: a compound depletion-enhancement MOSFET capable of operating in Class A/AB/E depending on load level to create a negative transconductance within a passive resonant network to regeneratively increase near zero sub-Silicon-bandgap voltage levels up to those typical of commercial off-the-shelf monolithic integrated-circuits further comprising: an automatic load isolation switch within the ZBCSBC core to disconnect the AC-DC output convertor during initial class-A startup period of that ZBCSBC core further comprising: an output load isolation switch to optimise the ZBCS core Class-A to Class-E start-up trajectory further comprising: a de-bias circuit [106] to cut-off the compound depletion-enhancement MOSFET device [400].Claim 7: We claim a Real-Time Tracking Switched-Mode Power Supply as presented in the lower part of Figure 7 comprising: a monostable within a sawtooth relaxation oscillator to create a Fixed Pulse-Width Variable-Position Modulator to linearise the host SMPS's reference voltage with respect to that SMPS's switch-frequency characteristic such that it functions as a Voltage Controlled Oscillator; use of a fixed-period mark or space within that modulator to maximize the Independence of the host Switched-Mode Power-Supply's primary switched-inductor current with respect to the host SMPS's switch-rate or frequency; the use of said inductor current to identify dVdt=0 and zero-current-crossing points in flyback waveform to enable the active rectifier synchronisation system of Claim 0, Claim 9 and the delta switch frequency identification system of Claim 10.Claim 8: We claim the use of the MOS Active Rectifier functional block [16] in the upper part of Figure 3 comprising: a MOSFET device [117]; a MOSFET device's Inverse body diode [112] or other external parallel diode or diode connecised bipolar or diode-eonnecLed field errecL device; a current-detection amplifier device [114]; a current-detection comparator device [115]; a switch-state-memory device [113]; a voltage-overshoot detection comparator device [116]; we further claim their use to track the current status through the external flyback inductor numbered [04] and that device's current sensing resistor numbered [03] to switch the MOSFET device [117] on and off.Autonomous Ambient Energy Management System CLAIMS (continued) Claim 9: We claim the Fly-back Inductor Zero-current detection construct formed by a current-mirror arrangement comprising: a substrate diode or MOS= body diode [112] of Figure 7 or a diode-connected MOSFET or a junction-diode or a diode-connected bipolar junction transistor used on the input side of that current mirror arrangement wherein an output device consisting of: a substrate bipolar junction transistor [411] or an isolated bipolar transistor or a MOSFET idenpifies the supply voltage over-shoot caused by a switched inductor [04] commutation voltage change dropping to zero as that switched inductor's dI/dt passes through zero; further we claim the use of the switched inductor's commutation current to activate the current mirror to self-initiate the MOS Channel conduction such that the Active Rectifier MOS channel conduction activates as in Claim B. Claim 10: We claim a device for Frequency Deviation Detection as in Figure 8 which measures the derivative of a dual phase envelope decimator comprising: a multiplicity of input synchronised Frequency-Tracking ramp generators [134, 133 and 135]; a multiplicity of envelope decimators [137, 138] and [143, 141] with [138] and [142]]; and a multiplicity of sampleand-hold integrators [139, 141] with [140 and 144] synchronised to an input clock divider [136]; for use identifying changes in input frequency from a SMPS such as voltage controlled switch rate SMPS or VCO or fixed pulse-width variable-frequency modulator such as that in Claim 7.Claim 11: We claim a device that implements an Source Load-Pull Analyser (SLPA) as in Figures 8 and 9 to track an input then hold a sample of that input as a reference over time for that sampled input voltage level as in Figure 9 which comprises: a hold event trigger [125] as driven by a sample-pulse teed-forward signal path through the sample window comparator [145] and [146] with the second Monostable [148] of Figure 8 whose operation is explained in the DESCRIPTION to generate the SMPL flag [125]; a BLNH flag [123] as in Figure 9 set by the said SMPL flag to disable the primary boost-converter [15] of Figure 4 causing the Vpd input to settle to its open-circuit unloaded value; meanwhile the Input Derivative Settle Detection Window within the SLPA [122] of Figure 9 generates a feed-back reset flag via [152] when the said Vpd input's settle trajectory approaches zero terminating the BIRK period; the reference scaling switches [118] and [119] open to leave a scaled replica of that unloaded Vpd input voltage on the Reference Hold Capacitor [08] as described in the DESCRIPTION; further we claim the method and use of the feed-forward plus feed-back handshake formed by the said SMPL-BLNK-reset loop within the SLPA [122] to identify when the optimum source load-pull reference point has been found then stored once the BIRK flag [123] has been removed by the Vpd input [301] dVdt decay detection window comparator within the SLPA [122].Autonomous Ambient Energy Management System CLAIMS (continued) Claim 12: We claim the method and use of a replica of the energy harvester input integration filter capacitor comprising Cpd [02] and Cref [08] with a pair of -1n(0.5) scaled resistors [120] and [121] and their controlling switches [118] and [119] as presented in Figure 9 which monitor the input charge-rate received by a power-supply during is track phase whereby one part of a capacitor array is switch into circuit during the blank and sample period to track input voltage settling via the said pair of 0.307x and 0.693x scaled resistors [120] and [121] then Isolated from the input and ground by said dual switches [118] and [119] when a dVdt monitor comprising a capacitor [124], a resistor [149] with a window comparator [150] and [151] driving an "AND" gate [152] detects when the Vpd input transient has settled and terminates the BLNK period switching the said split input capacitance into its hold mode during the switched-mode power-supply's run-period to hold the said scaled and stored reference voltage for the SMPS's modulator's switch-level input during both that run-period and its blank-period as part of tracking the input source's or combined sources' optimum operating point for source to load power-transfer within a switched-mode power-supply's power input tracking system.Claim 13: we claim a Maximum Power-Point Tracking method based on the Source Load-Pull Analyser (SPLA) [122] of Claim 11 and harvester input replica of Claim 12 comprising: a monostable linearised sawtooth relaxation oscillator of Figure 3, Figure 7 and Claim 7 embedded within a Fixed Pulse-Width Variable-Position Modulator also in Claim 7 and described in the DESCRIPTION; a single Instance or a multiplicity of Instances of the said frequency discriminating envelope decimator of Claim 10 and Figure 8; a track and hold construct controlled by the said sample feed-forward and an input dV/dt driven feed-back handshake of the SIPA device of Claim 11 Figure 8 and Figure 9 to identify when the optimum source load-pull reference value for the host Switched-Mode Power-Supply or Voltage Controlled Oscillator has been identified and stored in said scaled input reference as in Claim 12 and described in the DESCRIPTION.Claim 14: we claim the method and use of a Bi-directional Switch and/or Active-Rectifier Multiplexed Drive [20] of Figure 5 to time-share a single inductor terminated by dual switch/active-rectifier construct or constructs [21] plus [24] and [22] plus [25] of Figure 5 as described in the DESCRIPTION to enable the use of HV dielectric cells for energy storage; we further claim said Si-directional SW-AR Multiplexer construct [20] of Figure 5; we further claim the method for pulse by pulse control of charge and depletion of the energy store enabled by either a single pulse in either direction or a multiplicity of pulses in either direction consecuLiyely; farLher we claim Ube whole consLrueL which funeLions as a DC isolated bidirectional dual-phase switch with ports that can alternately be a LV Inductor-Switch input and a HV Active-Rectifier output or a LV Active-Rectifier output and a HV Inductor-Switch input as described in the DESCRIPTION for the functional blocks [20] to [25] for the SICSnPreg [200] of Figure 5; further we claim both off-chip positive going and negative going High-Voltage variants which replace the on-chip functional blocks [24] and [25] as shown Figure 5 and numbered [38] to [5E] in Figure 10 and their inter-connectivity as shown in Figure 10.Autonomous Ambient Energy Management System CLAIMS (continued) Claim 15: We claim a Si-directional Switch and/or Active-Rectifier Multiplexed Drive as shown in Figure 2, 5 and 10 of the DRAWiNGS to timeshare a single inductor terminated by a dual switch/active-rectifier constructs as in Claim 14 for use with one or many Dielectric Elastomer Generators as both a HV Energy Storage Cell as well as a MV Energy Generator input to said Single Inductor Charge Storage and Recovery Regulator PMMIC [200] and the Ambient Energy Management System SoC [300] as described in the DESCRIPTION as shown in Figure 1 of the DRAWINGS.Claim 16: we claim the use of a merged two inductor variant of the Cold-Start Maximum Power-Point Tracking Boost Converter (CSMPPTBC) [100] off-chip support circuit for the Zero-Bias Cold-Start Boost-Converter (ZBCSBC) [14] external resonant tank to timeshare its output shunt inductor L2 [35] shown at the top of Figure 6, between the ZBCS core [101] of Figure 3 being the Negative Transconductance [400] of pin 325 of Figure 6 with pin [305] the MPPRTTBC's NMOS output device [110] of Figure 4 as redrawn in the upper schematic of Figure 6 where L2 [35] of the ZBCSBC [14] tank to be re-used by the MPPRTTBC NMOS output device's drain [305] in place of its own dedicated Commutation Inductor Lflyl [04] of Figure 3 redrawn in the middle schematic of Figure 6 as described in the DESCRIPTION; we further claim the fragmented three inductor variant of the CSMPPTBC [100] support circuit where the ZBCSBC external resonant tank's Ll [34] and L2 [35] are separate and uncoupled from the Commutation Inductor Lflyl [04] of the separate MPPRTTBC's NMOS output device [110] whereas the ZBCS core [101] remains connected to 12 [35] as drawn in the middle schematic of Figure 6 and described in the DESCRIPTION.Claim 17: We claim the Si-directional Switch and/or Active-Rectifier Multiplexed Drive of Claim 15 for use with Dielectric Elastomer Generators; we further claim use of the Multiplexed Switch/Active-Rectifier of Claim 15 and its connection to a Dielectric Elastomer Generator for the purpose of energy charging, energy storage, voltage-priming and energy recovery from Dielectric Elastomer Generators.NOTE: the encircled Dielectric Elastomer Generator's self-priming voltage mulLiplier labelled [60] in Figure 1 remains 'she inLellebLual properLy of the authors of Reference 1 as follows: See Figure 5 "Self Priming Dielectric Elastomer Generators" McKay, O'Brian, Callus and Anderson, 91[1' April 2010. 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