GB2616573A - Resistive memory array - Google Patents

Resistive memory array Download PDF

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Publication number
GB2616573A
GB2616573A GB2309314.9A GB202309314A GB2616573A GB 2616573 A GB2616573 A GB 2616573A GB 202309314 A GB202309314 A GB 202309314A GB 2616573 A GB2616573 A GB 2616573A
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GB
United Kingdom
Prior art keywords
resistive memory
vertical resistive
electrode
vertical
memory unit
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
GB2309314.9A
Inventor
Kim Youngseok
Lee ChoongHyun
Matthew Philip Timothy
Seo Soon-Cheon
Ok Injo
Reznicek Alexander
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
International Business Machines Corp
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International Business Machines Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by International Business Machines Corp filed Critical International Business Machines Corp
Publication of GB2616573A publication Critical patent/GB2616573A/en
Pending legal-status Critical Current

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Classifications

    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C13/00—Digital stores characterised by the use of storage elements not covered by groups G11C11/00, G11C23/00, or G11C25/00
    • G11C13/0002—Digital stores characterised by the use of storage elements not covered by groups G11C11/00, G11C23/00, or G11C25/00 using resistive RAM [RRAM] elements
    • G11C13/0007—Digital stores characterised by the use of storage elements not covered by groups G11C11/00, G11C23/00, or G11C25/00 using resistive RAM [RRAM] elements comprising metal oxide memory material, e.g. perovskites
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C13/00—Digital stores characterised by the use of storage elements not covered by groups G11C11/00, G11C23/00, or G11C25/00
    • G11C13/0002—Digital stores characterised by the use of storage elements not covered by groups G11C11/00, G11C23/00, or G11C25/00 using resistive RAM [RRAM] elements
    • G11C13/0021—Auxiliary circuits
    • G11C13/0033—Disturbance prevention or evaluation; Refreshing of disturbed memory data
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C13/00—Digital stores characterised by the use of storage elements not covered by groups G11C11/00, G11C23/00, or G11C25/00
    • G11C13/0002—Digital stores characterised by the use of storage elements not covered by groups G11C11/00, G11C23/00, or G11C25/00 using resistive RAM [RRAM] elements
    • G11C13/0021—Auxiliary circuits
    • G11C13/004—Reading or sensing circuits or methods
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10B—ELECTRONIC MEMORY DEVICES
    • H10B63/00—Resistance change memory devices, e.g. resistive RAM [ReRAM] devices
    • H10B63/80—Arrangements comprising multiple bistable or multi-stable switching components of the same type on a plane parallel to the substrate, e.g. cross-point arrays
    • H10B63/84—Arrangements comprising multiple bistable or multi-stable switching components of the same type on a plane parallel to the substrate, e.g. cross-point arrays arranged in a direction perpendicular to the substrate, e.g. 3D cell arrays
    • H10B63/845—Arrangements comprising multiple bistable or multi-stable switching components of the same type on a plane parallel to the substrate, e.g. cross-point arrays arranged in a direction perpendicular to the substrate, e.g. 3D cell arrays the switching components being connected to a common vertical conductor
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10N—ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10N70/00—Solid-state devices having no potential barriers, and specially adapted for rectifying, amplifying, oscillating or switching
    • H10N70/011—Manufacture or treatment of multistable switching devices
    • H10N70/061—Shaping switching materials
    • H10N70/066—Shaping switching materials by filling of openings, e.g. damascene method
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10N—ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10N70/00—Solid-state devices having no potential barriers, and specially adapted for rectifying, amplifying, oscillating or switching
    • H10N70/20—Multistable switching devices, e.g. memristors
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10N—ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10N70/00—Solid-state devices having no potential barriers, and specially adapted for rectifying, amplifying, oscillating or switching
    • H10N70/801—Constructional details of multistable switching devices
    • H10N70/821—Device geometry
    • H10N70/826—Device geometry adapted for essentially vertical current flow, e.g. sandwich or pillar type devices
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10N—ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10N70/00—Solid-state devices having no potential barriers, and specially adapted for rectifying, amplifying, oscillating or switching
    • H10N70/801—Constructional details of multistable switching devices
    • H10N70/841—Electrodes
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10N—ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10N70/00—Solid-state devices having no potential barriers, and specially adapted for rectifying, amplifying, oscillating or switching
    • H10N70/801—Constructional details of multistable switching devices
    • H10N70/881—Switching materials
    • H10N70/882—Compounds of sulfur, selenium or tellurium, e.g. chalcogenides
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10N—ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10N70/00—Solid-state devices having no potential barriers, and specially adapted for rectifying, amplifying, oscillating or switching
    • H10N70/801—Constructional details of multistable switching devices
    • H10N70/881—Switching materials
    • H10N70/883—Oxides or nitrides
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C13/00—Digital stores characterised by the use of storage elements not covered by groups G11C11/00, G11C23/00, or G11C25/00
    • G11C13/0002—Digital stores characterised by the use of storage elements not covered by groups G11C11/00, G11C23/00, or G11C25/00 using resistive RAM [RRAM] elements
    • G11C13/0021—Auxiliary circuits
    • G11C13/003—Cell access
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C13/00—Digital stores characterised by the use of storage elements not covered by groups G11C11/00, G11C23/00, or G11C25/00
    • G11C13/0002—Digital stores characterised by the use of storage elements not covered by groups G11C11/00, G11C23/00, or G11C25/00 using resistive RAM [RRAM] elements
    • G11C13/0021—Auxiliary circuits
    • G11C13/0069—Writing or programming circuits or methods
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C13/00—Digital stores characterised by the use of storage elements not covered by groups G11C11/00, G11C23/00, or G11C25/00
    • G11C13/0002—Digital stores characterised by the use of storage elements not covered by groups G11C11/00, G11C23/00, or G11C25/00 using resistive RAM [RRAM] elements
    • G11C13/0021—Auxiliary circuits
    • G11C13/004—Reading or sensing circuits or methods
    • G11C2013/005—Read using potential difference applied between cell electrodes
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C2213/00—Indexing scheme relating to G11C13/00 for features not covered by this group
    • G11C2213/70—Resistive array aspects
    • G11C2213/71—Three dimensional array
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C2213/00—Indexing scheme relating to G11C13/00 for features not covered by this group
    • G11C2213/70—Resistive array aspects
    • G11C2213/77—Array wherein the memory element being directly connected to the bit lines and word lines without any access device being used

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  • Engineering & Computer Science (AREA)
  • Manufacturing & Machinery (AREA)
  • Chemical & Material Sciences (AREA)
  • Materials Engineering (AREA)
  • Semiconductor Memories (AREA)

Abstract

A vertical resistive memory array is presented. The array includes a pillar electrode and a switching liner around the side perimeter of the pillar electrode. The array includes two or more vertically stacked single cell (SC) electrodes connected to a first side of the switching liner. The juxtaposition of the switching liner, the pillar electrode, and each SC electrode forms respective resistance switching cells (e.g., OxRRAM cell). A vertical group or bank of these cells may be connected in parallel and each share the same pillar electrode. The cells in the vertical cell bank may written to or read from as a group to limit the effects of inconsistent CF formation of any one or more individual cells within the group.

Claims (20)

1. A vertical resistive memory array comprising: a front vertical resistive memory unit comprising a front resistive random access memory (RRAM) pillar and a first vertically stacked electrode group connected to a firs t side of the front RRAM pillar; the front RRAM pillar comprising a first pillar electrode and a first swit ching liner around and contacting a sidewall perimeter of the first pillar electrode; and the first vertically stacked electrode group comprising a first upper sing le cell (SC) electrode in contact with the first switching liner and a first lower SC electrode in contact with the first switching liner.
2. The vertical resistive memory array of claim 1, wherein the front vertical resistive memory unit further comprises: a second vertically stacked electrode group connected to a second side of the front RRAM pillar, the second vertically stacked electrode group comprising a second upper S C electrode in contact with the first switching liner and a second lower S C electrode in contact with the first switching liner.
3. The vertical resistive memory array of claim 2, further comprising: a rear vertical resistive memory unit comprising a rear RRAM pillar and a third vertically stacked electrode group connected to a first side of the rear RRAM pillar; the rear RRAM pillar comprising a second pillar electrode and a second swi tching liner around a sidewall perimeter of the second pillar electrode; and the third vertically stacked electrode group comprising a third upper SC e lectrode in contact with the second switching liner and a third lower SC e lectrode in contact with the second switching liner.
4. The vertical resistive memory array of claim 3, wherein the rear vertical resistive memory unit further comprises: a fourth vertically stacked electrode group connected to a second side of the rear RRAM pillar, the fourth vertically stacked electrode group comprising a fourth upper S C electrode in contact with the second switching liner and a fourth lower SC electrode in contact with the second switching liner.
5. The vertical resistive memory array of claim 4, comprising a first upper multi cell (MC) electrode connected to the first upper SC electrode and connected to the third upper SC electrode.
6. The vertical resistive memory array of claim 5, comprising a second upper MC electrode connected to the second upper SC e lectrode and connected to the fourth upper SC electrode.
7. The vertical resistive memory array of claim 6, comprising a first lower MC electrode connected to the first lower SC ele ctrode and connected to the third lower SC electrode.
8. The vertical resistive memory array of claim 7, comprising a second lower MC electrode connected to the second lower SC e lectrode and connected to the fourth lower SC electrode.
9. A vertical resistive memory array method comprising: receiving, with a memory controller, a read request to obtain data stored in a single memory cell from a reque sting device; applying, with the memory controller, a read potential to a vertical resistive memory unit that comprises a plu rality of ReRAM cells that share the same pillar electrode; determining, with the memory controller, an equivalent resistance of the vertical resistive memory unit; determining, with the memory controller, a resistance state of the vertical resistive memory unit; returning, with the memory controller, a data value that is associated with the determined resistance state of t he vertical resistive memory unit to the requesting device.
10. The vertical resistive memory array method of claim 9, wherein the vertical resistive memory unit further comprises a plurality of single cell (SC) electrodes and a switching liner around and contacting the sidewall perim eter of the pillar electrode.
11. The vertical resistive memory array method of claim 10, wherein each of the plurality of SC electrodes comprises a pillar facing sidewall that contacts the switching liner.
12. The vertical resistive memory array method of claim 10, wherein applying the read potential to the vertical resistive memory unit , comprises: applying, with the memory controller, a low or ground potential to the pillar electrode; and applying, with the memory controller, a read potential to each of the plurity of SC electrodes.
13. The vertical resistive memory array method of claim 12, further comprising: sensing, with the memory controller, current through the vertical resistive memory unit that is caused by the read potential being applied to the vertical resistive memory unit.
14. The vertical resistive memory array method of claim 13, wherein the equivalent resistance of the vertical resistive memory unit i s determined from the sensed current through the vertical resistive memory unit.
15. A vertical resistive memory array method comprising: receiving, with a memory controller, a read request to obtain data stored in a single memory cell from a reque sting device; applying, with the memory controller, a read potential to a vertical resistive memory unit that comprises a plu rality of ReRAM cells that share the same pillar electrode; determining, with the memory controller, a resistance of the each of the plurality of ReRAM cells in the vertical resistive memory unit; determining, with the memory controller, a combined resistance of each resistance of the plurality of ReRAM cells in the vertical resistive memory unit; determining, with the memory controller, a resistance state of the vertical resistive memory unit from the combine d resistance; returning, with the memory controller, a data value that is associated with the determined resistance state of t he vertical resistive memory unit to the requesting device.
16. The vertical resistive memory array method of claim 15, wherein the vertical resistive memory unit further comprises a plurality of single cell (SC) electrodes and a switching liner around and contacting the sidewall perim eter of the pillar electrode.
17. The vertical resistive memory array method of claim 16, wherein each of the plurality of SC electrodes comprises a pillar facing sidewall that contacts the switching liner.
18. The vertical resistive memory array method of claim 16, wherein applying the read potential to the vertical resistive memory unit , comprises: applying, with the memory controller, a low or ground potential to the pillar electrode; and applying, with the memory controller, a read potential to each of the plurality of SC electrodes.
19. The vertical resistive memory array method of claim 18, further comprising: sensing, with the memory controller, current through each of the plurality of ReRAM cells in the vertical resi stive memory unit caused by the read potential being applied to the vertic al resistive memory unit.
20. The vertical resistive memory array method of claim 19, wherein the combined resistance of the vertical resistive memory unit is determined from the sensed current through each of the plurality of ReRAM cells in the vertical resistive memory unit.
GB2309314.9A 2020-11-25 2021-10-21 Resistive memory array Pending GB2616573A (en)

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
US17/104,405 US11588103B2 (en) 2020-11-25 2020-11-25 Resistive memory array
PCT/CN2021/125236 WO2022111150A1 (en) 2020-11-25 2021-10-21 Resistive memory array

Publications (1)

Publication Number Publication Date
GB2616573A true GB2616573A (en) 2023-09-13

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ID=81657512

Family Applications (1)

Application Number Title Priority Date Filing Date
GB2309314.9A Pending GB2616573A (en) 2020-11-25 2021-10-21 Resistive memory array

Country Status (6)

Country Link
US (1) US11588103B2 (en)
JP (1) JP2023551159A (en)
CN (1) CN116529819A (en)
DE (1) DE112021006143T5 (en)
GB (1) GB2616573A (en)
WO (1) WO2022111150A1 (en)

Citations (5)

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US20130201750A1 (en) * 2012-02-08 2013-08-08 Samsung Electronics Co., Ltd. Variable resistance memory device and related method of operation
US20130229855A1 (en) * 2012-03-02 2013-09-05 Samsung Electronics Co., Ltd. Resistive memory device having defined or variable erase unit size
CN103378290A (en) * 2012-04-26 2013-10-30 爱思开海力士有限公司 Variable resistance memory device and method for fabricating the same
CN106448727A (en) * 2015-08-12 2017-02-22 华邦电子股份有限公司 Resistive memory apparatus and reading method thereof
CN108346446A (en) * 2017-01-23 2018-07-31 西部数据技术公司 The vertical RERAM of high density 3D with two-way threshold type selector

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WO2010101340A1 (en) 2009-03-05 2010-09-10 광주과학기술원 Resistance change memory device with three-dimensional structure, and device array, electronic product and manufacturing method therefor
CN103325414A (en) 2013-05-21 2013-09-25 清华大学 RRAM memory read circuit
GB2515567A (en) 2013-06-28 2014-12-31 Ibm Phase-Change memory cells
GB2515568B (en) 2013-06-28 2016-05-18 Ibm Resistive random-access memory cells
CN104716259A (en) 2013-12-13 2015-06-17 上海华虹宏力半导体制造有限公司 Three-dimensional multi-layer resistive random access memory
US9698202B2 (en) 2015-03-02 2017-07-04 Sandisk Technologies Llc Parallel bit line three-dimensional resistive random access memory
US10497752B1 (en) 2018-05-11 2019-12-03 International Business Machines Corporation Resistive random-access memory array with reduced switching resistance variability
US10658582B2 (en) 2018-06-06 2020-05-19 International Business Machines Corporation Vertical resistive processing unit with air gap
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Patent Citations (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US20130201750A1 (en) * 2012-02-08 2013-08-08 Samsung Electronics Co., Ltd. Variable resistance memory device and related method of operation
US20130229855A1 (en) * 2012-03-02 2013-09-05 Samsung Electronics Co., Ltd. Resistive memory device having defined or variable erase unit size
CN103378290A (en) * 2012-04-26 2013-10-30 爱思开海力士有限公司 Variable resistance memory device and method for fabricating the same
CN106448727A (en) * 2015-08-12 2017-02-22 华邦电子股份有限公司 Resistive memory apparatus and reading method thereof
CN108346446A (en) * 2017-01-23 2018-07-31 西部数据技术公司 The vertical RERAM of high density 3D with two-way threshold type selector

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Publication number Publication date
JP2023551159A (en) 2023-12-07
US11588103B2 (en) 2023-02-21
DE112021006143T5 (en) 2023-09-21
WO2022111150A1 (en) 2022-06-02
US20220165947A1 (en) 2022-05-26
CN116529819A (en) 2023-08-01

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