GB2608110A

GB2608110A - Wireless power and data transfer

Info

Publication number: GB2608110A
Application number: GB2108856.2A
Authority: GB
Inventors: Kazemi Masoud; Obszanski Karl
Original assignee: Aston Vision Sciences Ltd
Current assignee: Aston Vision Sciences Ltd
Priority date: 2021-06-21
Filing date: 2021-06-21
Publication date: 2022-12-28
Also published as: GB202108856D0; GB2608205A; GB2608205B

Abstract

Wireless power and data transfer system arranged to transmit a power signal having a first frequency; a secondary coil 1011 arranged to receive the power signal from the primary coil 1009 by wireless induction; a primary side circuit 1001 arranged to superimpose a first control signal onto the power signal between the coils at the primary coil 1009, the first control signal having a second frequency different to the first frequency; and a secondary side A wireless power and data transfer system 1000 comprising: a primary coil 1009 circuit arranged to superimpose a second control signal onto the power signal between the coils at the secondary coil 1011, the second control signal having a third frequency different to the first frequency and second frequency.

Description

WIRELESS POWER AND DATA TRANSFER

The present disclosure relates to a wireless power transfer system and a method of wireless power and data transfer.

Various wireless power transfer methods are known. For example, near field wireless power transfer may take place by inductive coupling or capacitive coupling. Such techniques allow the transmission of power only from a power source to a load, but not for the transmission of data in any direction. Various wireless communication techniques are also known, such as WiFi, Bluetooth, cellular communications and Zigbee. These allow transmission of data but not power.

Techniques such as Radio Frequency Identification (RF1D) and Near Field Communications (NFC) allow for both transmission of data and power. However, these are passive communication methods and the data transmission is unidirectional.

According to a first aspect of the invention, there is provided wireless power and data transfer system comprising: a primary coil arranged to transmit a power signal having a first frequency; a secondary coil arranged to receive the power signal from the primary coil by wireless induction; a primary side circuit arranged to superimpose a first control signal onto the power signal between the coils at the primary coil, the first control signal having a second frequency different to the first frequency; and a secondary side circuit arranged to superimpose a second control signal onto the power signal between the coils at the secondary coil, the second control signal having a third frequency different to the first frequency and second frequency.

The system allows for bidirectional communication between a primary side and a secondary side, whilst also allowing for concurrent power transfer from the primary side to the secondary side. The transfer of power is continuous and uninterrupted, even whilst communication is ongoing. Furthermore, the system is simple and low cost to implement due to the low number of components. The system is also long lasting as there are no frictional parts or connections.

The primary side circuit may comprise: a primary filter arranged to isolate the second control signal at the primary coil. The secondary side circuit may comprise: a secondary filter arranged to separate the power signal and the first control signal at the secondary coil.

The primary filter and/or the secondary filter may comprise inductive transformers with LC filters.

One of the first control signal and the second control signal may encode a dock component and a data component, and the other of the first control signal and the second control signal encodes a different data component.

The first control signal may comprise a data component and the clock component. The clock component may be common between both the first and the second control signals. The sccond control signal may bc identical or have a different data component to the first control signal.

The one of the first control signal and the second control signal that encodes a clock component may comprise a logic signal able to adopt a plurality of different logic values, each logic value corresponding to a unique combination of the values of the data component and the clock component.

The data components and the clock component may each comprise a binary logic signal having a low value and a high value, such that the one of the first control signal and the second control signal that encodes a clock component and a data component adopts one of four possible logic values.

The wireless power and data transfer system may comprise: a combination module arranged to combine clock component and data component into a single signal.

The first control signal and/or the second control signal may be modulated through a carrier signal to encode the content of the control signal.

I5 20 25 The control signal may be modulated by amplitude modulation, optionally using amplitude-shift keying modulation.

The wireless power and data transfer system may comprise a modulation module arranged to modulate the control signal.

The first frequency may be lower than the second frequency and the third frequency.

The amplitude of the power signal may be greater than the amplitude of the first control signal and the second control signal.

The primary side circuit may comprise: a primary inductive transformer to superimpose the first control signal. The secondary side circuit may comprise a secondary inductive transformer to superimpose the second control signal.

The primary side circuit may comprise: a primary processor arranged to generate the first control signal and receive the second control signal. The secondary side circuit I5 may comprise a secondary processor arranged to generate the second control signal and receive the first control signal.

The first control signal may comprise instructions sent from the primary processor to the secondary processor, and the second control signal may comprise an acknowledge signal, confirming successful transmission of at least a portion of the first control signal.

In certain cases, the roles of the primary processor and secondary processor may be reversed and the secondary side can be capable of receiving an acknowledge signal should control signals be sent from the secondary to the primary.

The wireless power and data transfer system may comprise: a first counter arranged to detect a start of a communication window; a second counter arranged to count a number of bits received; and a third counter arranged to detect the window for the acknowledge signal. Alternatively, digital components such as logic gates may be used as substitutes to counters.

The wireless power and data transfer system may comprise: a primary inverter to invert the output of the primary processor. The wireless power and data transfer system may comprise: a secondary inverter to invert the output of the secondary processor. The secondary side may work without an inverter as the signals coming from the primary side can be interpreted through logic gates.

The primary and secondary coils may be arranged stationary with respect to each other and to an external reference. Alternatively, one or both of the primary coil and secondary coil may be arranged to rotate about its central axis.

The primary coil and secondary coil may each comprise an aperture arranged in the coil.

The wireless power and data transfer system may optionally comprise a core extending through the opening between the primary coil and the secondary coil. The core may be hollow, thereby allowing components or cabling to be passed through the centre of the coils. The core may optionally be a ferrite material IS According to a second aspect of the invention, there is provided a method of wireless power and data transfer, comprising: transmitting a power signal from a primary coil to a secondary coil by wireless induction; superimposing a first control signal onto the power signal at the primary coil; and superimposing a second control signal onto the power signal at the secondary coil, wherein the power signal has a first frequency, the first control signal has a second frequency different to the first frequency and the second control signal has a third frequency different to the first frequency and the second frequency.

The method allows for bidirectional communication between a primary side and a secondary side, whilst also allowing for concurrent power transfer from the primary side to the secondary side. The transfer of power is continuous and uninterrupted, even whilst communication is ongoing. Furthermore, the method is simple and low cost to implement due to the low number of components required.

The method may comprise: filtering the signal induced at the secondary coil to isolate the first control signal; and/or filtering the signal induced at the primary coil to isolate the second control signal.

The method may comprise: generating one of the first control signal and the second control signal by combining a clock signal from a processor and a data signal from the processor.

The one of the first control signal and the second control signal may comprise a logic value encoding a clock component and a data component Various aspects and embodiments of the invention provide for bidirectional communication between a primary side and a secondary side, whilst also allowing for concurrent power transfer from the primary side to the secondary side. The transfer of power is continuous and uninterrupted, even whilst communications are ongoing. Furthermore, the system is simple and low cost to implement due to the low number of components required. The system is also long lasting as there are no frictional parts or connections.

IS

It will be appreciated that, unless mutually exclusive, features discussed in relation to one aspect of the invention may be applied, mutatis mutandis, to any other aspect of the invention.

Embodiments of the invention will now be described, by way of example only, with reference to the accompanying drawings, in which: Figure I schematically illustrates a wireless power transfer system; Figure 2 illustrates a Hock diagram of the wireless power transfer system of Figure 1; Figure 3A provides a circuit diagram of the control circuit for the primary side of the system of Figure 2; Figure 3B provides a circuit diagram of the control circuit for the secondary side of the system of Figure 2; Figure 4 illustrates the combination of a clock signal and data signal into a single analogue signal; Figures 5A to SC illustrate examples of a power signal with a first control signal superimposed Figure 6 illustrates an example of the signal induced at the secondary coil with the first control signal superimposed once power has been separated from the control signal; Figures 7A and 7B illustrates an example of the signal including the power signal, and first and second control signals superimposed; Figure 8 illustrates the timing of an acknowledge window for I2C communication protocol; Figures 9A and 9B illustrate cut-through side views of examples of the coils of the wireless power transfer system of Figure 1; and Figures 10 illustrates the three counters responsible for monitoring the acknowledge time period.

The below description relates to wireless power transfer. It will be appreciated that in the following description the term "primary" will be used to refer to anything on the side from which power is transmitted and the term "secondary" will be used to refer to anything on the power receiving side. The electronic connection between the primary and secondary side is inductive coupling through coils. I5

Figure 1 schematically illustrates a wireless power transfer system 1000. The system 1000 has a primary side 1001 including a power source 1003 and a secondary side 1005 including a power load 1007 that receives power from the power source 1003.

Power is transmitted from the primary side 100 I to the secondary side 1005 by inductive coupling between a primary coil 1009 coupled to the power source 1003 by conductive connections and a secondary coil 1011 coupled to the load 1007 by conductive connections.

Although the coils 1009, 1011 are shown as side by side in the Figures 1, 2, 3A and 3B, the person skilled in the art will appreciate that this is for illustrative purposes only. As shown in Figures 9A and 9B, the primary coil 1009 and secondary coil 101 -I are arranged in parallel planes, and are separated in a perpendicular direction by an air or vacuum (or dielectric) gap 1013. The coils at least partially overlap each other when viewed along the perpendicular direction.

The air or vacuum gap may be any suitable distance. In one example, the air or vacuum gap may be < 20mm. However, the person skilled in the art will appreciate that similar levels of power transfer can be maintained for a larger air or vacuum gap by increasing the power source voltage or coil area.

As will be discussed in more detail below, a first control signal 1017 is superimposed (or injected) into the power signal at the primary coil 1009 and a second control signal 1029 is superimposed onto the power signal at the secondary coil 1011.

The first control signal originates from a primary processor 1015. It is received as a component of the signal induced in the secondary coil 1011 and is fed to a secondary processor 1027. This control signal may be used to control operation of the load 1007 or other components provided on the secondary side.

The second control signal 1029 originates from the secondary processor 1027. It is received as a component of the signal induced at the primary coil 1009, and is fed back to the primary processor 1015.

in one example, the second control signal 1029 may be an acknowledge signal for commands sent using the first control signal 1017, or may be any other type of communication signal.

As shown in Figure 2, the secondary side 1005 includes a filter 1047 which extracts the first control signal 1017 from the power signal and second control signal. Likewise, the primary side 1001 includes a filter 1031 which extracts the second control signal 1029 from the power signal and first control signal.

To ensure proper co-ordination of the primary side 1001 and secondary side 1005 of the system 1000, the clocks of the processors 1015, 1027 must be synchronised. In the current example being discussed, the first control signal 1017 includes a data signal component 1019a and a dock signal component 10196, both generated by the primary processor 1015. The data signal component 1019a provides the commands/communication whilst the clock signal component 1019b is used to provide synchronisation. The data signal component 1019a and clock signal component 1019b are combined at a combination module 1021 on the primary side and separated at an interpretation module 1023 on the secondary side 1005.

The primary side 1001 of the system 1000 and the secondary side 1005 of the system are formed as separate circuits, only connected through the primary and secondary coils 1009, 10 I 1. Each circuit has a circuit ground, and there is no ground connection between the primary and secondary side.

Figure 2 illustrates a block diagram of one example of how to implement a wireless power transfer system 1000 as discussed above. Example circuit diagrams for the primary side 1001 and secondary side 1005 are shown in Figures 3A and 3B respectively. it will be appreciated that various intervening components shown in the circuit diagrams are examples only, and may be changed or removed.

The communications may be through any known protocol. The below example will be discussed in relation to the 12C protocol.

As discussed above, on the primary side 1001 of the system 1000, a primary processor 1015 generates a data signal (SDA) 1019a and a clock signal (SCL) 1019b.

The data signal 1019a is a binary digital signal having a low state (0) and a high state (1). The switching between the states encodes data for transmission. The clock signal is likewise a binary digital signal having a low state (0) and a high state (1). The clock signal has a regular frequency for switching between the states, to ensure correct synchronisation of the primary side 1001 and secondary side 1005, with the primary processor 1015 acting as leader (Master), and the secondary processor 1027 as follower (Slave).

The clock signal 1019b may have any frequency (fd) between 1 kHz and 100 kHz. For example, in the below it will be assumed that fd = 10 kHz, but this is by way of example only. Different fd values may be used in I2C communications and also in different communication protocols The data signal 1019a and clock signal 1019b are inverted by an inverter 1033. The inverter 1033 flips the signal by transforming high digital states into low digital states and low digital states into high digital states. In the I2C protocol (and many other communications protocols) the dock and data outputs default to the high state when no signal is sent. This requires constant power to transfer this state to the secondary side 1005. By inverting the combined signal, power consumption of the signal is reduced.

The inverted data signal 1019a and clock signal 1019b are provided to the combination module 1021 to generate a single analogue signal including both binary values.

In the example shown in Figures 2 and 3A, the combination module 1021 comprises a digital to analogue converter that generates an analogue signal 1035 adopting one of four different voltage levels corresponding to the digital input states, as shown in table 1 below. Figure 4 shows the combination of the inverted signals into the combined signals 1035.

Clock Data signal Clock signal Data signal Combined signal 1019a 1019b 1019a signal 1019b (output (inverted) (inverted) (voltage) (output from from processor processor 1015) 1015) I I 0 0 Voo 1 0 0 1 Vot 0 1 1 0 V10 0 0 1 1 Vii

Table 1

In the example of Figure 4, Voo < Vol < Vto < VII, but this is by way of example, and the four input states (00, 01, 10, 11) may be represented by any suitable differentiable voltages.

The analogue signal 1035 is then modulated onto a first carrier signal of frequency fct to generate the first control signal 1017 by a modulation module 1037. In the example being discussed, Amplitude-Shift Keying Modulation (ASK) with carrier frequency of fel = 4.9152 MHz is used.

An amplifier 1039 is also provided to amplify the first control signal 1017 prior to superimposing onto the power signal Typically, the power source 1003 will be a DC source (for example a 5V DC power source). However, for inductive wireless power transfer, an AC power signal is required. Therefore, a power inverter 1041 is provided.

In the example shown in Figure 3A, the power inverter is a differential pair LC oscillator. This generates a power signal of frequency fp = 80 to 120kHz.

An inductive transformer 1043, including an LC filter, is provided on the primary side 1001 of the system. A first coil 1043a of the transformer 1043 is connected in series to the amplifier 1039 for amplifying the first control signal 1017. A second coil 1043b is connected in series with a second inductive transformer 1067 (discussed below in more detail) and the primary coil 1009 of the wireless power transfer system 1000. The LC filter 1043c is formed by the second coil 1043b of the inductive transformer 1043 and a capacitor connected across the second coil 1043b. The filter is a bandpass filter IS centred on the carrier frequency of the first control signal (f01) and removes the carrier frequency of the power signal and any other control signals, as discussed below.

The primary inductive transformer 1043 allows the first control signal 1017 to be superimposed on top of the power signal.

The primary inductive transformer 1043 is selected to provide a significant difference between fcr and fp in order to minimise the interferences and allow for easier separation of signal into constituent components on the secondary side 1003.

Figure 5A shows an example of the signal generated by superimposing the first control signal 1017 onto the power signal. In a first region 1045a, the trace shows a power signal without a superimposed control signal 1017 due to the inverter. In a second region 1045b, the trace shows a power signal with the superimposed control signal 1045b.

The second region includes: One or more sub-regions 1045b' in which the clock and signal output from the primary processor -1015 are both low (0) -as a result of the inverter 1033, this now has the highest amplitude.

One or more sub-regions 1045b-in which the clock output from the primary processor 1015 is low (0) and the data output is high (1).

One or more sub-regions 1045b' in which the clock output from the primary processor 1015 is high (1) and the data output is low (0).

One or more sub-regions 104513' in which the clock and signal output from the primary processor 1015 are both high (1) -as a result of the inverter 1033, this now has the lowest amplitude.

As can be seen, superimposing the first control signal 1017 causes an increase in the amplitude of the power signal, with the increase proportional to the voltage value of the analogue signal. For example, in the case where the clock and data output from the primary processor 1015 are both high (1) (Von in table 1), the amplitude of the signal is unchanged.

Figure 5B illustrates a close up on the region of the trace where the first control signal 1017 is being superimposed onto the power signal and the logical state changes from the clock and data output from the primary processor 1015 both being low (0) (V11 in table 1) to the clock signal being low (0) and the data signal being high (1) (Vio from table 1).

Figure 5C shows a close up on the region of the trace where the first control signal 1017 is being superimposed onto the power signal and the logical state changes from both being high (1) (Voo in table 1) to both being low (00) (VII in table 1).

The multi-frequency signal created by superimposing the first control signal onto the power signal is passed through the primary coil 1009 and the secondary coil 1011 experiences an inductive influence.

On the secondary side 1005 of the system 1000, the induced signal is a combination of both the power signal and the control signal 1017, which needs to be split. Therefore, the induced signal on the secondary side 1005 is passed to the interpretation module 1023 which extracts the first control signal 1017 and interprets it.

The interpretation module 1023 includes an inductive transformer with an LC filer 1 0 47. This is used for separating the first control signal 1017 from the power signal and the second control signal.

The inductive transformer 1047 includes a first coil 1047a in series with the secondary coil 1011 of the system and a second inductive transformer 1063 (discussed below in more detail), and a second coil 1047b in series with a filter 1049a of the interpretation module 1023.

The capacitor of the LC filter 1047c is connected across the first coil 1047a of the inductive transformer 1047. As discussed above, the lower frequency signal, with frequency fp is the power signal, and the higher frequency signal, with frequency fel is the first control signal. The LC filter is selected to isolate the frequency of the first control signal 1017.

The separated control signal is now passed through a band pass filter and amplifier sub-module 1049 having filter 1049a and amplifier 1049b. Thc filter is a first order narrow band pass filter used to isolate the carrier frequency of the first control signal. This generates a signal corresponding to the first control signal 1017, having four different voltage levels.

Figure 6 illustrates an example of the signal 1045c induced at the secondary coil 1011, with the first control signal superimposed. Figure 6 is the output from the filter 1049a and amplifier sub-module 1049b. As in Figure 5A, this includes regions 1045b', 1045b", 1045b". 1045b" in which the first control signal adopts different values: 00, 01, 10 & 11 respectively.

The signal is then passed through a comparator sub-module 1051 having comparators for detecting the four different voltage levels. A logic sub-module 1025 having logical gates is then used to convert the voltage detected at the comparator sub-module 1051 into two separate binary logic values representing the data signal 1019a and dock signal 1019b respectively. These are fed to the secondary processor 1027 which is used to control the operation of the load 1007.

For providing power to the load 1007 the induced signal may be changed back from AC to a DC using a full wave rectifier 1053 followed by a capacitive filter circuit 1055. Some applications may call for AC operating currents and so this can be omitted. Furthermore, a voltage regulator 1057 may optionally be provided to fix the voltage on the secondary side to work with the load 1007 accordingly.

The second control signal 1029 is generated in thc secondary sidc of thc circuit 1005. Since the secondary processor 1027 is operating as a follower, the second control signal 1029 includes only a data component. There is no clock component. As with the primary processor 1015, the output of the secondary processor is inverted by an inverter 1115.

As with the primary control signal, the second control signal 1029 is generated from a digital data signal 1029' . In one example, the digital data signal 1029' is generated by inverting the data output 1079 of the secondary processor 1027. In a similar fashion to the primary side 1001 of the system, the two data signals 1019a, 1079 are provided on a single line in the secondary side 1027.

As with the first control signal 1017, the signal 1029' is modulated onto a second carrier signal of frequency ft, to generate the second control signal 1029 by a modulation module 1059. In the example being discussed, Amplitude-Shift Keying Modulation (ASK) is again used, with carrier frequency of fc2 = 8 MHz. The carrier frequency of the second control signal 1029 is different to the carrier signal for the first control 1017 signal to allow the separate control signals 1017, 1029 to be distinguished. The modulated carrier signal is also amplified by amplifier 1061.

As with the superimposing of the first control signal 1017, the second control signal is superimposed onto the signal at the secondary coil 1011 using an inductive transformer 1063 including an LC filter. A first coil 1063a of the transformer 1063 is connected in series with the amplifier 1061 for amplifying the second control signal 1029. A second coil 1063b is connected in series with the secondary coil 1011 of the wireless power transfer system 1000 and also with the first coil 1047a of the inductive transformer used to isolate the first control signal 1017. Therefore, two inductive transformers 1047, 1063 are connected in series with the secondary coil 1011 of the system 1000.

The LC filter 1063c of the second inductive transformer on the secondary side 1005 is formed by the second coil 1063b of the inductive transformer 1063 and a capacitor connected across the second coil 1063b. The filter is a bandpass filter centred on the carrier frequency of the second control signal (fc)) and removes the carrier frequency of the power signal and the first control signal.

The second inductive transformer 1063 on the secondary side 1005 allows the second control signal 1029 to be superimposed on top of the power signal.

The second inductive transformer 1063 on the secondary side 1005 is selected to provide a significant difference between fe, and f,, in order to minimise the interferences and allow for easier separation of signal into constituent components on the secondary side.

Figure 7A illustrates an example of a signal 1065 at the secondary coil 1011. The signal 1065 includes a first region 1065a in which there is only the power signal, second regions 1065b in which the first control signal 1017 is superimposed and third regions which shows the power signal together with both first and second control signals 1017, 1029 superimposed. Figure 7B shows a dose up of a region 1065c including both control signals 1017, 1029 superimposed.

in a similar manner to the isolation of the first control signal on the secondary side 1005 of the system 1000, the primary side 1001 of the system 1000 includes a second inductive transformer with LC filter 1067 in order to isolate the second control signal.

The second inductive transformer 1067 on the primary side 1001 includes a first coil 1067a in series with the primary coil 1009 of the system. This is also in series with the second coil 1043b of the first inductive transformer 1043 on the primary side 1001, used on superimpose the first control signal 1017.

The second inductive transformer 1067 on the primary side 1001 includes a second coil 1067b in series with an interpretation module 1071 used to analyse and interpret the second control signal 1029.

The capacitor of the LC filter I067c is connected across the first coil 1067a of the inductive transformer 1067. The LC filter is selected to isolate the frequency of the second control signal 1029.

The separated second control signal is now passed through a band pass filter and amplifier sub-module 1071 having filter 1071a and amplifiers 1071b. The filter is a second order narrow band pass filter used to isolate the carrier frequency of the second control signal This generates a signal corresponding to the second control signal 1029.

The signal is then passed through a comparator sub-module 1073. In the current example, since the second control signal 1029 includes a data portion only, the data signal is a binary signal having only a high or low value. Thus, only a single comparator is required. The determined high (1) or low (0) value is fed to the primary processor 1015. As shown in Figure 3A, a single line is provided for the two control signals 1019a, 1079 on the primary side 1001 of the system 1000.

Any type of bidirectional communications may be achieved using the above system. For example, there may be full combinations in both directions. In another example that will now be discussed in detail by way of example only, the first control signal 1017 may comprise commands for controlling the operation of the load 1007, and the second control signal may comprise an acknowledge signal in a leader/follower relationship, the follower processor (secondary processor 1027) may need to send an acknowledge signal to leader processor (primary processor 1015) after each 8 bits is correctly received, to confirm successful instruction delivery.

The acknowledge signal should be transmitted in the correct timing window and is treated in the same manner as the second control signal 1029 discussed above (i.e. modulated onto a carrier frequency f02).

Figure 8 illustrates a communications window for sending two bytes I089a, I089b of data from the primary processor 1015 to the secondary processor 1027 using the 12C communications protocol. Figure 8 shows the data output 1019a and clock output 1019b from the primary processor 1015 and the data output 1079 from the secondary processor 1027 before inversion and digital signal 1029' used to generate the second control signal (which is generated by inversion of the data output 1079 of the secondary processor 1027). For the sake of illustration, any effects from inverting the primary processor data signal 1019a or clock signal 1019b are removed.

Within the VC protocol,: -The start of the communication sequence 1091 is indicated by the clock signal 1019b being in a high (1) state (or low state after inversion), and the data signal 1019a from the primary processor 1015 (transmitting device) falling to the low (0) state (or rising to a high state after inversion).

The end of the communication sequence 1093 is indicated by the clock signal 1019b being in a high state (or low state after inversion), and the data signal 1019a rising to a high state (or falling to a low state after inversion).

Between these start and end points, a number of bytes of data can be transmitted. Each bit of the byte is transmitted by the data output 1019a of the primary processor. Any change in data state from high to low or low to high can only take place when the clock signal is low (0) (or high after inversion). The value of each bit is the value of the data output 1019a when the clock is in the high state (or low after inversion).

Aftcr each byte is transmitted, an acknowledge signal 1095a, 1079 is transmitted by the secondary processor 1027. The acknowledge signal is transmitted as the data output 1079 of the secondary processor 1027 during the acknowledge window 1095b. To do this, the data output 1079 of the secondary processor 1027 is changed to low while the data component 1019a from the primary processor 1019a is high.

At the moment the 8111 bit has been received, the clock turns to the low state (high after inversion) and the data output from the secondary processor changes from high to low (start of the acknowledge pulse). On the next low state of the clock signal 1019b, the data output from the secondary processor 1027 changes back to the high state as the end of the acknowledge pulse. This switch back to the high state is within a fixed time period of the change of the clock signal 1019b, for example within 1011s. This fixed time period forms the acknowledge window. Therefore, for each byte of data, the system implements a 9 bit cycle.

If this acknowledge change is mistimed, either the data output from the secondary processor going from low to high or from high to low may occur when the clock signal is in the high state. In this case the microcontroller interprets this as either start of communication or end of communication and so causing the program to crash.

To ensure correct timing, three counters 1077a, 1077b, 1077c may be implemented in a detection module 1075 which monitors the data signal transmitted by the first processor 1015. and the data output from the secondary processor 1027. The counters detect the acknowledge window, and if the correct output from the secondary processor 1027 is received, generates an output to transmit back to thc primary processor 1015. Figure 10 illustrates the arrangement of the counters 1077a, 1077b, 1077c in more detail.

Each counter is implemented as a logic device which can have an output that is low or high. Each counter 1077a, 1077b, 1077c has a first input (CLK) and a second input (MR), and four outputs nQO to nQ3 (where n is the counter number). Each counter follows the same truth table shown in table 2 below First input (CLK) Second input (MR) Output state I 0 No change Falling 1 to 0 0 increment counter Rising 0 to 1 0 No change 0 0 No change X I Outputs QO to Q3 to 0

Table 2

For each counter, the total counted is indicated by the value of the four outputs as indicated in table 3: Total counted QO Qt Q2 Q3 0 0 0 0 0 1 1 0 0 0 2 0 1 0 0 3 1 1 0 0 4 0 0 1 0 ) 1 0 1 0 6 0 1 1 0 7 1 1 1 0 8 0 0 0 1 9 1 0 0 1

Table 3

The first counter 1077a detects the start of a communication window by monitoring the data signal 101 9a and clock signal 1019b received from the primary processor 1015. The data signal is provided to a first input (CLK) 1097a of the first counter and the clock signal is provided to a second input 1097b (MR), through an inverter 1099. Therefore, when, the clock signal 10 I 9b is high and the data signal 10I9a is falling from high to low, the first counter increments according to table 2. This causes the first output (1Q0) 1109 of the first counter 1107a to change to high, as in table 3, and indicates the start of the communication window.

Figure 8 shows the output 1109 of the first counter 1077a.The first output 1109 of the first counter I 077a is connected to the second input 1101b (MR) of the second counter 1077b. As indicated in table 2, when the second input 110 lb is high, all outputs of the second counter 1077b are reset to 0, effectively resetting the second counter 1077b.

The first input (CLK) 1101a of the second counter 1077b is connected to the clock signal 1019b. On the next change of the dock signal 1019b, the first counter will reset until the next start of a communications window is detected. This will cause the first output (1Q0) 1109 to return to low. Therefore, according to table 2, each change of the subsequent changes in the dock (including the one that causes the first counter I077a to reset) will cause an increment in the second counter 1077b, changing the outputs according to table 3 Figure 8 shows the first output (2Q0) 1111a. second output (2Q1) 1111c, third output (2Q2) 1111d and fourth output (2Q3) III lb of the second counter 1077b. Furthermore, at the top of Figure 8, the total count from the second counter 1077b is shown.

The first output (2Q0) 111 la and fourth output (2Q3) 1111b of the second counter I077b are connected to an AND gate 1103. Thus, when both 2Q0 and 2Q3 are high (which only occurs once the counter reaches 9) the output of the AND gate 1103 switches to high.

The output of the AND gate 1103 is coupled to the second input 1101b of the second counter. Thus, according to table 2, when the output of the AND gate 1103 switches to high second counter reaches 9, the second counter 1077b resets.

The output of the AND gate 1103, and the first output (1Q0) 1109 of the first counter 1077a are connected to the second input 1101b of the second counter by an OR gate 1105. Thus, either condition (detecting the start of a window or the second counter reaching 9) resets the second counter 1077b).

The first input (CLK) 107a of the third counter I 077c is connected to the fourth output (2Q3) 1111b of the second counter 1077b and the second input (MR) 1107b of the third counter I077c is connected to the first output (2Q0) liiia of the second counter 1077b). 5 On receipt of the eighth bit, the fourth output (2Q3) 1111b of the second counter 1077b changes to 0 and the first output (2Q0) III la of the second counter 1077b falls from 1 to 0. This causes an increment of the third counter I 077b. Therefore, the first output (3Q0) 1113 of the third counter 1077c changes to a high state (1). Figure 8 shows the signal from the first output (3Q0) 1113 of the third counter 1077c.

The first output (3Q0) 1113 of the third counter I 077c is connected to a first input of another AND gate 1117 (see Figure 3B). The second input of the AND gate 1117 is connected to the inverter 1115 on the data output 1079 of the secondary processor 1027. I5

The default data output signal 1079 of the secondary processor 1027 is a high state (1), which is inverted to a low state (0) by the inverter 1115. When the acknowledge signal is sent, the data output signal 1079 changes to a low state (0), which is inverted to a high state (1) by the inverter 1115.

Therefore, when the acknowledge signal is sent, both inputs to the AND gate 1117 are high, this changes the output of the AND gate to a high state (1) which is transmitted as the digital signal 1029' used to generate the second data control signal 1029. Thus it may be considered that when the first output (3Q0) 1113 of the third counter 1077c is high, this indicates the window for receiving the acknowledge signal and the detection module 1075 is able to detect and output the acknowledge signal, indicating the successful receipt of the previous byte of data.

On receipt of the next bit (which is the ninth bit in the cycle), the first and fourth outputs 1111a, 1111b of the second counter 1077b are high. As discussed above, this resets the second counter 1077b and also returns the first output 1113 of the third counter to a low state (0) until the next acknowledge window. In order to achieve this timing, the primary processor inserts a single dummy bit between each byte of data.

In the above example, the coils 1009, 1011 are stationary. However, it will be appreciated that in some cases, one or both of the coils 1009, 1011 may be rotated about an axis extending perpendicular to the plane in the which the coils 1009, 1011 are formed. Rotation may also be around any other suitable axis, provided the coils 1009, 1011 maintain sufficient air or vacuum gap to allow inductive transfer of signals.

The primary side circuit 1001 and secondary side circuit 1005 may be implemented in any suitable way. in one embodiment, at least part of the primary circuit 1001 may be formed on a printed circuit board (PCB) (not shown) with surface mount components.

Connections between the components may be via conducting tracks, wires or other connections. Further intervening components for other treatment of the signals may also be included.

Similarly, the secondary circuit 1005 may also be formed on a PCB in the same manner. 15 All of the primary circuit 1001 may be formed on a single PCB or may be distributed across multiple PCBs. Likewise, all of the secondary circuit 1005 may be formed on a single PCB or distributed across multiple PCBs. Some components may be formed separately and mounted independent from the PCB. For example, the coils 1009, 1011 may be formed away from the PCB.

The use of the PCB is by way of example only. The circuits 1001, 1005 may be formed and mounted in any suitable way.

Figures 9A and 9B illustrate examples of the coils 1009, 1011, in cut-through side view.

Each coil 1009, 1011 is formed by a wire 1081 wound around a central axis 1087. In the example shown, the coils 1009, 1011 are planar, in a plane perpendicular to the central axis 1087. However, this is by way of example only. The coils may also be of any shape when viewed end on, such as circular, elliptical, square or the like.

In some examples, a single wire 1081 forms each coil, but in other examples, multiple wires 1081 may be used. The wire 1081 in the primary and secondary coils 1009, 1011 will be made of any suitable conductive material for wireless power transfer and may be of any suitable gauge. The coils may have any suitable number of windings with any suitable density of windings.

In a first example, shown in Figure 9A, the coils 1009, 1011 may be continuous from the central axis 1087 to the outer perimeter. In a second example, shown in Figure 9B, the coils may be annular, with a central aperture 1083 formed along the central axis 1087. It is also possible to use coils of different type (wining, size, etc) for either primary or secondary sides.

Optionally, in order to improve the inductive transfer between the coils 1009, 1011, a cylindrical ferrite core 1085 may extending through the aperture 1083, between the two coils 1009, 1011. The ferrite core 1085 has a central axis extending along a direction perpendicular to the coils 1009, 1011, and passes through the aperture 1083 formed in both coils 1009, 1011. The ferrite core 1085 may be hollow with closed ends. hollow with open ends (to allow passage of other components) or solid.

Any suitable processor or microprocessor may be used as the primary processor 1015 and secondary processor 1027. For example, the primary processor may be a processor from a Raspberry Pi, or any other suitable type of processor. The primary processor 1015 and the secondary processor 1027 may be a LED Driver, motor diver, sensor, or any type of microprocessors or microcontrollers.

The load 1007 could be any suitable load. In one example, the load may comprise an LED driver circuit, but this is by way of example only. The power transferred from the primary cod 1009 to the secondary cod 1011 could be used to power any suitable component. This could be formed with the secondary circuit 1005 or separately.

The secondary circuit 1005 may directly power the load 1007. Alternatively, a battery or capacitor may be provided to store power received. There may also be a combination of direct supply when required, with a battery arranged to store power when direct power is not required.

In the system discussed above, the following frequencies are used: The frequency of the data signal 101 9a from the first processor 1015 The frequency of the data signal from the second processor 1027 The frequency fd of the clock signal 1019b.

The frequency fp of the power signal.

-The frequency f0i of the carrier signal for the first control signal 1017.

-The frequency fo, of the carrier signal for the second control signal 1029.

The frequencies and ranges discussed above, are given by way of example only. In order to allow the first and second control signals 1017, 1029 to be discerned, the carrier signals should have different frequencies to each other and to the power signal.

In order to achieve efficient power transfer, the power signal may be the lowest frequency and highest amplitude out of the power signal and the two carrier signals.

In order to improve detectability of the control signals, the frequency of the carrier signals may be one or more orders of magnitude higher than the power signal. Furthermore, the frequency of the carrier signals may be several times the frequency of the data signal (and clock signal) output from the processors 1015, 1027.

In the example discussed above, the frequency fc2 of the carrier signal for the second control signal 1029 is the highest frequency, but this is by way of example only. The amplitude of the two carrier signals may be the same or may be different to improve detectability. For example, the highest frequency signal may have the lowest amplitude.

In the example discussed above, the primary processor 1015 acts as a leader and the secondary processor 1027 acts as a follower. This means that the secondary processor 1027 is synchronised to the primary processor's clock signal 1019b. However, this is by way of example only. In some cases, the secondary processor 1027 may act as the leader. In this case, the second side 1005 of the system 1000 may include the combination module 1021 to combine the data signal and clock signal. In some cases, both sides may include a combination module 1021 to allow either side to be selected as the leader.

The power source 1003 may be an AC power source, in which case the power n erter 1041 is not required.

In the example discussed above, the output of the primary processor 1015 and secondary processor 1027 arc inverted. This is by way of example only. The output of one or both of the processors 1015, 1027 may not be inverted in some embodiments.

The interpretation modules 1023, 1069 discussed above are by way of example only. Any suitable way to separate and analyse the control signals 1017, 1029 from the power signals may be used In the examples discussed above, the binary values of the data signal 1019a and clock signal 1019b are combined into a single signal with four different voltage levels. Any suitable method can be used to combine the signals, for example, for different current values, or four different frequency values may be used.

Furthermore, any suitable modulation scheme may be used to modulate the carrie frequencies with the data information on both the primary and secondary side.

The counter discussed is given by way of example only. Any suitable counters may be used for synchronisation of communications.

In the above example, communication under the 12C protocol has been discussed. However, any suitable communication protocol can be used. In some communication protocols, synchronisation of the processors 1015, 1027 may not be required. In this case, there may be no need to combine a data signal 101 9a and clock signal 101 9b at the leader side of the system 1000. Counters may not be necessary in other communication protocols are they may be replaced with alternative solutions It will be appreciated that various parameters of the system, such as the frequencies discussed above, the number of turns in the coils 1009, 1011, the power source 1003, the presence (or not) of the rectifier 1053 and voltage regulator 1057 on the secondary side 1005 and the voltage provided by the regulator 1057 and any other circuit components can be tuned to achieve any desired power at the load 1007, based on end user requirements.

Claims

Claims 1. A wireless power and data transfer system comprising: a primary coil arranged to transmit a power signal having a first frequency; a secondary coil arranged to receive the power signal from the primary coil by wireless induction; a primary side circuit arranged to superimpose a first control signal onto the power signal between the coils at the primary coil, the first control signal having a second frequency different to the first frequency; and a secondary side circuit arranged to superimpose a second control signal onto the power signal between the coils at the secondary coil, the second control signal having a third frequency different to the first frequency and second frequency. I52. A wireless power and data transfer system as claimed in claim 1, wherein: the primary side circuit comprises a primary filter arranged to isolate the second control signal at the primary coil; and the secondary side circuit comprises a secondary filter arranged to separate the power signal and the first control signal at the secondary coil.A wireless power and data transfer system as claimed in claim 2, wherein the primary filter and/or the secondary filter comprise inductive transformers with LC filters.A wireless power and data transfer system as claimed in any preceding claim, wherein one of the first control signal and the second control signal encodes a clock component and a data component, and the other of the first control signal and the second control signal encodes a different data component A wireless power and data transfer system as claimed in claim 4, wherein the one of the first control signal and the second control signal that encodes a clock component comprises a logic signal able to adopt a plurality of different logic values, each logic value corresponding to a unique combination of the values of the data component and the clock component.A wireless power and data transfer system as claimed in claim 4 or claim 5, wherein the data components and the clock component each comprise a binary logic signal have having a low value and a high value, such that the one of the first control signal and the second control signal that encodes a clock component and a data component adopts one of four possible logic values.7 A wireless power and data transfer system as claimed in any of claims 4 to 6, comprising: a combination module arranged to combine the clock component and data component into a single signal.I5 A wireless power and data transfer system as claimed in any preceding claim, wherein the first control signal and/or the second control signal comprise a modulated signal through a carrier signal according to encode the control signal.9. A wireless power and data transfer system as claimed in claim 8, wherein the control signal is modulated by amplitude modulation, optionally using amplitude-shift keying modulation.10. A wireless power and data transfer system as claimed in claim 8 or claim 9, comprising: a modulation module arranged to modulate the control signal.A wireless power and data transfer system as claimed in any preceding claim, wherein the first frequency is lower than the second frequency and the third frequency.12. A wireless power and data transfer system as claimed in claim 11, wherein the amplitude of the power signal is greater than the amplitude of the first control signal and the second control signal.13. A wireless power and data transfer system as claimed in any preceding claim, wherein: the primary side circuit comprises a primary inductive transformer to superimpose the first control signal; and the secondary side circuit comprises a secondary inductive transformer to superimpose the second control signal.14. A wireless power and data transfer system as claimed in any preceding claim, comprising: the primary side circuit comprises a primary processor arranged to generate the first control signal and receive the second control signal; and the secondary side circuit comprises a secondary processor arranged to generate the second control signal and receive the first control signal.A wireless power and data transfer system as claimed in claim 14, wherein the first control signal comprises instructions sent from the primary processor to the secondary processor, and the second control signal comprises an acknowledge signal, confirming successful transmission of at least a portion of the first control signal.A wireless power and data transfer system as claimed in claim 15, comprising: a first counter arranged to detect a start of a communication window; a second counter arranged to count a number of bits received; and a third counter arranged to detect the window for the acknowledge signal.A wireless power and data transfer system as claimed in any of claims 14 to 16, comprising: a primary inverter to invert the output of the primary processor; and/or a secondary inverter to invert the output of the secondary processor.A wireless power and data transfer system as claimed in any preceding claim, wherein one or both of the primary coil and secondary coil is arranged to rotate about its central axis. I5 15. 16. 17. 18.19. A wireless power and data transfer system as claimed in any preceding claim, wherein the primary coil and secondary coil each comprise an aperture arranged in the coil, and wherein the wireless power and data transfer system comprises a core extending through the opening between the primary coil and the secondary coil 20. A wireless power and data transfer system as claimed in claim 19, wherein the core is hollow, thereby allowing components or cabling to be passed through the centre of the coils.21. A wireless power and data transfer system as claimed in claim 19 or claim 20, wherein the core is a ferrite core.22. A method of wireless power and data transfer, comprising: I5 transmitting a power signal from a primary coil to a secondary coil by wireless induction; superimposing a first control signal onto the power signal at the primary coil; and superimposing a second control signal onto the power signal at the secondary coil, wherein the power signal has a first frequency, the first control signal has a second frequency different to the first frequency and the second control signal has a third frequency different to the first frequency and the second frequency.23. A method as claimed in claim 22, comprising: filtering the signal induced at the secondary coil to isolate the first control signal; and/or filtering the signal induced at the primary coil to isolate the second control signal.24. A method as claimed in claim 22 or claim 23, comprising: generating one of the first control signal and the second control signal by combining a clock signal from a processor and a data signal from the processor.25. A method as claimed in claim 24, wherein the one of the first control signal and second control signal comprises a logic value encoding a clock component and a data component.