GB2594668A

GB2594668A - Detector and method for measuring a resistance of a variable resistance sensor while resistance varies with respect to a time-varying stimulus

Info

Publication number: GB2594668A
Application number: GB2111044.0A
Authority: GB
Inventors: Jay Peterson Cory; B Prakash Chandra; Ilango Anand; Zanbaghi Ramin; Wang Dejun
Original assignee: Cirrus Logic International Semiconductor Ltd
Current assignee: Cirrus Logic International Semiconductor Ltd
Priority date: 2019-08-02
Filing date: 2020-07-28
Publication date: 2021-11-03
Anticipated expiration: 2040-07-28
Also published as: GB2587902B; GB2594668B; GB2587902A; GB202011696D0; GB202111044D0

Abstract

A variable resistance sensor (VRS) circuit includes a first sensed voltage Vsns generated as a product of a first voltage reference Vref and an unknown scalar, a second sensed voltage generated as a product of the first voltage reference and a known scalar, and an amplifier having gain error that generates a second voltage reference (first voltage reference or scaled version thereof). An ADC uses the second voltage reference Vrefsc to generate first and second digital values, representing the first and second sensed voltages, that contain error caused by the second voltage reference gain error. A processor uses the known scalar and a ratio based on the first and second digital values to remove the error from the first digital value. The first sensed voltage may be generated by pumping a current, e.g. from a linearised DAC (LIDAC), into a variable resistance sensor (VRS) whose resistance varies with respect to a time-varying stimulus (e.g. temperature) and is proportional to the unknown scalar.

Description

DETECTOR AND METHOD FOR MEASURING A RESISTANCE OF A

VARIABLE RESISTANCE SENSOR WHOSE RESISTANCE VARIES

WITH RESPECT TO A TIME-VARYING STIMULUS

BACKGROUND

100011 There are many scenarios where it is essential to accurately detect a resistance of a sensor whose resistance varies over time. For example, the resistance of a photoresistor varies according to the intensity of light to which the photoresistor is exposed. Thus, to measure light intensity using a photoresistor, an accurate detector is needed to measure its resistance with minimum error. For another example, the resistance of a pressure sensor may vary according to the amount of pressure applied to it. Thus, to measure pressure using a pressure sensor, an accurate detector is needed to measure its resistance with minimum error. For another example, a thermistor is a device that exhibits precise change in its resistance value with respect to its ambient temperature. Thus, to measure temperature using a thermistor, an accurate detector is needed to measure its resistance with minimum error. There are many scenarios where maintaining an accurate light intensity, pressure, temperature, etc. is essential for quality control, e.g., in medical, automotive, petrochemical, aerospace, consumer electronics, and other applications.

SUMMARY

100021 In one embodiment, the present disclosure provides a detector for measuring a resistance of a variable resistance sensor (VRS), wherein the resistance of the VRS varies with respect to a time-varying stimulus, includes a voltage reference having variation with respect to operating conditions, and a linearized digital-to-analog converter (LIDAC) having a known transconductance that uses the voltage reference to generate a current for pumping into the VRS to cause the VRS to generate a voltage sensed by the detector. The sensed voltage includes error due to the variation of the voltage reference. The detector also includes a programmable gain amplifier (PGA) that gains up the sensed voltage to generate an output signal, an analog-to-digital converter (ADC) that converts the output signal to a digital value, and a digital processor that computes the resistance of the VRS using the digital value and the known transconductance.

[0003] In another embodiment, the present disclosure provides a method for measuring a resistance of a variable resistance sensor (VRS), wherein the resistance of the VRS varies with respect to a time-varying stimulus. The method includes generating a voltage reference having variation with respect to operating conditions, using, by a linearized digital-to-analog converter (LIDAC) having a known transconductance, the voltage reference to generate a current, and pumping the current into the VRS to cause the VRS to generate a sensed voltage. The sensed voltage includes error due to the variation of the voltage reference. The method also includes gaining up, by a programmable gain amplifier (PGA), the sensed voltage to generate an output signal, converting, by an analog-to-digital converter (ADC), the output signal to a digital value, and computing the resistance of the VRS using the digital value and the known transconductance.

[0004] In another embodiment, the present disclosure provides a system that includes a first sensed voltage generated as a product of the first voltage reference and an unknown scalar, a second sensed voltage generated as a product of the first voltage reference and a known scalar, and an amplifier that generates a second voltage reference. The amplifier has a gain error. The system also includes an analog-to-digital converter (ADC) that uses the second voltage reference to generate first and second digital values representing the first and second sensed voltages, respectively. The first and second digital values contain error caused by the gain error of the second voltage reference. The system also includes a digital processor that uses a ratio based on the first and second digital values to remove the error from the first digital value.

[0005] In another embodiment, the present disclosure provides a method for removing error in a system having an analog-to-digital converter (ADC) that includes generating a first sensed voltage that is a product of a first voltage reference and an unknown scalar, generating a second sensed voltage that is a product of the first voltage reference and a known scalar, and using, by the ADC, a second voltage reference to generate first and second digital values representing the first and second sensed voltages, respectively. The second voltage reference has gain error and the first and second digital values contain error caused by the gain error of the second voltage reference. The method also includes using a ratio based on the first and second digital values to remove the error from the first digital value.

BRIEF DESCRIPTION OF THE DRAWINGS

100061 FIGURE 1 is a circuit diagram illustrating an example of a system having a variable resistance sensor (VRS) and a detector for detecting the resistance of the VRS in accordance with embodiments of the present disclosure.

[0007] FIGURE 2 is a circuit diagram illustrating an example of a linearized DAC such as the LIDAC of Figure 1 according to embodiments of the present disclosure.

100081 FIGURE 3 is a circuit diagram illustrating an example of a dual-input programmable gain amplifier PGA according to embodiments of the present disclosure. [0009] FIGURE 4 is a flowchart illustrating an example of a method for removing error in a digital output generated by an ADC system such as the detector of Figure 1 according

to embodiments of the present disclosure

DETAILED DESCRIPTION

[0010] Embodiments of a resistance detector with ultra-low error are described.

100111 Figure 1 is a circuit diagram illustrating a system 10 having a variable resistance sensor (VRS) and a detector 14 for detecting the resistance RWS of the VRS in accordance with embodiments of the present disclosure. The resistance Rviis of the VRS varies with respect to a time-varying stimulus, e.g., temperature, pressure, voltage, light, location (e.g., location of a touch on a touchscreen), or combination thereof The VRS may be any material or device whose resistance varies with respect to a time-varying stimulus, e.g., negative/positive temperature coefficient (NTC/PTC) resistor, photoresistor, pressure sensor, thermistor, voltage-varying resistance, touchscreen (e.g, gridded screen whose resistance varies with location on the grid of user touch). In one embodiment, the detector 14 is integrated onto one or more integrated circuits. In one embodiment, the VRS is located external to the one or more integrated circuits that comprise the detector 14, as shown in Figure 1. Thus, the detector 14 may be employed as a remote resistance detector, e.g., remote temperature sensor. In such an embodiment, a pin may be attached at each terminal of the VRS, shown in Figure 1 as pin P+ and pin P-. Pin P-may be connected to ground. The pins may be used to pump VRS current Linke and sense voltage VsNs. In an alternative embodiment, the VRS is located on the same integrated circuit that comprises the detector 14.

[0012] The detector 14 includes a linearized current digital-to-analog converter (LIDAC), an anti-aliasing filter (AAF), a programmable gain amplifier (PGA), an analog-to-digital converter (ADC), an amplifier (AMP), a comparator (CON1P), and a digital processor (DP). The L1DAC generates a current ILTDAc that is pumped into the VRS. The current UEDAE through the VRS generates a voltage VsNs across the VRS that is sensed by the AA F and the comparator COMP. The detector 14 uses the sensed voltage VsNs to detect 5 the resistance RvRS of the VRS, which may vary over time with respect to the time-varying stimulus. The detected resistance may be used to calculate other quantities related to the VRS, e.g., temperature, pressure, light intensity, voltage, touch location. Advantageously, the detector 14 employs various aspects to detect the time-varying resistance RVRS of the VRS with high accuracy, low temperature sensitivity, relatively 10 low chip area and power consumption.

[0013] The detector 14 generates a voltage reference VREF. In one embodiment, voltage reference VREF is a bandgap voltage reference. In one embodiment, voltage reference VREF has a value of approximately 0.7 Volts. Amplifier AMP amplifies voltage reference VREF to generate an ADC voltage reference VREFADc used by the ADC to convert an output VOur of the PGA to a digital value DADC. In one embodiment, the gain L of amplifier AMP is two. Amplifier AMP may have gain error and/or offset error due to operating conditions, e.g., mechanical stress, process, voltage and/or temperature variation. Therefore, amplifier AMP may introduce error in ADC voltage reference VREFADC, which may introduce error into the digital values generated by the ADC.

Advantageously, the error may be minimized by using a ratio of digital values generated by the ADC, as described in more detail below, e.g., with respect to Figure 4.

[0014] Additionally, the LIDAC uses voltage reference VREF to generate a reference current 'REF (see Figure 2) that the L1DAC uses to generate the VRS current ILIDAC. Because the L1DAC is linearized, a transconductance G, which is the ratio of the VRS current ILTDAc to the voltage reference VREF, is known and is advantageously used to remove error that would otherwise be present in the measurement of the resistance Rws of the VRS, as described in more detail below. The L1DAC also uses voltage reference VREF to generate a scaled voltage reference VREFSC that is provided to multiplexing circuitry MUX and to comparator COMP. An embodiment of the L1DAC is described in more detail below with respect to Figure 2. Voltage reference VREF may also have variation due to operating conditions. The variation may introduce error into signals that use voltage reference VREF, e.g., ADC voltage reference VREFADE and scaled voltage reference Vithrsc. However, embodiments of the detector 14 are described that advantageously significantly remove the error introduced by the variation to detect the resistance RvRs of the VSR with low error.

[0015] The AAF filters the sensed voltage VSNS to generate an anti-alias-filtered voltage VAm. In one embodiment, the AAF includes a resistor-capacitor network connected to ground at pin P-that operates as a low-pass filter on sensed voltage VsNs. In one embodiment, the LIDAC accomplishes linearity using high-frequency switching, e.g., dynamic element matching (DEM), and the AAF advantageously attenuates the upconverted errors by the DENI and therefore improves accuracy of the sensed voltage VsNS signal into the desired signal band, e.g., 40 kHz range. The anti-alias-filtered voltage VAAF is provided as a second input to the multiplexing circuitry MUX. The output of the multiplexing circuitry MUX (i.e., either the scaled voltage reference VREFSC or the antialias-filtered voltage VAAF) is provided to the PGA. Operation of the multiplexing circuitry MUX is described in more detail below, e.g., with respect to Figure 3.

[0016] The PGA gains up the scaled voltage reference VREFSC or the anti-alias-filtered voltage VAAF selected by the multiplexing circuitry MUX to generate an output voltage V0uT that is sensed by the ADC and converted to the digital value Dc using the ADC voltage reference VREFADc. Preferably, the PGA is effectively non-varying with respect to the time-varying stimulus that varies the resistance RvRs of the VRS. The PGA scales up the sensed voltage VsNs to near the full scale of the ADC, i.e., to occupy the entire dynamic range of the ADC. This may advantageously enable use of a relatively low resolution, small and low power-consuming ADC while still providing relatively low quantization error.

[0017] The digital processor DP generates a digital current value DuDAC provided as an input to the LIDAC that controls the value of the VRS current ILIDAc that is pumped into the VRS to generate sensed voltage VsNs. More specifically, the digital current value DuDAC is a multiplier of a unit current IL513 (see Figure 2) generated within the LIDAC using the reference current 'REF (see Figure 2). The resistance of the VRS and therefore its sensed voltage VSNS may vary widely. At initialization, i.e., when the detector 14 begins being used to measure the resistance RvRs of the VRS, the comparator COMP compares the sensed voltage VsNs with scaled voltage reference VREFSC and provides a result of the comparison to the digital processor DP. The digital processor DP uses the result of the comparison to generate a digital current value DLIDAc that causes the value of sensed voltage VsNs (and therefore anti-alias-filtered voltage VAALF) to be close to a target voltage, e.g., near scaled voltage reference VafFsc. Preferably, the target voltage is kept relatively low (e.g., 0.35 Volts in one embodiment) in order to avoid self-heating effects of the VRS that may affect accuracy of the detection of its resistance. However, a low voltage input to the ADC might require a higher resolution ADC to lower error caused by quantization noise. Therefore, advantageously, the PGA scales up the target voltage, e.g., anti-alias-filtered voltage VAAF, in order to make the most use of the dynamic range of the ADC, as described in more detail below, thereby enabling employment of a lower resolution ADC to obtain a comparable quantization error level. 100181 In one embodiment, the ADC is a successive approximation register (SAR) ADC.

The digital processor DP outputs the digital ADC value DADC to the SAR ADC. The SAR ADC uses the digital ADC value 1130Anc to internally generate an analog voltage using the ADC voltage reference VREFADC. The SAR ADC responsively generates a match indicator to the digital processor DP. The match indicator indicates whether the internally generated analog voltage matches the output voltage Vout, is higher than the output voltage Vou r, or is lower than the output voltage Vout. In response to the match indicator, the digital processor DP successively provides different values of the digital ADC value DADc, preferably in a binary search fashion, until a match is indicated. The final digital ADC value DADC corresponds to the digital value of the output voltage VOLT, which is a gained-up version of either scaled voltage reference VREFSC or anti-alias-filtered voltage VAAF depending on the selection made by the multiplexing circuitry NIUX.

100191 Figure 2 is a circuit diagram illustrating a linearized DAC (e.g., LIDAC of Figure 1) according to embodiments of the present disclosure. The LLDAC includes an operational transconductance amplifier (OTA) OTA1, a p-channel MOSFET, two series resistors of equal value RTAN, and first and second segments SEG1 and SEG18. In one embodiment, the resistors RYAN are tantalum nitride resistors whose resistance is highly temperature-insensitive. The gate of the MOSFET is connected to the output of OTA1. The source of the MOSFET is connected to supply, and the drain of the MOSFET is connected to the inverting input of OTA1, which is also connected to the resistors RrAN, which are connected to ground at pin P-. OTA1 and the MOSFET operate to generate reference current 'REF that is provided to the LIDAC. In the embodiment of Figure 2, the value of reference current 'REF is equal to voltage reference VREF / (2 * RTAN) by virtue of negative feedback action. The known scalar quantity that is the ratio of voltage reference VREF and scaled voltage reference VREFsc may be used to ratiometrically remove error from the measurements made using the ADC as described in more detail below.

[0020] The fact that the LIDAC is linearized means it has de minimis quantization error. Stated alternatively, the fact that the LIDAC is linearized means it effectively has no differential non-linearity (DNL) nor integrated non-linearity (INL). In one embodiment, DEM is used by the LIDAC to linearize the LIDAC and to remove the offset error. Furthermore, offset error and gain error may be removed through calibration (e.g., during post-silicon device-specific product test). In an alternate embodiment, the L1DAC is linearized by using data-weighted averaging.

[0021] In the embodiment of Figure 2, segment SEG1 includes an 18-bit barrel shifter BS 1 and 18 current mirrors. Each current mirror is designed to mirror reference current IRE( by a factor of 1/W, where W is a ratio of reference current IRE( and unit current ILsB. In one embodiment, W is 32, 'REF is 40 microamps, and ILsB is 1.25 microamps. Each of the 18 current mirrors receives a corresponding control bit from barrel shifter BS 1 and generates a current with a value of unit current ILSB if the control bit is one and a value of zero if the control bit is zero. Segment SEG18 includes a second 18-bit barrel shifter BS18 and 18 current mirrors. Each current mirror in SEG18 is designed to mirror reference current lith( by a factor of 18/W and generates a current with a value of 18 times unit current 11,s,B if the control bit is one and a value of zero if the control bit is zero. The currents from the current mirrors of both segments SEG' and SEGI8 are summed together to generate VRS current ILIDAC. In the embodiment of Figure 2, the structure of the LIDAC enables it to generate values of VRS current ILIDAC from 11,sn to 17 x 19 = 323 ILsB, e.g., approximately 1.25 microamps to 403.75 microamps. The binary value loaded into each of the barrel shifters must include at least one bit that is not zero and at least one bit that is not one in order to accomplish the effect of canceling out process variation among the current mirrors of the segment.

[0022] Operation of the LIDAC is as follows. When the digital processor DP loads a new value of digital current value DLIDAC into barrel shifters BSI and BS18 (more specifically, 18-bit Dmakc_lx into BSI and 18-bit DuuAc_18x into BS18), the current mirrors responsively generate a value of VRS current ILTDAC. Then the value of each of the barrel shifters BS1 and BS18 is rotated by one bit and the current mirrors responsively generate a second value of VRS current ILIDAC. Then the value of each of the barrel shifters BS 1 and BS 18 is rotated by one bit and the current mirrors responsively generate a third value of VRS current Iimiac. This operation continues at a high frequency until all 18 bits have been rotated through the barrel shifters BSI and B SI8. In this manner, process variations in the current mirrors (e.g., size differences) are mitigated in order to minimize offset error and to provide a highly-linearized DAC with negligible quantization error. Employment of the barrel shifters BSI and B S18 may have the advantage of reducing the size and power consumption of the LIDAC relative to a current DAC that uses hardware to randomize the inputs to the current mirrors The A AF operates to remove any aliasing in sensed voltage VSNS that might be caused by the high-frequency switching operation of the LIDAC.

100231 In the embodiment of Figure 2, the number of DEM elements is chosen to support a resistance of the VSR in a range of about 1 kilo-Ohm to 100 kilo-Ohm. However, different numbers of DEM elements may be employed to support different ranges of resistance of the VSR. In one embodiment, the clock frequency at which the barrel shifters rotate is 12 MHz, which tends to generate tones at about 700 kHz given the number of DEM elements. The tones are filtered by the AAF (e.g., approximately 26 dB attenuation), and the averaging performed by operation of the barrel shifting may provide another approximately 12.5 dB (e.g., 10*logio(18)) of rejection.

100241 Figure 3 is a circuit diagram illustrating a dual-input programmable gain amplifier PGA according to embodiments of the present disclosure. The circuit of Figure 3 may perform the function of the multiplexing circuitry MUX and PGA of Figure 1, for example. The PGA includes an operational transconductance amplifier OTA2, a sampling capacitor Cs, a feedback capacitor Cf, and five switches that operate with sampling capacitor Cs and feedback capacitor Cr as a switched capacitor network that automatically cancels any offset of the PGA. Each of the five switches is labelled with a "1" or a "2" to indicate whether it is closed by a respective first or second phase of a clock signal, and the switches are referred to as a switch I or a switch 2. The non-inverting input of OTA2 receives scaled voltage reference VREFSC. OTA2 uses negative feedback to generate output voltage VOLcc of the PGA. A first switch 1 is connected across the output of the PGA and the inverting input of the PGA in parallel with feedback capacitor Cf, although a first switch 2 is connected between feedback capacitor Cr and the output side of the first switch 1. Scaled voltage reference VREFsc is connected to the output side of feedback capacitor CC by a second switch 1. The sampling capacitor Cs is connected to the inverting input of OTA2. The other side of sampling capacitor Cs is connected to a second switch 2 that selectively connects the sampling capacitor Cs to scaled voltage reference VREFSC. The other side of sampling capacitor C, is also connected to a third switch I that selectively connects the sampling capacitor C, to anti-alias-filtered voltage VAAF. Thus, the second switch 2 and third switch 1 operate to provide a multiplexing capability to select either anti-alias-filtered voltage VAAF or scaled voltage reference VREFsc as an input. The gain Ni of the PGA is the ratio of the capacitances of sampling capacitor C, and feedback capacitor Cf. The PGA is highly resistant to error caused by gain variation because its gain M is defined by a ratio of scaled components, e.g., sampling capacitor C, and feedback capacitor Cf, which makes it highly insensitive to temperature, voltage and process variation. In an alternate embodiment, the gain Ni is defined by scaled resistors. The PGA scales up the anti-alias-filtered sensed voltage VSNE to maximize the dynamic range of the ADC. As described above, the PGA may have minimal offset due to operation of the offset cancelled switched capacitor network.

[0025] Figure 4 is a flowchart illustrating a method for removing error in a digital output generated by an ADC system (e.g., detector 14 of Figure 1) according to embodiments of the present disclosure. Operation begins at block 402.

100261 At block 402, first and second voltage references are generated, e.g., voltage reference VREF and ADC voltage reference VREFADE. The first and second voltage references include variation with respect to their respective operating conditions, e.g., mechanical stress, process, voltage and/or temperature variation. Consequently, error may be introduced into signals that involve the first and second reference voltages. In one embodiment, the second voltage reference is a scaled version of the first voltage reference, e.g., ADC voltage reference VREFADC is a scalar multiple of voltage reference VREF in which the scalar is the gain L of amplifier AMP of Figure 1. In another embodiment, the second voltage reference is the first voltage reference. Operation proceeds to block 404.

[0027] At block 404, a first sensed voltage is generated that is a product of the first voltage reference and an unknown scalar, e.g., sensed voltage VSNE, or anti-alias-filtered voltage VAAF, or the output voltage VOUT that is the gained-up version of anti-alias-filtered voltage VAAF. The sensed voltage VsNs may be understood as the product of voltage reference WEI, and an unknown scalar. The unknown scalar may be the product resistance Ihms of the VRS, which is unknown, and the transconductance of detector 14. Operation proceeds to block 406.

[0028] At block 406, a second sensed voltage is generated that is a product of the first voltage reference and a known scalar, e.g., scaled voltage reference Vithrsc, or the output voltage VEKIT that is the gained-up version of scaled voltage reference VREESC. The scaled voltage reference VEEESE may be understood as the product of voltage reference WEE and a known scalar. The known scalar may be, in the embodiment of Figure 2, the voltage divider ratio accomplished by the two RTAN resistors (e.g., one-half). Operation proceeds to block 408.

[0029] At block 408, the ADC uses the second voltage reference (e.g., scaled voltage reference VREFSE) to generate a first digital value that represent the first sensed voltage and to generate a second digital value that represent the second sensed voltage. The first and second digital values may contain error as a result of the gain error of the second voltage reference. The first and second digital values may also contain error as a result of the variation of the first and second voltage references. Operation proceeds to block 412.

[0030] At block 412, a ratio based on the first and second digital values is used (e.g., by the digital processor DP) to remove the error from the first digital value. Various ratios based on the first and second digital values and their use are described in more detail 20 below. Operation proceeds to block 414.

[0031] At block 414, the ratio computed at block 412 is used to compute the resistance of the VRS.

[0032] The operation described in Figure 4 may be further described according to the following equations. In equation (1) below, VSENSEI is the first sensed voltage of block 404, Vithii is the first voltage reference of block 402, and U is the unknown scalar of block 404. In equation (2) below, VSENSE) is the second sensed voltage of block 406, and K is the known scalar of block 406.

VSENSE1 = U * VREF1 (1) VSENSE2 = K * VREF1 (2) [0033] Assume VREFI has variation with respect to its operating conditions. In that case, error may be introduced into the two sensed voltages such that equations (1) and (2) may be expressed as equations (3) and (4) VSENSE1 = U * VREF1 * (1+ Aerr1) (3) VSENSE2 = K * VREF1 * (1+ Aerr1) (4) where Aerr1 is the error introduced by the variation in VREFI with respect to its operating conditions.

[0034] An ADC system, such as included in detector 14, uses the second voltage reference VIth.F2 that is gained up. The second voltage reference VREF2is assumed to have variation with respect to its operating conditions and the second voltage reference VREF7 is assumed to have gain error, e.g., amplifier AMP of Figure 1 has gain error and offset error induced by temperature variation (or other operating conditions) that introduce error into ADC voltage reference VREFAuc. In that case, when the ADC converts the two sensed voltages to respective digital values, error may be introduced into the two digital values as expressed essentially in equations (5) and (6) Di = U * V REF1 * (1 ± Aerr1) * (1 + Aerr2) * (1 + Aerr3) (5) D2 = K * VREFi * (1+ Aerrl) * (1 + Aerr2) * (1 + Aerr3) (6) where aerr2 is the error introduced by the variation in VREF2 with respect to its operating conditions, and Aerr3 is the gain error.

[0035] As may be observed, taking the ratio of the two digital values Di and D2 given by equations (5) and (6) cancels the error factors to yield a ratio of the unknown scalar U and the known scalar K, per equation (7). Di U D2 K Because the error is essentially canceled, the ratio of the two digital values may be expressed by equation (8) Di VSENSE1JDEAL (8) D2 V SENSE2JDEAL where V SENSE1 IDEAL and VSENSE2 IDEAL are the respective values of first and second sensed voltages without error caused by variation in VREF1 or VREF2 or gain error caused by a circuit element that added gain to generate VREF2. Furthermore, the unknown scalar U may be solved per equation (9). (7) (9)

[0036] Taking the embodiment of Figure 2, the relationship between voltage reference VREF and scaled voltage reference VREFSC may be expressed per equation (10).

RTAN 1 u VREFSC DTAN+ RTAN * "REF = -2 v REF (10) [0037] Taking scaled voltage reference VREEsc as VsENsE2 and voltage reference VREF as VREFI of equation (2), yields the known scalar K per equation (11) K = RTAN _1 (11) RTAN+ STAN 2 100381 Take VSENSE1 of equation (1) as a sensed voltage across a variable-resistance sensor whose resistance varies with respect to a time-varying stimulus, such as VSNS of detector 14, and take VREN of equation (1) as VREF of detector 14 such that VsNs is a product of VREF and an unknown scalar U per equation (12).

VSNS = U *VREE (12) [0039] Sensed voltage VSNS is given by equation (13).

VSNS = RVRS * ILIDAC (13) VRS current ILIDAC is given by equation (14).

ILIDAC = DLIDAC * 'LSE (14) Reference current 'REF is given by equation (15).

VREF REF =

2tnTAN Unit current ILss is given by equation (16). (15)

(16) current LSE = 'REF where W is the known ratio of IRE,F and the 1LsB according to the sizing of the mirrors of the LIDAC, which is known (e.g., which is 32 in the embodiment of Figure 2). [0040] Combining equations (12) through (16) yields an expression for U in equation 20 (17)

DLIDAC

U = RVRS * p " *-TAN 100411 By combining equations (9), (11) and (17), the unknown resistance RvNs of the VRS may be solved using the ratio of the two digital values Di and D2 by equation (18).

111.RTAN

RVRS

D2 DLIDAC [0042] In the above analysis, it was assumed that the gain M of the PGA is one and the common mode voltage of the PGA is zero. Now take the embodiment of Figure 3 in which the common mode voltage of the PGA is scaled voltage reference VREFSC and the gain of the PGA is M (e.g., 2 in one embodiment). The two digital values Di and D2 may then be expressed by equations (19) and (20).

-[VREFsc * (1 + Aerrl) + M(VsNs * (1 + Aerr1) -V REFSC* (1+ aerr1))] * (1 + Aerr2) * (1 + aerr3) (19) (17) (18) D2 = [VREFSC (1 ± Aerrl) MWREFSC (1+ Aerrl) VREFSC* (1 + Aerrl))] * (1 + Aerr2) * (1 + Aerr3) (20) [0043] Taking the ratio of Di and D2 given by equations (19) and (20) and solving for sensed voltage VsNs yields equation (21) in which the error terms are effectively 5 eliminated VSNS = VREFSC * Al*D2 [0044] Combining equation (21) with equation (14) and solving for resistance RvRs of the VRS yields equation (22). = * *

1 VREFSC 01+ 02(M-1) (22) RVRS DLIDAC 'LSE M.02 [0045] Let the second term of equation (22) be designated as the unit resistance R[1] of the LIDAC per equation (23), e g, where the value of digital current value DL1DAc is one.

R [1] = VREFSC LSE (23) [0046] Further, let the product of the first and second terms of equation (22) be designated as a non-unit resistance R[D] of the LIDAC per equation (24), where R[D] is the resistance for a given value D of digital current value Du-DAC.

R[D] - * VREFSC (24) DLIDAC 'LSE' [0047] Thus, if the resistance R[D] for a given VRS current ILIDAc stimulated by a digital current value DLIDAC is known, then the resistance RvRs of the VRS may be determined according to equation (22), e g, by digital processor DP. In one embodiment, the unit resistance R[1] and non-unit resistance R[D] may be computed using equations (25) and (26), which are derived from equations (23), (24), (10), (15) and (16).

R[1] -RTAiv * W (25) R[D] = * R[1] (26)

DLIDAC

100481 However, in an alternate embodiment, the unit resistance R[1] may be determined at calibration time (e.g., during post-silicon device-specific product test) by inputting a unit digital current value DLIDAC, measuring the VRS current 'LIDAC while simultaneously measuring the scaled voltage reference VREFSC (e.g., at pins P+ and P-), and substituting the measured values into equation (23). Similarly, the non-unit resistance R[D] may be determined at a calibration time by inputting different non-unit D digital current values DLIDAC, measuring the VRS current luokc while simultaneously measuring the scaled voltage reference VREFSC, and substituting the measured values into equation (24). In one D1+ D2(M-1) (21) embodiment, such a procedure may be performed for each segment of the LIDAC. In one embodiment, measurements may be taken at minimum and maximum values of digital current value DLIDAC and intermediate values of R[D] may be linearly interpolated from the minimum and maximum values. In one embodiment, a crossbar switch may precede OTA1 of Figure 2 to enable its inputs to be toggled, and during calibration time scaled voltage reference VREFSC is measured twice -once at each configuration of the crossbar switch -and the two values are averaged to minimize effects of OTA1 offset error. Such an embodiment may be susceptible to mismatch in the RTAN resistors, which susceptibility may be minimized by careful sizing and calibration of the RTAN resistors.

Such an embodiment may also be susceptible to variation in the RTAN resistors due to operating conditions. In one embodiment, an internal temperature sensor may be included in the detector 14 to compensate for variation in the temperature coefficient of resistance (TCR) of the RTAN resistors. In yet another embodiment, the RTAN resistors may be replaced by an external precision resistor, 100491 Various advantages may be obtained by using the ratio based on the first and second digital values Di and D2. First, the determination of resistance Rws of the VRS is independent of variation of scaled voltage reference VREFSC. The independence may be observed from the second term of equation (22) because it involves a ratio of scaled voltage reference VREFSC and unit current UR. Unit current ITsa is generated from reference current 'REF (by the linearized DAC) which is generated from scaled voltage reference VREFSC. Thus, by knowing the unit resistance R[1], variation in scaled voltage reference VREFSC is eliminated in the determination of resistance Rws of the VRS by using the ratio based on the first and second digital values DI and D2, e.g., the third term of equation (22), as well as equation (18). Second, the determination of resistance RN/Rs of the VRS is independent of variation of ADC voltage reference VREFADC because gain error and offset error of amplifier AMP and error introduced to amplifier AMP by variation in voltage reference VREF, are eliminated by using the ratio based on the first and second digital values Di and D2, e.g., the third term of equation (22), as described above with respect to equations (19) through (21), as well as equation (18). Third, the determination of resistance KVRS of the VRS is independent of variation of offset error in the LIDAC which is removed by the DEM. As may be observed from equation (22), variation in the gain NI of the PGA may affect accuracy of the determination of resistance RvRS of the VRS. Preferably, the PGA is calibrated to minimize any gain error it may have. Furthermore, as described above, the embodiment of the PGA of Figure 3 is highly resistant to error caused by gain variation because its gain M is defined by a ratio of scaled components, e.g., sampling capacitor Cs and feedback capacitor Cf. . [0050] Viewing the LIDAC effectively as a transconductor that receives voltage 5 reference VREF as an input and generates VRS current ILTDAC as an output, the non-unit transconductance G[D] of the LIDAC may be expressed by equation (27), and the unit transconductance G[]] of the LIDAC may be expressed by equation (28).

-G [D]

LIDAC _ DLIDAC*1LSB 1 L' (27) 2.V REPE 2sR[D] G [1] = 2.R[1] 100511 In an embodiment in which the common mode voltage Vcm of the PGA is a different value than the scaled voltage reference VREFsc, a third digital value D3 may be measured while the input to the PGA is the common mode voltage Vcrvi (e.g., the differential input to OTA2 is zero). The three digital values Di and D7 may then be expressed by equations (29), (30) and (31).

Di = [Vcm * (1 + Aerr1) + M (Vg ivs * (1 + Aerr 1) -/ cm * (1 + Aerr1))] (1 + Aerr2) * (1 + Aerr3) (29) D2 = [Vcm * (1 + Aerr1) + M(V -REFSC * (1 + Aerr1) -Vcm * (1 + Aerr1))] * (1 + Aerr2) * (1 + Aerr3) (30) D3 = [Vcm * (1 + Aerr1) + M (Vcm * (1 + Aerr1) -Vcm * (1 + Aerr1))] * (1 + Aerr2) * (1 + Aerr3) (31) [0052] Equations (29) through (31) may be simplified as equations (32) through (34). = [Vcm * (1 + Aerr1) * (1 -M) Aerr2) * (1 + Aerr3) (32) D2 = [licm * (1 + Aerr1) * (1 -M) + M * VREFSC * (1 ± Aerr1)] * (1 + Aerr2) * (1 + Aerr3) (33) D3 = Vcm * (1 ± Aerrl) * (1 + Aerr2) * (1 + Aerr3) (34) [0053] Equations (35) and (36) may be derived from equations (33) and (34).

-(1 -M) * D3 = M * VSNS * (1 + Aerr1) * (1 + Aerr2) * (1 + Aerr3) (35) D2 -(1 -M) * D3 --M * V REFSC * (1 + Aerr1) * (1 + Aerr2) * (1 + Aerr3) (36) (28) ± Al * VSN5 * (1 ± Aerr1)] * (1 ± [0054] Dividing equations (35) and (36) and solving for Vs1,Es yields equation (37), which is analogous to equation (21) above Substituting with equations (13) and (14) yields the resistance Rvns of the VRS, which may be determined per equation (38).

VSNS = VREFSC 02+ 03(M-1) 1 V REFSC Dr+ D3(M-1) RV RS = DLIDAR 1E5B 132+ D3(M-1) 100551 Again, error introduced by variation in scaled voltage reference VREFSC is advantageously eliminated by using the ratio based on the first, second and third digital values DI, D2, and D3, i.e., the third term of equation (38).

[0056] It should be understood -especially by those having ordinary skill in the art with the benefit of this disclosure -that the various operations described herein, particularly in connection with the figures, may be implemented by other circuitry or other hardware components. The order in which each operation of a given method is performed may be changed, unless otherwise indicated, and various elements of the systems illustrated herein may be added, reordered, combined, omitted, modified, etc. It is intended that this disclosure embrace all such modifications and changes and, accordingly, the above description should be regarded in an illustrative rather than a restrictive sense.

[0057] Similarly, although this disclosure refers to specific embodiments, certain modifications and changes can be made to those embodiments without departing from the scope and coverage of this disclosure. Moreover, any benefits, advantages, or solutions to problems that are described herein with regard to specific embodiments are not intended to be construed as a critical, required, or essential feature or element.

100581 Further embodiments likewise, with the benefit of this disclosure, will be apparent to those having ordinary skill in the art, and such embodiments should be deemed as being encompassed herein. All examples and conditional language recited herein are intended for pedagogical objects to aid the reader in understanding the disclosure and the concepts contributed by the inventor to furthering the art and are construed as being without limitation to such specifically recited examples and conditions.

[0059] This disclosure encompasses all changes, substitutions, variations, alterations, and modifications to the example embodiments herein that a person having ordinary skill in the art would comprehend. Similarly, where appropriate, the appended claims encompass all changes, substitutions, variations, alterations, and modifications to the example Di+ 03(M-1) (37) (38) embodiments herein that a person having ordinary skill in the art would comprehend. Moreover, reference in the appended claims to an apparatus or system or a component of an apparatus or system being adapted to, arranged to, capable of configured to, enabled to, operable to, or operative to perform a particular function encompasses that apparatus, system, or component, whether or not it or that particular function is activated, turned on, or unlocked, as long as that apparatus, system, or component is so adapted, arranged, capable, configured, enabled, operable, or operative.

For the avoidance of doubt, the present invention includes the subject matter as defined in the following numbered paragraphs (abbreviated "para ") Para 1. A detector for measuring a resistance of a variable resistance sensor (VRS), wherein the resistance of the VRS varies with respect to a time-varying stimulus, comprising: a voltage reference having variation with respect to operating conditions; a linearized digital-to-analog converter (LIDAC) having a known transconductance that uses the voltage reference to generate a current for pumping into the VRS to cause the VRS to generate a voltage sensed by the detector, wherein the sensed voltage includes error due to the variation of the voltage reference; a programmable gain amplifier (PGA) that gains up the sensed voltage to generate an output signal, an analog-to-digital converter (ADC) that converts the output signal to a digital value, and a digital processor that computes the resistance of the VRS using the digital value and the known transconductance.

Para 2 The detector of Para. 1, wherein the PGA is non-varying with respect to the time-varying stimulus.

Para 3. The detector of Para. 1 wherein the ADC uses a scaled version of the voltage reference used by the LIDAC to convert the output signal to the digital value.

Para. 4. The detector of Para. 1, wherein the time-varying stimulus is a temperature of the VRS.

Para. 5 The detector of Para. 1, wherein the VRS is from the list: a photoresistor whose resistance varies with light intensity; a touchscreen whose resistance varies with a touched coordinate location; a pressure sensor whose resistance varies with pressure; and a sensor whose resistance varies with voltage.

Para 6. The detector of Para. I, wherein the LIDAC: (1) is linearized by using dynamic element matching (DEM) or data-weighted averaging; (2) is calibrated to generate a value of the current to cause the VRS to initially generate a value of the sensed voltage that is close to a target voltage that is a common mode voltage of the PGA; or (3) comprises a non-variable resistance element (NVRE) used to generate the current using the voltage reference, and the NVRE is non-varying with respect to the time-varying stimulus that causes the resistance of the VRS to vary.

Para. 7 The detector of Para. I, wherein the LIDAC comprises: a first segment of N equally-weighted binary-controlled current mirrors; a first barrel shifter that receives a first N-bit input value and provides the first N-bit input value in a rotated fashion over a period to respective ones of the first segment of N equally-weighted binary-controlled current mirrors; wherein the N bits of the first input value include at least one zero-valued bit and at least one one-valued bit; a second segment of N equally-weighted binary-controlled current mirrors; a second barrel shifter that receives a second N-bit input value and provides the second N-bit input value in a rotated fashion over the period to respective ones of the second segment of N equally-weighted binary-controlled current min-ors wherein the current mirrors of the first and second segments are differently weighted; wherein the N bits of the second input value include at least one zero-valued bit and at least one one-valued bit; and wherein outputs of all of the current mirrors of the first and second segments are summed together to generate the current for pumping into the VRS Para. 8. The detector of Para. 1 further comprising: an anti-aliasing filter that reduces noise in the sensed voltage for provision to the PGA.

Para. 9 The detector of Para.

wherein the PGA uses a scaled version of the voltage reference to gain up the sensed voltage to generate the output signal.

Para 10. The detector of Para. 1, wherein the PGA selectively receives the sensed voltage and a scaled version of the voltage reference, wherein the ADC also converts the scaled version of the voltage reference to a second digital value, and wherein the digital processor computes the resistance of the VRS using one of a ratio that includes the first digital value and the second digital value; a known gain of the PGA; or a known digital input value to the LIDAC that controls the current generated by the L1DAC.

Para 11. The detector of Para. 10, wherein the digital processor computes the resistance of the VRS as a product of: the ratio that includes the first and second digital values, a reciprocal of the digital input value to the LIDAC, and a ratio of a one-time measurement of the voltage reference; and a one-time measurement of a unit current of the L1DAC, or: wherein the PGA further generates a zero-input signal output voltage, and wherein the ratio further includes a third digital value that is the zero-input signal output voltage converted by the ADC.

Para 12. A method for measuring a resistance of a variable resistance sensor (VRS), wherein the resistance of the VRS varies with respect to a time-varying stimulus, comprising: generating a voltage reference having variation with respect to operating conditions, using, by a linearized digital-to-analog converter (LIDAC) having a known transconductance, the voltage reference to generate a current; pumping the current into the VRS to cause the VRS to generate a sensed voltage; wherein the sensed voltage includes error due to the variation of the voltage reference; gaining up, by a programmable gain amplifier (PGA), the sensed voltage to generate an output signal; converting, by an analog-to-digital converter (ADC), the output signal to a digital value, and computing the resistance of the VRS using the digital value and the known transconductance.

Para 13. The method of Para. 12, wherein the PGA is non-varying with respect to the time-varying stimulus. Para 14. The method of Para. 12, further comprising: wherein the ADC uses a scaled version of the voltage reference used by the LIDAC to convert the output signal to the digital value.

Para. 15. The method of Para. 12, wherein the time-varying stimulus is a temperature of the VRS. Para. 16. The method of Para. 12, wherein the VRS is from the list: a photoresistor whose resistance varies with light intensity; a touchscreen whose resistance varies with a touched coordinate location; a pressure sensor whose resistance varies with pressure; and a sensor whose resistance varies with voltage. Para 17. The method of Para. 12, (1) wherein the LIDAC is linearized by using dynamic element matching (DEM) or data-weighted averaging; (2) the method further comprises calibrating the LIDAC to generate a value of the current to cause the VRS to initially generate a value of the sensed voltage that is close to a target voltage that is a common mode voltage of the PGA; or (3) wherein the LIDAC comprises a non-variable resistance element (NVRE) used to generate the current using the voltage reference, and the NVRE is non-varying with respect to the time-varying stimulus that causes the resistance of the VRS to vary.

Para 18. The method of Para. 12, wherein said using, by the LIDAC, the voltage reference to generate the current comprises: receiving, by a first barrel shifter, a first N-bit input value; providing, by the first barrel shifter, the first N-bit input value in a rotated fashion over a period to respective ones of a first segment of N equally-weighted binary-controlled current mirrors; and wherein the N bits of the first input value include at least one zero-valued bit and at least one one-valued bit; and wherein said using, by the L1DAC, the voltage reference to generate the current further comprises: receiving, by a second barrel shifter, a second N-bit input value; providing, by the second barrel shifter, the second N-bit input value in a rotated fashion over the period to respective ones of a second segment of N equally-weighted binary-controlled current mirrors; wherein the current mirrors of the first and second segments are differently weighted; wherein the N bits of the second input value include at least one zero-valued bit and at least one one-valued bit, and summing together outputs of all of the current mirrors of the first and second segments to generate the current for pumping into the VRS.

Para. 19. The method of Para. 12, further comprising: reducing, by an anti-aliasing filter, noise in the sensed voltage for provision to the PGA.

Para 20. The method of Para. 12, further comprising: using, by the PGA, a scaled version of the voltage reference to gain up the sensed voltage to generate the output signal.

Para 21. The method of Para. 12, further comprising: selectively receiving, by the PGA, the sensed voltage and a scaled version of the voltage reference; converting, by the ADC, the scaled version of the voltage reference to a second digital value; and computing the resistance of the VRS using one of: a ratio that includes the first digital value and the second digital value; a known gain of the PGA; or a known digital input value to the LIDAC that controls the current generated by the LIDAC.

Para 22. The method of Para. 21, further comprising: computing the resistance of the VRS as a product of: the ratio that includes the first and second digital values; a reciprocal of the digital input value to the LIDAC; and a ratio of: a one-time measurement of the voltage reference; and a one-time measurement of a unit current of the LIDAC; or: generating, by the PGA, a zero-input signal output voltage, and wherein the ratio further includes a third digital value that is the zero-input signal output voltage converted by the ADC.

Para 23. A system, comprising: a first sensed voltage generated as a product of a first voltage reference and an unknown scalar; a second sensed voltage generated as a product of the first voltage reference and a known scalar; an amplifier that generates a second voltage reference, wherein the amplifier has a gain error; an analog-to-digital converter (ADC) that uses the second voltage reference to generate first and second digital values representing the first and second sensed voltages, respectively; wherein the first and second digital values contain error caused by the gain error of the second voltage reference; and a digital processor that uses a ratio based on the first and second digital values to remove the error from the first digital value.

Para 24 The system of Para 23, wherein the first voltage reference has variation with respect to operating conditions; wherein the first and second digital values also contain error caused by the first voltage reference variation; and wherein the digital processor also uses the ratio to remove the error caused by the first voltage reference variation from the first digital value.

Para 25. The system of Para. 23, wherein the second voltage reference is a scaled version of the first voltage reference.

Para 26. The system of Para. 23, wherein the second voltage reference is the first voltage reference. Para 27. The system of Para. 23, wherein the first sensed voltage is generated by pumping a current into a variable resistance sensor (VRS), wherein the resistance of the VRS varies with respect to a time-varying stimulus; wherein the resistance of the VRS is proportional to the unknown scalar; and wherein the digital processor computes the resistance of the VAS using the ratio and the known scalar.

Para 28. The system of Para. 27, further comprising: a linearized digital-to-analog converter (LIDAC) having a known transconductance that generates the current from the first voltage reference; and wherein the digital processor computes the resistance of the VRS using the ratio and the known scalar and the known transconductance Para 29. The system of Para. 27, further comprising: a digital-to-analog converter (DAC) that receives a digital input value and generates the current from the first voltage reference; and wherein the digital processor computes the resistance of the VRS as a product of: the ratio based on the first and second digital values; a reciprocal of the digital input value of the DAC; and a ratio of a measurement of the first voltage reference; and a measurement of a unit current of the LIDAC. Para. 30. The system of Para. 27, further comprising: wherein a numerator of the ratio based on the first and second digital values is a sum of the first digital value; and a product of a difference of one minus a calibrated gain; and a third digital value received from the ADC; wherein a denominator of the ratio based on the first and second digital values is a sum of the second digital value; and a product of: a difference of one minus the calibrated gain and a third digital value received from the ADC; wherein the calibrated gain is of a programmable gain amplifier (PGA) that scaled up the sensed voltage to maximize a signal dynamic range of the ADC; and wherein the third digital value is a measurement of an output voltage of the PGA when a zero input signal is applied to an input of the PGA; or: wherein a numerator of the ratio based on the first and second digital values is a sum of the first digital value and a product of a difference of one minus a calibrated gain and a second digital value; wherein a denominator of the ratio based on the first and second digital values is a product of: the second digital value; and the calibrated gain; wherein the calibrated gain is of a programmable gain amplifier (PGA) that scaled up the sensed voltage to maximize a signal dynamic range of the ADC; and wherein the second sensed voltage is a reference voltage of the PGA. Para 31. The system of Para. 27, further comprising: wherein the time-varying stimulus is a temperature of the VRS.

Para 32. The system of Para. 27, further comprising: wherein the VRS is from thelist: a photoresistor whose resistance varies with light intensity; a touchscreen whose resistance varies with a touched coordinate location; a pressure sensor whose resistance varies with pressure; and a sensor whose resistance varies with voltage. Para. 33. The system of Para. 27, further comprising: alinearized digital-to-analog converter (LIDAC) that generates the current from the first voltage reference; and wherein the LIDAC is linearized by using dynamic element matching (DEM) or data-weighted averaging Para 34. A method for removing error in a system having an analog-to-digital converter (ADC), comprising: generating a first sensed voltage that is a product of a first voltage reference and an unknown scalar; generating a second sensed voltage that is a product of the first voltage reference and a known scalar; using, by the ADC, a second voltage reference to generate first and second digital values representing the first and second sensed voltages, respectively; wherein the second voltage reference has gain error and the first and second digital values contain error caused by the gain error of the second voltage reference; and using a ratio based on the first and second digital values to remove the error from the first digital value.

Para 35. The method of Para. 34, wherein the first voltage reference has variation with respect to operating conditions; wherein the first and second digital values also contain error caused by the first voltage reference variation, and wherein said using the ratio also removes the error caused by the first voltage reference variation from the first digital value Para. 36. The method of Para. 34, wherein the second voltage reference is a scaled version of the first voltage reference Para 37. The method of Para. 34, wherein the second voltage reference is the first voltage reference.

Para 38. The method of Para. 34, further comprising: wherein said generating the first sensed voltage comprises pumping a current into a variable resistance sensor (VRS), wherein the resistance of the VRS varies with respect to a time-varying stimulus; wherein the resistance of the VRS is proportional to the unknown scalar; and detecting the resistance of the VRS using the ratio and the known scalar.

Para 39. The method of Para. 38, further comprising: generating the current from the first voltage reference using a linearized digitalto-analog converter (LIDAC) having a known transconductance; and detecting the resistance of the VRS using the ratio and the known scalar and the known transconductance.

Para 40. The method of Para. 38, further comprising: generating, by a digital-to-analog converter (DAC) that receives a digital input value, the current from the first voltage reference; and calculating the resistance of the VRS as a product of: the ratio based on the first and second digital values; a reciprocal of the digital input value of the DAC; and a ratio of a measurement of the first voltage reference; and a measurement of a unit current of the L1DAC.

Para. 41. The method of Para. 38, further comprising: wherein a numerator of the ratio based on the first and second digital values is a sum of the first digital value; and a product of: a difference of one minus a calibrated gain; and a third digital value received from the ADC; wherein a denominator of the ratio based on the first and second digital values is a sum of: the second digital value; and a product of a difference of one minus the calibrated gain; and a third digital value received from the ADC; wherein the calibrated gain is of a programmable gain amplifier (PGA) that scaled up the sensed voltage to maximize a signal dynamic range of the ADC; and wherein the third digital value is a measurement of an output voltage of the PGA when a zero input signal is applied to an input of the PGA; or: wherein a numerator of the ratio based on the first and second digital values is a sum of the first digital value and a product of a difference of one minus a calibrated gain and a second digital value; wherein a denominator of the ratio based on the first and second digital values is a product of: the second digital value; and the calibrated gain, wherein the calibrated gain is of a programmable gain amplifier (PGA) that scaled up the sensed voltage to maximize a signal dynamic range of the ADC; and wherein the second sensed voltage is a reference voltage of the PGA.

Para 42. The method of Para. 38, wherein the time-varying stimulus is a temperature of the VRS.

Para 43. The method of Para. 38, wherein the VRS is from the list: a photoresistor whose resistance varies with light intensity; a touchscreen whose resistance varies with a touched coordinate location; a pressure sensor whose resistance varies with pressure; and a sensor whose resistance varies with voltage. Para 44. The method of Para. 38, further comprising: generating, by a linearized digital-to-analog converter (L1DAC), the current from the first voltage reference; and wherein the LIDAC is linearized by using dynamic element matching (DENI) or data-weighted averaging.

Claims

CLAIMSA system, comprising: a first sensed voltage generated as a product of a first voltage reference and an unknown scalar, a second sensed voltage generated as a product of the first voltage reference and a known scalar, an amplifier that generates a second voltage reference, wherein the amplifier has a gain error; an analog-to-digital converter (ADC) that uses the second voltage reference to generate first and second digital values representing the first and second sensed voltages, respectively; wherein the first and second digital values contain error caused by the gain error of the second voltage reference; and a digital processor that uses a ratio based on the first and second digital values to remove the error from the first digital value.
The system of claim 1, wherein the first voltage reference has variation with respect to operating conditions; wherein the first and second digital values also contain error caused by the first voltage reference variation, and wherein the digital processor also uses the ratio to remove the error caused by the first voltage reference variation from the first digital value.
3. The system of claim I, wherein the second voltage reference is a scaled version of the first voltage reference.
The system of claim 1, wherein the second voltage reference is the first voltage reference.
5. The system of claim 1, wherein the first sensed voltage is generated by pumping a current into a variable resistance sensor (VRS), wherein the resistance of the VRS varies with respect to a time-varying stimulus; wherein the resistance of the VRS is proportional to the unknown scalar; and wherein the digital processor computes the resistance of the VRS using the ratio and the known scalar.The system of claim 5, further comprising: a linearized digital-to-analog converter (L1DAC) having a known transconductance that generates the current from the first voltage reference, and wherein the digital processor computes the resistance of the VRS using the ratio and the known scalar and the known transconductance.The system of claim 5, further comprising: a digital-to-analog converter (DAC) that receives a digital input value and generates the current from the first voltage reference; and wherein the digital processor computes the resistance of the VRS as a product of: the ratio based on the first and second digital values; a reciprocal of the digital input value of the DAC; and a ratio of a measurement of the first voltage reference; and a measurement of a unit current of the LIDAC. The system of claim 5, further comprising: wherein a numerator of the ratio based on the first and second digital values is a sum of the first digital value and a product of a difference of one minus a calibrated gain; and a third digital value received from the ADC, wherein a denominator of the ratio based on the first and second digital values is a sum of the second digital value; and a product of a difference of one minus the calibrated gain and a third digital value received from the ADC; wherein the calibrated gain is of a programmable gain amplifier (PGA) that scaled up the sensed voltage to maximize a signal dynamic range of the ADC; and wherein the third digital value is a measurement of an output voltage of the PGA when a zero input signal is applied to an input of the PGA; or: wherein a numerator of the ratio based on the first and second digital values is a sum of the first digital value; and a product of a difference of one minus a calibrated gain and a second digital value; wherein a denominator of the ratio based on the first and second digital values is a product of: the second digital value; and the calibrated gain; wherein the calibrated gain is of a programmable gain amplifier (PGA) that scaled up the sensed voltage to maximize a signal dynamic range of the ADC; and wherein the second sensed voltage is a reference voltage of the PGA.9. The system of claim 5, further comprising: wherein the time-varying stimulus is a temperature of the YRS.10. The system of claim 5, further comprising: wherein the VRS is from the list: a photoresistor whose resistance varies with light intensity; a touchscreen whose resistance varies with a touched coordinate location; a pressure sensor whose resistance varies with pressure; and a sensor whose resistance varies with voltage.11. The system of claims, further comprising: a linearized digital-to-analog converter (LIDAC) that generates the current from the first voltage reference; and wherein the LIDAC is linearized by using dynamic element matching (DEM) or data-weighted averaging 12. A method for removing error in a system having an analog-to-digital converter (ADC), comprising: generating a first sensed voltage that is a product of a first voltage reference and an unknown scalar, generating a second sensed voltage that is a product of the first voltage reference and a known scalar; using, by the ADC, a second voltage reference to generate first and second digital values representing the first and second sensed voltages, respectively; wherein the second voltage reference has gain error and the first and second digital values contain error caused by the gain error of the second voltage reference; and using a ratio based on the first and second digital values to remove the error from the first digital value.13. The method of claim 12, wherein the first voltage reference has variation with respect to operating conditions; wherein the first and second digital values also contain error caused by the first voltage reference variation, and wherein said using the ratio also removes the error caused by the first voltage reference variation from the first digital value.14. The method of claim 12, wherein the second voltage reference is a scaled version of the first voltage reference.15. The method of claim 12, wherein the second voltage reference is the first voltage reference.16. The method of claim 12, further comprising: wherein said generating the first sensed voltage comprises pumping a current into a variable resistance sensor (VRS), wherein the resistance of the VRS varies with respect to a time-varying stimulus; wherein the resistance of the VRS is proportional to the unknown scalar; and detecting the resistance of the VRS using the ratio and the known scalar.17. The method of claim 16, further comprising: generating the current from the first voltage reference using a linearized digital-to-analog converter (1_1:DAC) having a known transconductance; and detecting the resistance of the VRS using the ratio and the known scalar and the known transconductance.18. The method of claim 16, further comprising: generating, by a digital-to-analog converter (DAC) that receives a digital input value, the current from the first voltage reference; and calculating the resistance of the VRS as a product of: the ratio based on the first and second digital values; a reciprocal of the digital input value of the DAC* and a ratio of: a measurement of the first voltage reference; and a measurement of a unit current of the L1DAC.19. The method of claim 16, further comprising: wherein a numerator of the ratio based on the first and second digital values is a sum of: the first digital value; and a product of a difference of one minus a calibrated gain; and a third digital value received from the ADC; wherein a denominator of the ratio based on the first and second digital values is a sum of: the second digital value; and a product of: a difference of one minus the calibrated gain; and a third digital value received from the ADC; wherein the calibrated gain is of a programmable gain amplifier (PGA) that scaled up the sensed voltage to maximize a signal dynamic range of the ADC; and wherein the third digital value is a measurement of an output voltage of the PGA when a zero input signal is applied to an input of the PGA; or: wherein a numerator of the ratio based on the first and second digital values is a sum of the first digital value; and a product of a difference of one minus a calibrated gain; and a second digital value; wherein a denominator of the ratio based on the first and second digital values is a product of: the second digital value; and the calibrated gain; wherein the calibrated gain is of a programmable gain amplifier (PGA) that scaled up the sensed voltage to maximize a signal dynamic range of the ADC; and wherein the second sensed voltage is a reference voltage of the PGA The method of claim 16, wherein the time-varying stimulus is a temperature of the YRS.21. The method of claim 16, wherein the VRS is from the list: a photoresistor whose resistance varies with light intensity; a touchscreen whose resistance varies with a touched coordinate location; a pressure sensor whose resistance varies with pressure; and a sensor whose resistance varies with voltage.22. The method of claim 16, further comprising: generating, by a linearized digital-to-analog converter (LIDAC), the current from the first voltage reference, and wherein the LIDAC is linearized by using dynamic element matching (DEM) or data-weighted averaging.