GB2590532A - Information processing system, platform, and computer-readable program - Google Patents

Abstract

An information processing system comprises a plurality of platforms connected by an expansion bus, such as a PCI Express bus. Each platform has a processor, memory, storage and a root complex to connect to the bus. To send data a platform writes data into a transmission buffer and transmits a reception request to the target platform. The request causes an interrupt on the target platform. The interrupt service routine releases a semaphore, if the number of released semaphores is less than a threshold. A reception processing thread, which is waiting on the semaphore, acquires the data from the transmission buffer. When the data has been acquired, a reception complete signal is sent to the sending platform. The threshold may be a variable value, which may be dependent on the load on the processor in the target platform or on the time zone.

Description

INFORMATION PROCESSING SYSTEM, PLATFORM, AND COMPU l'ERREADABLE PROGRAM

FIELD

Embodiments described herein relate to an information processing system, a platform, and a computer-readable program.

BACKGROUND

There is known information processing systems including a plurality of processors (platforms) and a relay device including a bus connecting the processors to one another in a communicable manner. In such an information processing system, transmission/reception of data between the processors is typically performed via a buffer for transmission (transmission buffer) of a certain device.

In transmission/reception of data between the processors (platforms) via the transmission buffer described above, a semaphore may be used to implement execution control of a reception processing thread for acquiring the data from the transmission buffer. In this case, for example, at the time of receiving a hardware interrupt representing a reception request from a processor on a side of transmitting the data, a processor on a side of' receiving the data performs only processing of releasing one semaphore to minimize hardware interrupt processing having high priority. The reception processing thread advances acquisition of the data after acquiring the one released semaphore.

However, in a case in which communication between the processors is frequently caused, the number of semaphores to be released becomes extensive in a short time. On the other hand, the reception processing thread to be executed after acquiring one released semaphore typically acquires, as much as possible at once, pieces of data transferred via a relay device.

Thus, in a case in which the number of semaphores to be released is extensive, when executing the same number of reception processing threads as the number of semaphores to be released, the reception processing thread may be repeatedly executed although there is no data that should be acquired. As a result, communication performance may be deteriorated due to waste of resources of the processor.

SUMMARY

An information processing system according to the present disclosure includes a plurality of platforms; and a relay device configured to connect the platforms to one another via an expansion bus in a communicable manner. The plurality of platforms includes a first platform and a second platform. The first platform includes a first bridge driver configured to, in response to a transmission request for data to the second platform, write the data into a transmission buffer of the first platform, and transmit, to the second platform, a reception request for the data. The second platform includes: a semaphore control driver configured to, in response to the reception request transmitted from the first bridge driver, control a semaphore for implementing exclusive control over execution of a reception processing thread for acquiring the data from the transmission buffer of the first platform, the semaphore control driver controlling the semaphore by switching whether to release the semaphore or not in accordance with a comparison result between a threshold and a number of semaphores having been released; and a second bridge driver configured to, when a semaphore having been released is present, acquire the semaphore having been released, acquire the data from the transmission buffer via the expansion bus, and transmit, to the first platform, a reception completion notification for the data.

A platform according to the present disclosure is included in a plurality of platforms connected to one another in a communicable manner via an expansion bus by a relay device, the plurality of platforms including a first platform and a second platform.

The platform as the second platform includes: a semaphore control driver configured to, in response to a reception request for data transmitted from the first platform, control a semaphore for implementing exclusive control over execution of a reception processing thread for acquiring data from a transmission buffer of the first platform, the semaphore control driver controlling the semaphore by switching whether to release the semaphore or not in accordance with a comparison result between a threshold and a number of semaphores having been released_ the first platform being configured to, in response to a transmission request for the data to the second platform, write the data into the transmission buffer and transfer the data to the second platform; and a bridge driver configured to, when a semaphore having been released is present, acquire the semaphore having been released, acquire the data from the transmission buffer. and transmit. to the first platform, a reception completion notification for the data.

A computer-readable program according to the present disclosure includes instructions executed by a computer as a platform included in a plurality of platforms connected to one another in a communicable manner via an expansion bus by a relay device. The plurality of platforms including a first platform and a second platform. The instructions causes the computer as the second platform to: in response to a reception request for data transmitted from the first platform, control a semaphore for implementing exclusive control over execution of a reception processing thread for acquiring data from a transmission buffer of the first platforrn" the control of the semaphore including switching whether to release the semaphore or not in accordance with a comparison result between a threshold and a number of semaphores having been released, the first platform being configured to, in response to a transmission request for the data to the second platform.

2 0 write the data into the transmission buffer and transfer the data to the second platform; and, when a semaphore having been released is present, acquire the semaphore having been released, acquire the data from the transmission buffer, and transmit, to the first platform, a reception completion notification for the data.

BRIEF DESCRIPTION OF THE DRAWINGS

FIG. I is an exemplary and schematic block diagram illustrating the entire configuration of an information processing system according to an embodiment; FIG. 2 is an exemplary and schematic block diagram illustrating hardware configurations of' a platform and a relay device of the information processing system according to the embodiment; FIG. 3 is an exemplary and schematic block diagram illustrating a software configuration of the platform according to the embodiment; FIG. 4 is an exemplary and schematic diagram for explaining communication processing performed by the information processing system according to the embodiment; FIG. 5 is an exemplary and schematic diagram for explaining transmission/reception of data via a buffer for transmission according to the embodiment; FIG. 6 is an exemplary and schematic sequence diagram illustrating a processing procedure performed by the information processing system at the time of transmission/reception of data between platforms according to the embodiment; FIG. 7 is a sequence diagram illustrating a release processing procedure for a semaphore performed by a platform on a receiving side at the time of transmission/reception of data between platforms according to the embodiment; and FIG. 8 is an exemplaw and schematic diagram illustrating a processing procedure performed by a reception processing thread according to the embodiment as a sequence diagram.

DETAILED DESCRIPTION

The following describes an embodiment and a modification of the present disclosure based on the drawings. Configurations of the embodiment and the modification described below, and functions and effects caused by the configurations are merely examples, and are not limited to the content described below.

Embodiment FIG. I is an exemplary and schematic block diagram illustrating the entire configuration of an information processing system I according to an embodiment. As illustrated in FIG. I, the information processing system 1 according to the embodiment includes a plurality of platforms 10-1 to 10-8, and a relay device 30. The platforms 10-1 to 10-8 are inserted into a plurality of slots on a board on which the relay device 30 is provided, for example. Due to this, the platforms 10-1 to 10-8 are connected to one another in a communicable manner via the relay device 30.

In the following description, in a case in which the platforms are not required to be distinguished from each other, an optional platform out of the platforms 10-1 to 10-8 may be simply referred to as a platform 10. FIG. 1 exemplifies a configuration in which the information processing system 1 includes the eight platforms 10, but it is sufficient that the number of the platforms 10 is plural, not limited to eight, in the embodiment.

The following describes a case in which communication between the platform 10 and the relay device 30 is performed in accordance with a communication standard based on Peripheral Component Interconnect-Express (PCIe) (registered trademark), but communication may be performed in accordance with a communication standard other than the PCIe (registered trademark) in the embodiment.

The platforms 10-1 to 10-8 each include a host device that functions as a control unit and a Graphical User Interface (GUI) of the information processing system 1, and an arithmetic device that performs Artificial Intelligence (Al) inference processing, image processing, and the like. In the following description, by way of example, it is assumed that the platform 10-1 functions as the host device, and the platforms 10-2 to 10-8 function as arithmetic devices. The platforms 10-2 to 10-8 as the arithmetic devices may have functions different from each other, or at least some of the platforms 10-2 to 10-8 may have a common function.

The platforms 10-1 to 10-8 include root complexes 11-1 to 11-8, respectively, and the relay device 30 includes end points 31-1 to 31-8 corresponding to the root complexes 11-1 to 11-8, respectively. In the following description, in a case in which the root complexes and the end points are not required to be distinguished from each other, an optional root complex of the root complexes 11-1 to 11-8 may be simply referred to as a root complex 11, and an optional end point of the end points 31-1 to 31-8 may be simply referred to as an end point II.

FIG. I exemplifies a configuration in which the platform 10 corresponds to the root complex 11 on a one-to-one basis, but the platform 10 does not necessarily correspond to the root complex 11 on a one-to-one basis in the embodiment. For example, in the embodiment, one platform 10 may include two or more root complexes 11.

The platform 10 and the relay device 30 described above have hardware configurations illustrated in the following FIG. 2.

FIG. 2 is an exemplary and schematic block diagram illustrating the hardware configurations of the platform 10 and the relay device 30 of the information processing system 1 according to the embodiment.

First, the following describes the hardware configuration of the platform 10.

As illustrated in FIG. 2, the platform 10-1 includes the root complex 11-1, a processor 12-1, a memory 13-1, and a storage unit 14-1. These pieces of hardware (circuitry) are connected to one another in a communicable manner via a bus (not illustrated).

The other platforms 10-2 to 10-8 each have the same hardware configuration as that of the platform 10-1. That is, the platforms 10-2 to 10-8 respectively include the root complexes 11-2 to 11-8, processors 12-2 to 12-8, memories 13-2 to 13-8, and storage units 14-2 to 14-8.

In the following description, in a case in which the processors, the memories, and 2 0 the storage units are not required to be distinguished from each other, an optional processor of the processors 12-1 to 12-8 may be simply referred to as a processor 12, an optional memory of the memories 13-1 to 13-8 may be simply referred to as a memory 13, and an optional storage unit of the storage units 14-1 to 14-8 may be simply referred to as a storage unit 14.

The root complex 11 performs communication with the corresponding end point 31. In the embodiment, the root complex Ii communicates with the end point 31 in accordance with Peripheral Component Interconnect Express (PC1e) (registered trademark) as one of communication standards, for example. Alternatively, the platform 10 may communicate with the relay device 30 in accordance with another communication standard other than the PCIe (registered trademark) The processor 12 controls each unit of the platform 10. The processor 12 is constituted of, for example, a central processing unit (CPU), a micro processing unit (MPU), a digital signal processor (DSP), an application specific integrated circuit (ASIC), a programmable logic device (PLD), or a field programmable gate array (FPGA). The processor 12 may be configured as a multicore processor, or may be configured as a combination of two or more processors.

The memory 13 stores data required for control performed by the processor 12, data generated as a result of control performed by the processor 12, and the like. The memory 13 is constituted of a read only memory (ROM) and a random access memory (RAM), for example. The ROM stores, for example, various pieces of software (computer programs) executed by the processor I 2, data for the software, and the like, and the RAM provides a working area for executing the software stored in the ROM to the processor 12.

The storage unit 14 stores, for example, various pieces of data including various pieces of software (computer programs) executed by the processor 12, data to be transmitted/received to/from the other platform 10, and the like (in a non-volatile manner). The storage unit 14 is, for example, constituted of a hard disk drive (HDD), a Solid State Drive (SSD), a Storage Class Memory (SCM), and the like.

The platform 10 executes the computer programs stored in the memory 13 or the storage unit 14 by the processor 12 to implement various functions for performing Al inference processing or image processing.

The computer program described above is not necessarily stored in the memory 13 or the storage unit 14. For example, the computer program described above may be provided as a computer program product that is recorded in a computer-readable recording medium such as various magnetic discs including a flexible disk (FD) or various optical discs including a Digital Versatile Disk (DVD) in an installable format or an executable format.

The computer program described above may be provided or distributed via a network such as the Internet. That is, the computer program described above may be provided in a state of being stored in a computer connected to a network such as the Internet to be downloaded from the computer over the network.

Next, the following describes the hardware configuration of the relay device 30 that relays communication between the platforms 10.

As illustrated in FIG. 2, the relay device 30 includes the end point 31, a processor 32, a memory 33, a storage unit 34, an internal bus 35, and an expansion bus 36.

The end point 31 is provided so as to correspond to the platform 10. The end point 31 transmits (transfers) data from a first platform among the platforms 10 to a second platform different from the first platform via the expansion bus 36.

For example, when the root complex 11-5 transmits data to the platform 10-1 by Direct Memory Access (DMA) transfer, the relay device 30 receives the data from the end point 31-1 corresponding to the root complex 11-5 via the expansion bus 36, and transfers the received data to the platform 10-1.

The processor 32 controls each unit of the relay device 30. The processor 32 is constituted of a CPU, an MP U, a DSP, an AS1C, a PLD, or an FPGA, for example. The processor 32 may be configured as a multicore processor, or may be configured as a combination of two or more processors.

2 0 The memory 33 stores data required for control performed by the processor 32, data generated as a result of control performed by the processor 32, and the like. The memory 33 is constituted of, for example, a ROM and a RAM.

The storage unit 34 stores various pieces of data (in a non-volatile manner). The storage unit 34 is constituted of, for example, an HDD, an SSD, and an SCM.

The relay device 30 executes computer programs stored in the memory 33 or the storage unit 34 by the processor 32 to implement various functions for relaying communication between the platforms 10.

The internal bus 35 connects the processor 32, the memory 33, the storage unit 34, and the expansion bus 36 to one another in a communicable manner.

The expansion bus 36 connects the end points 31 to the internal bus 35 in a communicable manner. Due to this, the expansion bus 36 enables data transfer among the end points 31, that is, data transfer among the platforms 10. The expansion bus 36 is a bus conforming to the PCIe (registered trademark), for example.

Based on the hardware configuration as described above, the platform 10 according to the embodiment implements a software configuration illustrated in the following FIG. 3. FIG. 3 is an exemplary and schematic diagram illustrating the software configuration of the platform 10 according to the embodiment.

As illustrated in FIG. 3, the platform 10-1 as the host device implements a Basic Input Output System (BIOS) 202, an operating system (OS) 203, a driver 204, a service 205, a virtual local area network (LAN) driver 206, a distributed control unit 207, and common software 208. Based on the software configuration, the platform 1 0-I executes an application 209 to control a personal computer (PC) platform 201 as a hardware resource included in the platform 10-1.

The BIOS 202 executes reading of the OS 203 at the time of activation of the platform 10-1, basic input/output control for the platform 10-1, and the like. The OS 203 is, for example, Windows (registered trademark), but may be another OS.

The OS 203 accesses the root complex 11-1 of the platform 10-1 by reading various 2 0 drivers 204 including a bridge driver 204A for controlling the expansion bus described above, and performs communication with the other platform 10. The OS 203 performs various pieces of processing by reading the service 205 for performing various kinds of control.

The virtual LAN driver 206 and the distributed control unit 207 are implemented on an upper layer of the driver 204 and the service 205. The common software 208 is implemented on an upper layer of the virtual LAN driver 206 and the distributed control unit 207 and on a lower layer of the application 209. Due to this, by accessing the virtual LAN driver 206 via the common software 208, the application 209 performs communication with the other platform 10 assuming that the other platform 10 is present on a virtual LAN.

On the other hand, the platforms 10-2 and 10-3 as the arithmetic devices implement a Bootloader 212, an OS 213, a driver 214, a virtual LAN driver 215, a distributed control unit 216, and common software 217. Based on the software configuration, the platforms 10-2 and 10-3 respectively perform distribution processing A and distribution processing B, and controls hardware platforms 211 as hardware resources included in the platforms 10-2 and 10-3.

For the sake of simplification, FIG. 3 illustrates only software configurations of the platforms 10-2 and 10-3, but in the embodiment, the other platforms 10-4 to 10-8 as the arithmetic devices may implement the same software configuration as that of the platforms 10-2 and 10-3.

The Bootloader 212 is activated at the time when a power supply of the corresponding platform 10 is turned on to activate the OS 213. The OS 203 is, for example, Linux (registered trademark), but may be another OS.

The OS 213 accesses the corresponding root complex 11 by reading various drivers 214 including a bridge driver 214A for controlling the expansion bus described above, and performs communication with the other platform 10.

The virtual LAN driver 215 and the distributed control unit 216 are implemented on an upper layer of the driver 214. The common software 217 is implemented on an upper laver of the virtual LAN driver 215 and the distributed control unit 216, and on a lower layer of corresponding distribution processing. Due to this, by accessing the virtual LAN driver 215 via the common software 217, the distribution processing A and the distribution processing B perform communication with the other platform 10 assuming that the other platform 10 is present on the virtual LAN.

Based on the software configuration described above, the information processing system 1 according to the embodiment performs communication processing illustrated in the following FIG. 4 at the time of communication between the platforms 10. FIG. 4 exemplifies communication processing between the platform 10-1 as the host device and the platform 10-5 as the arithmetic device, but communication processing between the other platforms 10 may be similarly performed.

FIG. 4 is an exemplary and schematic diagram for explaining communication processing performed by the information processing system 1 according to the embodiment.

As illustrated in FIG. 4, the information processing system 1 has a layer structure including a predetermined number of layers. The information processing system 1 performs communication between the platforms 10 via the layers.

For example, the following describes a case in which software of the platform-10-1 as the host device transmits (transfers) data to the platform 10-5 as the arithmetic device. In this case, the software of the platform 10-1 transfers the data to a physical layer of the relay device 30, more specifically, to a physical layer corresponding to the end point 31-1 to which the platform 10-1 is connected, via a transaction layer, a data link layer, and a physical layer (PHY) of the platform 10-1.

In a case in which the data is transferred to the physical layer corresponding to the end point 31-1, the relay device 30 passes the data to the transaction layer via the data link layer. In the transaction layer, the relay device 30 transfers the data to the end point 31-5 to which the platform 10-5 is connected by tunneling. The relay device 30 then transfers the data transferred by tunneling to the physical layer of the platform 10-5 via the data link layer and the physical layer corresponding to the end point 31-5.

The platform 10-5 passes the data transferred from the relay device 30 to the software via the physical layer, the data link layer, and the transaction layer.

In this way, in the embodiment, data transfer from the platform 10-1 to the platform 10-5 is implemented by tunneling of the data in the transaction layer of the relay device 30.

Data transfer from the platform 10-5 to the platform I0-I is implemented when the data moves through the layers in order reverse to the order described above.

In the embodiment, in a case in which data transfer from the other platform 10 does not concentrate on a specific platform 10 data transfer may be performed between a plurality of optional different groups of platforms 10 in parallel.

That is, in a case in which a plurality of pieces of communication from the other platforms 10 concentrate on the specific platform 10, the relay device 30 serially processes the pieces of communication from the other platforms 10. However, in a case in which the different platforms 10 communicate with each other and the pieces of communication do not concentrate on the specific platform 10, the relay device 30 can process the pieces of communication between the platforms 10 in parallel.

In the embodiment, transmissiotheception of the data between the platforms 10 s performed via a buffer for transmission (a transmission buffer) 502 provided in each platform 10 as illustrated in the following FIG. 5. In FIG. 5, the relay device 30 is not illustrated, but transmission/reception of the data between the platforms 10 by Direct Memory Access (DMA) is relayed by the relay device 30 as described above with reference to FIG. 4, FIG. 5 is an exemplary and schematic diagram for explaining transmission/reception of the data via the buffer for transmission 502 according to the embodiment.

As illustrated in FIG. 5, each platform 10 includes the buffer for transmission 502 as a storage region into which the data to be transmitted to each platform 10 is written.

Herein, buffers for transmission 502-1 to 502-8 respectively included in the platforms 10-1 to 10-8 are collectively referred to as the buffer for transmission 502 (however, FIG. 5 illustrates only the buffers for transmission 502-1 and 502-5). The buffer for transmission 502 is implemented on the memory 13, for example.

In the example illustrated in FIG. 5, similarly to the example illustrated in FIG. 4 described above, it is assumed that the data is transmitted from the platform 10-5 to the platform 10-I. Thus, the following mainly describes transmission/reception of the data via the buffer for transmission 502-5 of the platform 10-5, In the example illustrated in FIG. 5, first, at Step S501, the virtual LAN driver 206 of the platform 10-5 issues, for example, a transmission request for the data to the platform 10-1 to a region indicated by Slot#0 in the buffer for transmission 502-5 of the platform 10-5.

Herein, the region indicated by Slot#0 is a region for transmitting data to the platform 10-1. The buffer for transmission 502-5 includes a plurality of regions for transmitting the data to the other platforms 10 in addition to an address range indicated by Slot#0.

At Step S502, the bridge driver 214A of the platform 10-5 writes the data to be transmitted to the platform 10-1 into the region indicated by Slot#0 in response to the transmission request described above.

At Step S503, the relay device 30 (not illustrated in FIG. 5) connects the end point 31-5 corresponding to the platform 10-5 to the end point 31-1 corresponding to the platform 10-I through processing such as an Endpoint to Endpoint communication (EP-toEP).

When writing of the data at Step S502 described above is ended, the bridge driver 214A of the platform 10-5 makes a reception request for the data via the relay device 30 to the platform 10-1.

At Step S504, the bridge driver 204A of the platform 10-1 acquires the data from the platform 10-5 via the relay device 30 in response to the reception request from the platform 10-5, and stores the acquired data in a storage unit 1401 via a buffer provided in the memory 13-1.

In this way, the data is transmitted from the platform 10-5 to the platform 10-1 via the relay device 30.

As illustrated in FIG. 5, the buffer for transmission 502-1 similar to the buffer for transmission 502-5 of the platform 10-5 is provided in the platform 10-1. The platform 10-I can transmit the data to the other platform 10 by utilizing the buffer for transmission 5021, Additionally, although not illustrated in FIG. 5, the other platforms 10 also include the similar buffers for transmission 502. Thus, in the embodiment, transmission/reception of the data between optional platforms 10 can be implemented by the same processing as the processing described above.

The processing procedure as described above can be represented as a sequence diagram as illustrated in the following FIG. 6.

FIG. 6 is an exemplary and schematic sequence diagram illustrating a processing procedure performed by the information processing system 1 at the time of transmission/reception of the data between the platforms 10 according to the embodiment.

By way of example, the following describes transmission (transfer) of the data from the platform 10-5 to the platform 10-1. In the example illustrated in FIG. 6, the virtual LAN driver 215 and the bridge driver 21 4A of the platform 10-5 are respectively illustrated as a "transmitting side virtual LAN driver" and a "transmitting side bridge driver", and the bridge driver 204A of the platform 10-1 is illustrated as a "receiving side bridge driver".

As illustrated in FIG. 6, in the embodiment, first, at Step S610, the virtual LAN driver 215 as the transmitting side virtual LAN driver makes a transmission request for the data to the platform 10-1 to the bridge driver 214A as the transmitting side bridge driver. At Step S620, the bridge driver 214A writes the data to be transmitted into a region for transmitting the data to the platform 10-1 in the buffer for transmission 502-5 of the platform 10-5 in response to the transmission request from the virtual LAN driver 215. At this point, the bridge driver 214A sets the region of the buffer for transmission 502-5 into which the data is written, to be a locked region prevented from overwriting.

At Step S630, the bridge driver 214A makes a reception request for the data to the bridge driver 204A as the receiving side bridge driver via the relay device 30.

At Step S640, the bridge driver 204A of the platform 10-1 acquires the data from the buffer for transmission 502-5 via the relay device 30 in response to the reception request from the bridge driver 2I4A. At this point, a flag of "transmission/reception is completed" is set to a point (region) at which acquisition of the data is completed in the buffer for transmission 502-5.

At Step S650. the bridge driver 204A transmits a reception completion notification to the bridge driver 214A via the relay device 30 in accordance with completion of acquisition of the data.

At Step S660, in response to the reception completion notification from the bridge driver 204A, the bridge driver 214A releases a region where transmission/reception of the written data is completed in the buffer for transmission 502-5. The release of the buffer for transmission 502 can be performed by setting the locked region prevented from ovenvriting in the buffer for transmission 502 to be an unlocked region where overwriting is allowed. Whether transmission/reception of the data is completed is determined based on the flag of "transmission/reception is completed" described above and the like.

The example illustrated in FIG. 6 is merely an example. In the embodiment, there may be a case in which the bridge driver 204A or 214A of the other platform 10 other than the platform 10-5 is the transmitting side bridge driver, and the bridge driver 214A of the other platform 10 other than the platform 10-1 is the receiving side bridge driver.

In transmission/reception of the data via the buffer for transmission 502 as described above, a semaphore may be used to implement exclusive control over execution of a reception processing thread for acquiring the data from the buffer for transmission 502. In this case, for example, the platform 10 on a side of receiving the data releases one of semaphores (that is, the platform 10 increments a value of semaphore by one) in response to the reception request from the platform 10 on a side of transmitting the data, and the reception processing thread advances acquisition of the data after acquiring the one released semaphore (that is, after decrementing a value of semaphore by one).

The semaphore is a variable used for controlling computer programs operating in parallel. In the present disclosure, semaphores are set to control operations of a plurality of threads present in the information processing system 1. For example, it is assumed that execution of a specific group of threads is controlled by using the semaphore. In a state where an initial value of the semaphore is 0, any thread in the group of threads cannot operate, and the group of threads is kept being in a stand-by state. At this point, when any thread in the group of threads or another computer program "releases" the semaphore, the semaphore is incremented to be 1. Any of the threads, which has confirmed that the semaphore is "released" to be 1, "acquires" the semaphore and decrements the semaphore to be returned to be 0 to start to operate.

Typically, in a case of performing thread management using the semaphores, the number of threads to be concurrently executed is controlled by releasing the semaphores corresponding to the number of threads to be operated and causing each of the threads to acquire the semaphore. As another method of using the semaphore, the semaphore is used to control execution and stop the thread in a case where the number of threads to be operated is one at the maximum. In this case, typically, control is performed such that the semaphore has a value of 1 or 0. Then, the thread is executed when the semaphore's value is 1, and the thread is stopped when the semaphore's value is 0.

From the viewpoint described above, with the configuration in which a plurality of the platforms 10 are disposed such as the information processing system 1 according to the embodiment, there may be a case in which communication between the platforms 10 is frequently caused. In this case, the number of semaphores to be released (that is, an incremental amount of a semaphore value) becomes extensive in a short time. On the other hand, the reception processing thread that is executed after acquiring one released semaphore typically acquires data that is transferred via the relay device 30 as much as possible.

Thus, in a case where the number of semaphores to be released is extensive, when executing the same number of reception processing threads as the number of semaphores to be released, the reception processing thread may be repeatedly performed although there is no data that should be acquired. As a result, communication performance may be deteriorated due to waste of resources of the processor 12.

Therefore, in the present embodiment, a threshold indicating an upper limit of the number of semaphores to be released is set based on the processing as illustrated in the following FIG. 7.

FIG. 7 is a sequence diagram illustrating a release processing procedure for the semaphore performed by the platform 10 on a receiving side at the time of transmission/reception of the data between the platforms 10 according to the embodiment.

In the example illustrated in FIG. 7, similarly to the examples illustrated in FIG. 5 and FIG. 6, assumed is a time of transmitting (transferring) the data to the platform 10-1 from the platform 10-5. In the example illustrated in FIG. 7, the OS 203, the bridge driver 204A, and the virtual LAN driver 206 of the platform 10-1 are respectively illustrated as a "receiving side OS", a "receiving side bridge driver", and a "receiving side virtual LAN driver".

As illustrated in FIG. 7, in the embodiment, first, at Step 5710, the OS 203 as the receiving side OS receives a reception request. This reception request is the same as that transmitted from the transmitting side bridge driver at Step S630 described above.

In response to the reception request, the OS 203 instructs the virtual LAN driver 206 as the receiving side virtual LAN driver to activate processing of controlling the number of the semaphore to be released in a range equal to or smaller than the threshold described above via the bridge driver 204A being the receiving side bridge driver. More specifically, the OS 203 outputs an activation instruction to the bridge driver 204A at Step S720, and the bridge driver 204A outputs an activation instruction to the virtual LAN driver 206 at Step S730.

The virtual LAN driver 206 then determines whether the number of released semaphores (that is, the present value of semaphore) is smaller than the threshold. For example, assuming that the threshold is N, the virtual LAN driver 206 determines whether the number of released semaphores is equal to or smaller than N-1. The virtual LAN driver 206 then performs processing at Step S740 only in a case in which the number of released semaphores is equal to or smaller than N-1.

At Step S740, the virtual LAN driver 206 increments the semaphore to release one semaphore. The semaphore is typically managed by the OS 203, so that release of the semaphore is executed by using an OS call, for example.

In the embodiment. N as the threshold may be set to be I, or may be set to be a value larger than 1 (for example, 100). N as the threshold may also be set as a variable value. In this case, N as the threshold may be set considering a load on the processor 12. For example, N as the threshold may be set in accordance kith performance of the processor 12 acquired at the time of activation of the platform 10. The load on the processor 12 may vary depending on a time zone in which the platform 10 works, so that N as the threshold may be set in accordance with the time zone in which the platform 10 works.

In a case in which it is determined that the number of released semaphores (the present value of semaphore) is larger than N-! in the determination processing described above, or a case in which the processing at Step 5740 described above is performed in accordance with the determination result that the number of released semaphores (the present value of semaphore) is equal to or smaller than N-i, the virtual LAN driver 206 notifies the OS 203 of completion of the processing via the bridge driver 204A. More specifically, at Step S750, the virtual LAN driver 206 notifies the bridge driver 204A of completion of the processing, and at S760, the bridge driver 204A notifies the OS 203 of completion of the processing.

In this way, in the embodiment, the virtual LAN driver 206 functions as a semaphore control driver that controls the number of semaphores to be released in a range equal to or smaller than the threshold (for example, N). ha a case in which a direction of transmission/reception of the data is reverse to that described above, the virtual LAN driver 215 may function as the semaphore control driver. The threshold described above for the semaphore is set by the semaphore control driver, for example.

In the embodiment, in accordance with the processing as described above, the reception processing thread for acquiring the released semaphores and performing reception of the data is executed as illustrated in the following FIG. 8, FIG. 8 is an exemplary and schematic diagram illustrating a processing procedure performed by the reception processing thread according to the embodiment as a sequence diagram.

The processing illustrated in FIG. 8 specifically represents the processing at Step S640 illustrated in FIG. 6 described above. Thus, the reception processing thread is executed by the receiving side bridge driver. In the example illustrated in FIG. 8, similarly to the example illustrated in FIG. 6, assumed is a case in which the data is transmitted (transferred) from the platform 10-5 to the platform 10-1.

As illustrated in FIG. 8, in the embodiment, first, the bridge driver 204A as the receiving side bridge driver determines whether the number of released semaphores (the present value of semaphore) is equal to or larger than 1. This determination processing loops until it is determined that the number of released semaphores is equal to or larger than 1. In a case in which it is determined that the number of released semaphores is equal to or larger than 1, processing at Step S810 is performed.

At Step S810, the bridge driver 204A acquires one semaphore, and exit the loop of the determination processing. Similarly to release of the semaphore, acquisition of the semaphore is executed by using an OS call, for example.

At Step S820, the bridge driver 204A performs reception processing for acquiring the data transferred via the relay device 30 as much as possible. At the time when the reception processing is completed, the reception completion notification at Step 5650 illustrated in FIG. 6 described above is output. The process then returns to the determination processing described above.

As described above, the virtual LAN driver 206 (or 215) as the semaphore control driver according to the embodiment controls the semaphore in response to the reception request transmitted from the bridge driver 214A (or 204A) as the transmitting side bridge driver. The semaphore is data for implementing exclusive control over execution of the reception processing thread for acquiring the data from the buffer for transmission 502.

The semaphore control driver switches whether to release the semaphore or not in accordance with a comparison result between the threshold and the number of released semaphores (that is, the present value of semaphore).

With the configuration as described above, the number of semaphores to be released can be limited by the threshold. Due to this, in a case in which communication between the platforms 10 is frequently caused, the number of semaphores to be released can be prevented from being extensive in a short time. As a result, it is possible to suppress the disadvantage as described above that the reception processing thread is repeatedly executed although there is no data that should be acquired, and it is possible to prevent communication performance from being deteriorated due to waste of resources of the processor 12.

In the embodiment, the threshold described above may be set as a variable value.

With this configuration, it is possible to prevent the communication performance from being deteriorated in various situations with a variable threshold.

More specifically, in the embodiment, the threshold described above may be set in accordance with the performance of the processor 12 of the platform 10 acquired at the time of activation of the platform 10 on a side of receiving the data, or the time zone in which the platform 10 operates. With this configuration, an appropriate threshold can be set while appropriately considering the load on the processor 12.

Modification In the embodiment described above, the PCIe (registered trademark) is exemplified as an I/0 interface of each unit, but the I/0 interface is not limited to the PCIe (registered 2 0 trademark). For example, the 1/0 interface of each unit may be a technique of performing data transfer between a device (peripheral control controller) and a processor via a data transfer bus. The data transfer bus may be a general-purpose bus that can transfer data at high speed in a local environment provided in one housing and the like (for example, one system or one device). The I/O interface may be any of a parallel interface and a serial 2 5 interface.

The I/O interface may have a configuration that can make point-to-point connection, and can serially transfer data on a packet basis. In a case of serial transfer, the 1/0 interface may include a plurality of lanes. A layer structure of the I/0 interface may include a transaction layer for generating and decoding a packet, a data link layer for performing error detection and the like, and a physical layer for converting between serial and parallel. The I/O interface may include a root complex on the uppermost layer including one or a plurality of ports, an end point as an I/0 device, a switch for increasing the port, a bridge for converting a protocol, and the like. The I/0 interface may multiplex, using a multiplexer, data to be transmitted and a clock signal to be transmitted. In this case, a receiving side may separate the data from the clock signal using a demultiplexer.

With the information processing system, the platform, and the computer-readable program according to the present disclosure, communication performance can be prevented from being deteriorated, in a case in which communication between the platforms is frequently caused.

While certain embodiments have been described, these embodiments have been presented by way of example only, and are not intended to limit the scope of the inventions. Indeed, the novel methods and systems described herein may be embodied in a variety of other forms: furthermore, various omissions, substitutions and changes in the form of the methods and systems described herein may be made without departing from the spirit of the inventions. The accompanying claims and their equivalents are intended to cover such forms or modifications as would fall within the scope and spirit of the inventions.

Claims (5)

1. CLAIMSAn information processing system comprising: a plurality of platforms; and a relay device configured to connect the platforms to one another via an expansion bus in a communicable manner, wherein the plurality of platforms includes a first platform and a second platform, the first platform comprises a first bridge driver configured to, in response to a transmission request for data to the second platform, write the data into a transmission buffer of the first platform, and transmit, to the second platform, a reception request for the data, and the second platform comprises: a semaphore control driver configured to, in response to the reception request transmitted from the first bridge driver, control a semaphore for implementing exclusive control over execution of a reception processing thread for acquiring the data from the transmission buffer of the first platform, the semaphore control driver controlling the semaphore by switching whether to release the semaphore or not in accordance with a comparison result between a threshold and a number of semaphores having been released; and a second bridge driver configured to, when a semaphore having been 2 0 released is present, acquire the semaphore having been released, acquire the data from the transmission buffer via the expansion bus, and transmit, to the first platform a reception completion notification for the data.
2. 2. The information processing system according to claim I wherein the threshold is set as a variable value.
3. 3. The information processing system according to claim 2, wherein the threshold is set in accordance with: performance of a processor of the second platform acquired at the time of activation of the second platform; or a time tone in which the second platform operates.
4. 4. A platform included in a plurality of platforms connected to one another in a communicable manner via an expansion bus by a relay device, the plurality of platforms including a first platform and a second platform, the platform as the second platform comprising: a semaphore control driver configured to, in response to a reception request for data transmitted from the first platform, control a semaphore for implementing exclusive control over execution of a reception processing thread for acquiring data from a transmission buffer of the first platform, the semaphore control driver controlling the semaphore by switching whether to release the semaphore or not in accordance with a comparison result between a threshold and a number of semaphores having been released, the first platform being configured to, in response to a transmission request for the data to the second platform, write the data into the transmission buffer and transfer the data to the second platform; and a bridge driver configured to, when a semaphore having been released is present, acquire the semaphore having been released, acquire the data from the transmission buffer, and transmit, to the first platform, a reception completion notification for the data.
5. 5. A computer-readable program comprising instructions executed by a computer as a platform included in a plurality of platforms connected to one another in a communicable manner via an expansion bus by a relay device, the plurality of platforms including a first platform and a second platform, the instructions causing the computer as the second platform to: in response to a reception request for data transmitted from the first platform, control a semaphore for implementing exclusive control over execution of a reception processing thread for acquiring data from a transmission buffer of the first platform, the control of the semaphore including switching whether to release the semaphore or not in accordance with a comparison result between a threshold and a number of semaphores having been released, the first platform being configured to. in response to a transmission request for the data to the second platform, write the data into the transmission buffer and transfer the data to the second platform; and, when a semaphore having been released is present, acquire the semaphore having been released, acquire the data from the transmission buffer. and transmit. to the first platform, a reception completion notification for the data.