GB2586491A

GB2586491A - Signal processing device

Info

Publication number: GB2586491A
Application number: GB1912010.4A
Authority: GB
Inventors: Gao Yue; Qi Haoran
Original assignee: Queen Mary University of London
Current assignee: Queen Mary University of London
Priority date: 2019-08-21
Filing date: 2019-08-21
Publication date: 2021-02-24
Also published as: GB201912010D0

Abstract

A signal processing apparatus comprises: a signal sampling module comprising a signal input unit configured to receive an input signal which includes a multiband frequency spectrum, a signal splitter 101 configured to split the input signal along a plurality of branches 102a,b,…, and a plurality of analogue-to-digital converters (ADC) 103a,b,…, wherein each branch comprises a respective ADC to sample the input signal; and a clock distribution module 300 configured to generate a plurality of unique and random delays for each branch, such that the timing at which the input signal in each branch is sampled by each respective ADC is offset from one another, wherein the plurality of unique and random delays are generated based on delay values stored in the clock distribution module. A random number generation unit 215 updates the values stored in module 200 with new generated values. A digital signal recovery module 200 recovers the signals output from the ADCs. The random delays are said to remove performance degradation fixed delay lines experience with certain kinds of sparse signals.

Description

SIGNAL PROCESSING DEVICE

FIELD OF THE INVENTION

[0001] The present invention relates generally to signal sampling and reconstruction, and particularly to a system for sampling and reconstructing multi-band signals.

BACKGROUND

[0002] Spectrum sensing is a way to survey ambient spectrum availability information, which is required for applications such as dynamic spectrum access where spectrum holes that are not utilised can be dynamically accessed. Wideband spectrum sensing (WSS) being implemented in real-time has required sampling and processing of the wideband spectrum at the Nyquist rate. This is becoming increasingly challenging as wideband devices continue to evolve towards millimetre-wave (mm-wave) frequency bands. Traditional WSS techniques have employed narrowband radio receivers which sequentially scan every narrow band across the whole spectrum of interest. Such implementations mean that dynamic radio activities cannot readily be sensed. Therefore, real-time WSS is desired to deliver reliable spectrum sensing performance.

[0003] Compressive sensing (CS) techniques have been introduced to achieve real-time spectrum sensing at the sub-Nyquist rate, eliminating the need for the complexity and high cost of analog-to-digital converters (ADCs) operating at the Nyquist rate. Several practical baseband processing architectures have been proposed to obtain the compressed signal using CS techniques, including random demodulator, multicoset sampler, and modulated wideband converter (MWC). The multicoset sampler has a simpler hardware architecture than the MWC, inheriting the configurations of filterbank reconstruction systems based on interleaved ADCs. The multicoset sampler employs multiple parallel ADCs sampling various time shifted versions of the baseband signal at a fraction of the Nyquist rate.

[0004] The present invention aims to practically implement the multicoset sampler, which has not yet been realised in practice. A major challenge has been to control the timing offsets for each of the parallel ADCs in the multicoset sampler due to instantaneous multi-gigahertz bandwidth signals. The timing offset at each of the parallel ADCs should be at steps of the Nyquist period (i.e. the inverse of the Nyquist frequency). For example, if the frequency spectrum being sampled has a bandwidth of 2 GHz, the timing offset step should be around 500 ps, and the error tolerance of the offset should be only a fraction of the 500 ps to minimise the error due to imperfect timing in the obtained samples. Proposals for the implementation of the multicoset sampler in the literature have relied on fixed delay lines of differing lengths to achieve time-shifted versions of the baseband signal. However, fixed delay lines may suffer from performance degradation with certain kinds of sparse signals. In practice, the delays should be reconfigurable in order to obtain the optimal performance of the signal reconstruction. The present invention aims to provide a multicoset sampler with reconfigurable delays.

SUMMARY

[0005] In accordance with the present invention, a signal processing apparatus comprises a signal sampling module comprising a signal input unit configured to receive an input signal which includes a multiband frequency spectrum, a signal splitter configured to split the input signal along a plurality of branches, and a plurality of analog-to-digital converters. Each branch comprises a respective analog-to-digital converter to sample the input signal. The signal sampling module further comprises a clock distribution module configured to generate a plurality of unique and random delays for each branch, such that the timing at which the input signal in each branch is sampled by each respective analog-to-digital converter is offset from one another, wherein the plurality of unique and random delays are generated based on delay values stored in the clock distribution module.

[0006] In an embodiment, the signal processing apparatus further comprises a delay value generator unit configured to generate the delay values and update the stored delay values in the clock distribution module.

[0007] In an embodiment, the plurality of unique and random delays are a plurality of phase offset clock signals and each analog-to-digital converter comprises a clock reference signal input arranged to receive a respective phase offset clock signal from the clock distribution module.

[0008] In an embodiment, the clock distribution module comprises a reference clock signal and a delay-locked-loop circuit comprising a plurality of identical delay gates, wherein a subset of the plurality of identical delay stages are selected, in dependence on the stored delay values, as the plurality of phase offset clock signals.

[0009] In an embodiment, the clock distribution module comprises a clock distribution unit comprising a clock signal input, a fan-out buffer configured to split the clock signal input into a plurality of paths, a plurality of counter-dividers, each path comprising a respective counter-divider, wherein each counter-divider is provided with a counter value and an initial count value.

[0010] In an embodiment the clock distribution unit comprises a phase-locked loop with a prescaling divider and an in-loop divider, connected between the clock signal input and the fan-out buffer.

[0011] In an embodiment, each of the plurality of counter-dividers is provided with a synced reset configured to synchronise the plurality of counter-dividers.

[0012] In an embodiment, the clock signal input comprises a reference source selection multiplexer configured to select between a local reference oscillator and an external clock signal input as the clock signal.

[0013] In an embodiment, the initial count values of each of the plurality of counter-dividers are determined based on the stored delay values.

[0014] In an embodiment, the clock distribution module comprises a master clock distribution unit, and a plurality of slave clock distribution units. The reference source selection multiplexer of the master clock distribution unit is configured to select the local reference oscillator as the master clock distribution unit clock signal input, and the reference source selection multiplexer of each of the slave clock distribution units is configured to select the external clock signal input as the slave clock distribution unit dock signal input. An output of the master clock distribution unit is connected to the clock signal input for each of the plurality of slave clock distribution units and the outputs of each of the slave clock distribution units correspond to the outputs of the clock distribution module. The initial count values for the counter-dividers of the master dock distribution unit are set to the same value, and the initial count value for each of the counter-dividers for each of the slave clock distribution units is determined based on the stored delay values [0015] In an embodiment, the transmission lines between the fan-out buffer and each of the outputs of the dock distribution unit along each of the paths are length-matched [0016] In an embodiment, the transmissions lines between the signal splitter and each of the analog-to-digital converters in each of the branches are length-matched.

BRIEF DESCRIPTION OF THE FIGURES

[0017] The invention is described below with reference to exemplary embodiments and the accompanying drawings, in which: Figure 1 shows a signal processing apparatus; Figure 2 shows a clock distribution module; Figure 3 shows the clock distribution module of Figure 2 in a master-slave configuration; and Figure 4 shows an alternative clock distribution module.

DETAILED DESCRIPTION

[0018] The general theory of sub-Nyquist sensing of a wideband and multiband spectrum based on the multicoset model is described in Y. Ma, Y. Gao, Y.-C. Liang, and S. Cui, "Reliable and Efficient Sub-Nyquist Wideband Spectrum Sensing in Cooperative Cognitive Radio Networks," IEEE Journal on Selected Areas in Communications, vol. 34, no. 10, pp. 2750-2762, 2016, and M. Mishali, Y. C. Eldar, "Blind multiband signal reconstruction: Compressed sensing for analog signals", IEEE Trans. Signal Process., vol. 57, no. 3, pp. 9931009, Mar. 2009.

[0019] Referring to the above documents, an analog signal x(t) is evenly segmented into L channels, or blocks. The multicoset sampler selects certain samples from each block, each block containing L consecutive samples. Within each block, a constant set C of length p describes the indexes of the p samples that are actually sampled in each block. The set C = tc}I?=1 is referred to as the sampling pattern where 0 < < *** < c L -1.

I

[0020] The measurement sequence of the ith sample sequence for 1 < <p is defined as lx(nT), n = mL + c" m E Z (1) xcr[n.] = 0, otherwise.

[0021] The sampling stage can be implemented by p uniform sampling sequences with period 1/LT, where the ith sampling sequence is shifted by ciT from the origin, where 1/T is the Nyquist rate. The periodic non-uniform sampling of the multicoset sampler can be realised by implementing p parallel cosets (or branches), each of which takes uniform samples at time instants (mLT + ciT), each parallel coset responsible for sampling one of the respective values of c, described above.

[0022] In order to reconstruct the signal, compressive sensing theories indicate that a randomly structured selection of distinct delays, corresponding to the set C = {cd,, can be used to achieve a high probability of successful reconstruction of the input signal.

[0023] Figure 1 shows an arrangement of a signal processing apparatus 10 that can operate as a multicoset sampler. The signal processing apparatus 10 includes an analog signal sampling module 100. The signal sampling module 100 includes a signal input unit (not shown) which receives an input signal In an embodiment, the input signal is a multiband signal whose frequency support is sparsely spread out over the entire frequency spectrum, i.e. the frequency spectrum within the frequency range off E [--' -The signal input unit 2T2T may be an antenna or any wideband radio-frequency receiver, such a superheterodyne receiver or a direct-conversion receiver. The signal sampling module 100 receives the analog input signal and converts it into a digital signal.

[0024] The input signal is transmitted to a signal splitter 101, which is arranged to split the input signal along a plurality of branches 102a, 102b,.... In an embodiment, the signal splitter 101 is a power splitter which outputs a plurality of identical copies of the input signal. In an embodiment, the sampling module 100 optionally includes a low-noise amplifier before the signal splitter 101 to compensate for the energy losses that occur in the signal splitter. [0025] The output of the signal splitter 101 is transmitted along the plurality of branches 102a, 102b, ... to a plurality of analog-to-digital converters (ADCs) 103a, 103b,... . Each branch 102 transmits the input signal to a respective one of the ADCs 103. Optionally, the lengths of the transmission lines of each of the branches 101 are matched. This may ensure that the input signal is transmitted to each of the ADCs 103 simultaneously. Each ADC 103 samples the input signal and outputs a digital signal. Each of the ADCs 103 may include a clock reference signal input to receive a clock signal. The clock signal received by each ADC 103 determines the timing at which the ADC samples the input signal.

[0026] The signal processing apparatus 10 includes a clock distribution module 300. The clock distribution module generates a plurality of unique and random delays. The clock distribution module provides a unique and random delay to each branch 102. This results in the input signal in each branch 102 being sampled by the respective ADC 103 in each branch at a timing that is offset from the timing at which the other ADCs sample the input signal The clock distribution module 300 may include a memory which stores delay values which are used to generate the unique and random delays. In an embodiment, the delay values correspond to the set C = fcilc_, previously described. Changing the delay values results in the plurality of unique and random delays to be changed. This results in a clock distribution module 300 which can generate reconfigurable and controllable delays.

[0027] In an embodiment, the clock distribution module 300 is a clock distribution unit 400 as shown in Figure 2. The clock distribution unit 400 includes a clock signal input unit 410 to provide a clock distribution unit clock signal to the clock distribution unit 400. The clock distribution unit 400 also includes a fan-out buffer 430 to split and transmit the clock distribution unit clock signal along a plurality of paths 431. This produces a plurality of identical copies of the clock distribution unit clock signal along each path 431 a, 43]b..... The clock distribution unit 400 also includes a plurality of counter-dividers 440a, 440b,...

Each path 431a, 431b, transmits the clock signal to a respective counter-divider 440a, 440b,... . [0028] Each counter-divider 440 is provided with a counter value N, and an initial count value between 0 and N-1. The count value of each counter-divider 440 increases by 1 at each rising edge (or falling edge) of the clock signal. The value of the counter-divider 440 returns to 0 at the next rising edge (or falling edge) if the count value is N-1. Each counter-divider 440 generates a rising edge of an output signal on the transition of the counter value of N-1 to 0, and generates a falling edge on the transition of the counter value from N/2-1 to N/2. The counter-dividers function as frequency dividers that output a signal with a frequency of 1/N of the input signal frequency. Each counter-divider 440 may be implemented by a synchronous counter formed from a ring of D flip-flops. The counter values are determined by the number of D flip-flop stages and the feedback logic, i.e. the number of flip-flops states in a cycle. [0029] In an embodiment, each counter-divider 440 is provided with the same counter value N, but a different initial count value. The clock distribution unit 400 outputs a plurality of clock signals with the same frequency, which are phase shifted from one another based on the difference in initial count values.

[0030] The initial count values of each of the counter-dividers 440 are determined in dependence on the delay values stored in a memory 450 of the clock distribution unit 400. As described in Al/shall & Eldar referenced above, each of the delay values ci can take a value between 0 and L -1. However, the counter value N may be different from L. The delay values ci may be multiplied by a factor of N/L in order to arrive at the initial count values for each of the counter-dividers 440.

[0031] In an embodiment, the clock signal input 410 includes an external clock signal input 411, a local reference oscillator 412, and a reference source selection multiplexer 413. In such an embodiment, it is possible to select between the local reference oscillator and an external dock signal as the clock distribution unit clock signal. The reference source selection multiplexer 413 is any suitable device which can select between a pair of inputs and output the selected input to a single output line.

[0032] In an embodiment, the clock distribution unit 400 additionally includes a phase-locked-loop (PLL) 420. The PLL may be arranged between the clock signal input 410 and the fan-out buffer 430. The PLL includes a phase detector 421, a low-pass loop filter 422, a voltage-controlled oscillator 423, and an in-loop divider 424. The clock distribution unit 400 may additionally include a prescaling divider 415 before the PLL 420. The prescaling divider and/or the PLL may function as frequency multiplier in order to multiply the frequency of the clock signal input, and may be implemented as a synchronous counter formed from a ring of D flip-flops. The frequency multiplication settings of prescaling divider 415 and the in-loop divider 424 may be independently set in advance. The PLL allows the clock distribution module to output a fractional or multiple frequency signal of the clock signal input with its phase aligned to the phase of the clock signal input.

[0033] In an embodiment, the plurality of counter-dividers 440 are provided with a synced-reset function. The synced reset function provides each of the counter-dividers 440 with their respective initial count value. The synced reset function also synchronises the counter-dividers 440 in order to ensure that they all start counting on a common rising edge (or falling edge) of the clock signal. In an embodiment, the counter-dividers 440 are D flip-flop ring counters with an asynchronous pre-set and reset. The initial value assignment may be performed by setting a logic value of 1 at the pre-set or the reset, which initialises the state of each D flip-flop to be 1 or 0 respectively. The initial values of each of the counter-dividers are set by a user who inputs the desired initial count values of each of the counter-dividers 440 in advance.

[0034] In an embodiment, each of the paths 431a, 431b, ... are length matched. This is to ensure that the phase offset clock signals are generated based on the delay values, and not due to analog delays introduced by unmatched transmission path lengths.

[0035] An exemplary configuration of the clock distribution unit is now described. The bandwidth B of the input signal is 2 GHz which is divided into 50 channels L, and the number of parallel cosetsp is 4. As described in Ala et al., at page 2753, the sampling rate of the ADCs and thus the desired output frequency of the clock distribution unit may be set to B/L= 2 GHz/50 = 40 MHz. The reference source selection multiplexer 413 is set to select the local

S

reference oscillator operating at 10 MHz, the prescaling divider 415 is set to a frequency multiplication value of 10, the in-loop divider is set to a frequency multiplication value of 40, the fan-out buffer 430 splits the clock signal into 4 paths 430a-d, and each counter-divider 440a-d is set with a count value N=100. The randomly generated delay values c1 -c4 are 2, 32, 37, and 40, which result in initial count values for the four counter-dividers 430a-430d of 4, 64, 74, and 80. The clock signal output by each of the counter-dividers 440 can be shown to be equal to ci/B. Thus the clock distribution outputs 4 phase offset clock signals, each offset from the local reference oscillator clock signal by 1 ns, 16 ns, 18.5 ns and 20 ns. [0036] In an embodiment as shown in Figure 3, the clock distribution module 300 may be formed from multiple clock distribution units 400 connected together in a master-slave configuration. The master clock distribution unit 400M is connected to two slave clock distribution units 400S. The number of outputs of each of the clock distribution units is 4, however it will be appreciated that each of the clock distribution units may have any number of outputs, and any number of slave clock distribution units may be connected to the master clock distribution unit 400M. The clock distribution module 400 allows for such configurability by the nature of its design. This contributes to the reconfigurability of the delays because both the delay timings, and the number of branches of the signal sampling module 100 to which delays can be provided, are reconfigurable.

[0037] The clock distribution units 400 shown in Figure 3 are generally the same as the clock distribution unit 400 described above in relation to Figure 2. However, in the present embodiment, the master clock distribution unit 400M is set so that the reference source selection multiplexer 413M selects the local reference oscillator 412M as the master clock distribution unit clock signal input, and the reference source selection multiplexers 413S of each of the two slave clock distribution units 400S are set to receive an external clock signal 411S.

[0038] The initial count values of the counter-dividers 440M of the master clock distribution unit 400M are set to the same value, so that the master clock distribution unit 400M outputs a plurality of synchronised clock signals all with the same phase. Each of the counter-dividers 440S of the slave clock distribution units 400S are provided with initial count values determined based on the delay values stored in the clock distribution module memory. In the embodiment as shown in Figure 3, an output from the master clock distribution unit 400M is connected to the external clock signal input for each of the slave clock distribution units 400S, and an output of the master clock distribution unit 400M is provided as synchronisation signal as part of the synced reset function for each of the two slave clock distribution units 400S. This ensures that the slave clock distribution units 400S have a clock signal which is in phase with the clock signal generated by the master clock distribution unit. Where a clock distribution unit 400 is manufactured with a fixed number of clock signal outputs, connecting together multiple clock distribution units 400 allows for a scalable device.

[0039] In another embodiment, the clock distribution module is a clock distribution unit 500 as shown in Figure 4, which employs a delay-locked-loop (DLL) architecture. The clock distribution unit 500 includes a reference source oscillator 501 which provides a clock signal for the clock distribution unit 500. The clock distribution unit 500 includes a delay chain 504 composed of a plurality of delay gates 505a, 505b, 505c,... connected in series, output to input. In an embodiment, the number of delay gates 505 is determined by the number of narrowband channels L, and is greater than or equal to the number of channels L, or is a multiple of L The output of the last delay gate of the delay chain 504, along with the clock signal from the reference source oscillator 501 are also provided to a phase comparator 502.

The phase comparator 502 produces an error signal based on the phase of the last delay gate output compared to the phase of the clock signal from the reference source oscillator. The error signal is provided to a loop filter 503, which generates a control voltage to be provided to each of the delay gates 505 in the delay chain 504.

[0040] The outputs of each stage of the delay chain 504 (the outputs from each delay gate 505a, 505b,...) are connected to a multiplexer 506. The multiplexer 506 outputs a subset of the signals from plurality of delay gates 505 as the phase offset clock signals of the clock distribution unit 500. The selection of the signals is determined in dependence on the delay values stored in the clock distribution unit. The delay step of the outputs from each stage of the delay chain 504 can be calculated as the period of the reference source oscillator 501 divided by the number of delay gates.

[0041] In an embodiment, the signal processing apparatus 10 includes a random number generation unit 215. The random number generation unit is configured to generate the delay values ct and to update the stored delay values in the memory of the clock distribution module 300. The random number generation unit 215 may regenerate the delay values at predetermined time intervals. This may ensure that the signal processing apparatus may accurately sample the input signal without significant performance degradation due to specific randomly selected delays. The delay values may be pseudorandom numbers generated by selecting uniformly random out of C!/(C -P)! possible permutations as indicated in "E. J. Candes, J. Romberg, and T. Tao, "Robust uncertainty principles: Exact signal reconstruction from highly incomplete frequency information," IEEE Trans. h?f: Theory, vol. 52, no. 2, pp. 489-509, Feb. 2006." [0042] In an embodiment, the signal processing apparatus 10 includes a digital signal recovery module 200. The digital signal recovery module 200 is connected to the analog signal sampling module 100. In an embodiment, the digital signal recovery module 200 may reconstruct the input signal based on the outputs from the plurality of ADCs 103.

Alternatively or additionally, the digital signal recovery 200 module may identify the power spectrum (i.e. the channel occupancy) based on the outputs from the plurality of ADCs 103.

In practice, the signal reconstruction error increases if the signal-to-noise ratio of the received sub-Nyquist samples from the plurality of ADCs is increased. For reconstruction of the input signal, a low error tolerance is desired in order to have a satisfactory reconstruction of the original input signal. However, even with a high signal-to-noise ratio the power spectrum and channel occupancy may still be accurately obtained.

[0043] In practice, only a finite-length samples can be obtained by each coset, i.e. 'C.; [n] = x. [n] * w1[n] for n = 0,1, -, N -1, where N is the number of samples for each coset per sensing round and w1 [n] for n = 0,1, * * * , N -1 denotes the window function of each coset. Denote the frequency-domain presentation of the analog input signal x(t) by its Fourier transform X(f). Denote the N-point discrete Fourier transform (DFT) of x[n] by X[k] := v A I -1 [n] exp( j2Tcnk / N). Similarly the DFT of each coset's samples can be linked to 2.,n=0 the frequency-domain presentation g(f) of 37(0, which is a windowed version of x(t) denoted by 3t (0: = x(t)w(t), writing Xi[k] = -BL exp 1-j27-cc1D * 1+.

exp (-prcci -L nI3) L(2) Nicat where w(t) is the continuous-time-domain presentation of the primitive window function.

Discrete-time window function w1 [n] is related to the primitive continuous-time window function w(t) by n = 0,1, ---, N -1 Select the frequency-domain indices k = 0, 1, , N -1 according to the interested period f E [0, B/L] and the relationship f = -from (2), and (2) is reorganised as

NL (3)

(kB) inB\ YT[k] = eXp (71271-0 Yir n=7+1 L L) L) (1. 72)) g (kB) _11(nB) 2.71;i1,13,exp(-j2n-ci k.2 (4) km,/ 2 L) where 17.i [Id:= * X[k] exp (-j27rci j*..) for k = 0,1, * ,N -1. A single-measurementvector (SMV) model expression can be directly written for each k = 0, 1, * N -1 based on (4), [k] = L..a g p a t -1211-clic Kji[k]i (5) IT2[k] =A kNL g (kB re; [k] Y[k] C.BIL 2) - kfilL 2 X cp[k]

NL 2) ± L) L) L)-

which is then rewritten by vector denotations Y[k] = f3' * A" [k]Ijk] = A-l[k] (6) If we stack the N column vectors -1c[k] and y[k] into matrices XL xN and ifrp,<N respectively, the linear system (5) can be expressed by a multi-measurement-vector (MMV) model, P = (7) The baseband processing architecture of the multicoset sampler is illustrated in Figure 1. Recovering a row-sparse matrix from compressed measurements 17 under the dictionary A is a fundamental problem in CS literature. Specifically, for multicoset samplers, one should set cis as distinct integers, i.e. ci E (0,1, ***, L -1) and ci for i j, making the dictionary A partial Fourier basis, with which the recovery performance is guaranteed by its minimal mutual coherence among all randomly structured dictionaries.

[0044] The digital signal recovery module 200 recovers information about the input signal by performing a sparse recovery operation. A sparse recovery operation is the reconstruction of the signal from sub-Nyquist samples using compressive sensing techniques, such as those described in Mishali & Eldar and Ma et all As described above, only a finite number of samples may be obtained in practice. The sparse recovery operation involves obtaining 111 samples from the set of m possible samples given by equation (1). A sample acquisition frame may thus include samples taken with m = 0, 1, 2, , M -1. Each sparse recovery operation may occur after a frame has been acquired, with a period of M/LT, corresponding to the frame acquisition time. Acquiring samples in frames in this manner can allow for the input signal to be obtained and processed in real-time. Alternatively Q consecutive frames may be accumulated into a single frame, which is obtained with a frame acquisition time of QM/LT.

[0045] The signal recovery module 200 may include a plurality of frame accumulation units 211, with each frame accumulation unit 211 being provided in each branch 102. Each frame accumulation unit 211 is arranged configured to calculate the sum of successive frames which converts multiple frames to a single accumulated frame as described above This may reduce the frame generation rate to an extent where real-time signal reconstruction is practically implementable. The number of accumulated frames Q of the frame accumulation unit 211 may be determined in dependence on the signal processing times of window function units 212, Fast Fourier transform units 213, and a sparse recovery and decision making module 214. Real-time signal recovery and decision making can be achieved if the accumulated frame acquisition time QM/LT is no less than the total signal processing latencies of the window function units 212, Fast Fourier transform units 213, and the sparse recovery and decision making module 214.

[0046] In an embodiment, the signal recovery module 200 includes a plurality of window function units 212. Each branch 102 is provided with a respective window function unit 212.

Each window function unit is arranged to apply a window function to the discreet signal output by the respective ADC to alleviate the effect of spectrum leakage, especially the energy leaked from occupied channels to vacant channels in the vvideband frequency spectrum. In an embodiment, the window function units 212 apply the respective window functions to the acquired frames of data. Any suitable windowing function may be used, for example Nanning, Hamming, Kaiser, and/or Chehyshei, windows.

[0047] The signal reconstruction module 200 includes a plurality of Fast Fourier transform (FFT) units 213, each branch 102 being provided with a FFT unit 213. Each FFT unit 213 is arranged to implement a discreet Fourier transform required in accordance with the theory in the cited papers.

[0048] The outputs of each of the branches 102 of the signal processing apparatus 10 are provided to the sparse recovery and decision making module 214. The sparse recovery and decision making module 214 is arranged to determine whether a specific channel in the frequency spectrum is occupied or vacant, during or after signal reconstruction. The input signal may first be reconstructed, and then the channel occupancy (spectrum support) is determined in dependence on the reconstructed signal. Alternatively, the channel occupancy (i.e. spectrum support) is first determined before the signal is reconstructed. Tn some embodiments, the random numbers are regenerated at each sparse recovery operation. [0049] The above-described embodiments serve to provide a teaching of how to practically implement a multicoset sampler. In particular, the embodiments described herein aim to teach how to implement a multicoset sampler with reconfigurable delays. Numerous modifications and variations will be apparent to the skilled person in light of the present invention which is defined by the following claims. The present invention is not intended to be limited to the specific means of generating offset clock signals in the above description, and is intended to cover numerous variations of how a plurality of phase offset clock signals may be generated, in accordance with the common general knowledge of the skilled person.

Claims

CLAIMS1. A signal processing apparatus comprising: a signal sampling module comprising: a signal input unit configured to receive an input signal which includes a multiband frequency spectrum, a signal splitter configured to split the input signal along a plurality of branches, and a plurality of analog-to-digital converters, wherein each branch comprises a respective analog-to-digital converter to sample the input signal; and a clock distribution module configured to generate a plurality of unique and random delays for each branch, such that the timing at which the input signal in each branch is sampled by each respective analog-to-digital converter is offset from one another; wherein the plurality of unique and random delays are generated based on delay values stored in the clock distribution module.
2. The signal processing apparatus of claim 1, further comprising a delay value generator unit configured to generate the delay values and update the stored delay values in the clock distribution module.
3. The signal processing apparatus of any one of claims 1 to 2, wherein the plurality of unique and random delays are a plurality of phase offset clock signals, wherein each analog-to-digital converter comprises a clock reference signal input arranged to receive a respective phase offset clock signal from the clock distribution module
4. The signal processing apparatus of claim 3, wherein the clock distribution module comprises: a reference clock signal; and a delay-locked-loop circuit comprising a plurality of identical delay gates, wherein a subset of the plurality of identical delay stages are selected, in dependence on the stored delay values, as the plurality of phase offset clock signals.
5. The signal processing apparatus of claim 3, wherein the clock distribution module comprises a clock distribution unit comprising: a clock signal input; a fan-out buffer configured to split the clock signal input into a plurality of paths; a plurality of counter-dividers, each path comprising a respective counter-divider, wherein each counter-divider is provided with a counter value and an initial count value.
6. The signal processing apparatus of claim 5, wherein the clock distribution unit comprises a phase-locked loop with a prescaling divider and an in-loop divider, connected between the clock signal input and the fan-out buffer.
7 The signal processing apparatus of any one of claims 5 to 6, wherein each of the plurality of counter-dividers is provided with a synced reset configured to synchronise the plurality of counter-dividers
8. The signal processing apparatus of any one of claims 5 to 7, wherein the clock signal input comprises a reference source selection multiplexer configured to select between a local reference oscillator and an external clock signal input as the clock signal.
9. The signal processing apparatus of any one of claims 5 to 8, wherein the initial count values of each of the plurality of counter-dividers are determined based on the stored delay values.
10. The signal processing apparatus of claim 8, wherein the clock distribution module comprises a master clock distribution unit, and a plurality of slave clock distribution units; wherein the reference source selection multiplexer of the master clock distribution unit is configured to select the local reference oscillator as the master clock distribution unit clock signal input, and the reference source selection multiplexer of each of the slave clock distribution units is configured to select the external clock signal input as the slave clock distribution unit clock signal input; wherein an output of the master clock distribution unit is connected to the clock signal input for each of the plurality of slave clock distribution units; wherein the outputs of each of the slave clock distribution units correspond to the outputs of the clock distribution module; wherein the initial count values for the counter-dividers of the master clock distribution unit are set to the same value, and the initial count value for each of the counter-dividers for each of the slave clock distribution units is determined based on the stored delay values.
11. The signal processing apparatus of any one of claims 5 to 10, wherein the transmission lines between the fan-out buffer and each of the outputs of the clock distribution 10 unit along each of the paths are length-matched
12. The signal processing apparatus of any of the preceding claims wherein the transmissions lines between the signal splitter and each of the analog-to-digital converters in each of the branches are length-matched