GB2576282B - Hardware unit for performing matrix multiplication with clock gating - Google Patents

Hardware unit for performing matrix multiplication with clock gating Download PDF

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Publication number
GB2576282B
GB2576282B GB1916780.8A GB201916780A GB2576282B GB 2576282 B GB2576282 B GB 2576282B GB 201916780 A GB201916780 A GB 201916780A GB 2576282 B GB2576282 B GB 2576282B
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GB
United Kingdom
Prior art keywords
hardware unit
matrix multiplication
clock gating
performing matrix
gating
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Active
Application number
GB1916780.8A
Other versions
GB2576282A (en
GB201916780D0 (en
Inventor
Martin Chris
Pulimeno Azzurra
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Imagination Technologies Ltd
Original Assignee
Imagination Technologies Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Imagination Technologies Ltd filed Critical Imagination Technologies Ltd
Priority to GB2012011.9A priority Critical patent/GB2584228B/en
Priority to GB1916780.8A priority patent/GB2576282B/en
Priority claimed from GB201718296A external-priority patent/GB2568085B/en
Publication of GB201916780D0 publication Critical patent/GB201916780D0/en
Publication of GB2576282A publication Critical patent/GB2576282A/en
Application granted granted Critical
Publication of GB2576282B publication Critical patent/GB2576282B/en
Active legal-status Critical Current
Anticipated expiration legal-status Critical

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Classifications

    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F7/00—Methods or arrangements for processing data by operating upon the order or content of the data handled
    • G06F7/38—Methods or arrangements for performing computations using exclusively denominational number representation, e.g. using binary, ternary, decimal representation
    • G06F7/48—Methods or arrangements for performing computations using exclusively denominational number representation, e.g. using binary, ternary, decimal representation using non-contact-making devices, e.g. tube, solid state device; using unspecified devices
    • G06F7/544—Methods or arrangements for performing computations using exclusively denominational number representation, e.g. using binary, ternary, decimal representation using non-contact-making devices, e.g. tube, solid state device; using unspecified devices for evaluating functions by calculation
    • G06F7/5443—Sum of products
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F17/00—Digital computing or data processing equipment or methods, specially adapted for specific functions
    • G06F17/10—Complex mathematical operations
    • G06F17/16—Matrix or vector computation, e.g. matrix-matrix or matrix-vector multiplication, matrix factorization
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F7/00—Methods or arrangements for processing data by operating upon the order or content of the data handled
    • G06F7/38—Methods or arrangements for performing computations using exclusively denominational number representation, e.g. using binary, ternary, decimal representation
    • G06F7/48—Methods or arrangements for performing computations using exclusively denominational number representation, e.g. using binary, ternary, decimal representation using non-contact-making devices, e.g. tube, solid state device; using unspecified devices
    • G06F7/52—Multiplying; Dividing
    • G06F7/523—Multiplying only

Landscapes

  • Engineering & Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • General Physics & Mathematics (AREA)
  • Theoretical Computer Science (AREA)
  • Pure & Applied Mathematics (AREA)
  • Mathematical Analysis (AREA)
  • Mathematical Optimization (AREA)
  • Computational Mathematics (AREA)
  • Mathematical Physics (AREA)
  • Computing Systems (AREA)
  • Data Mining & Analysis (AREA)
  • General Engineering & Computer Science (AREA)
  • Algebra (AREA)
  • Databases & Information Systems (AREA)
  • Software Systems (AREA)
  • Complex Calculations (AREA)
GB1916780.8A 2017-11-03 2017-11-03 Hardware unit for performing matrix multiplication with clock gating Active GB2576282B (en)

Priority Applications (2)

Application Number Priority Date Filing Date Title
GB2012011.9A GB2584228B (en) 2017-11-03 2017-11-03 Hardware unit for performing matrix multiplication with clock gating
GB1916780.8A GB2576282B (en) 2017-11-03 2017-11-03 Hardware unit for performing matrix multiplication with clock gating

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
GB201718296A GB2568085B (en) 2017-11-03 2017-11-03 Hardware unit for performing matrix multiplication with clock gating
GB1916780.8A GB2576282B (en) 2017-11-03 2017-11-03 Hardware unit for performing matrix multiplication with clock gating

Publications (3)

Publication Number Publication Date
GB201916780D0 GB201916780D0 (en) 2020-01-01
GB2576282A GB2576282A (en) 2020-02-12
GB2576282B true GB2576282B (en) 2020-09-16

Family

ID=69063411

Family Applications (1)

Application Number Title Priority Date Filing Date
GB1916780.8A Active GB2576282B (en) 2017-11-03 2017-11-03 Hardware unit for performing matrix multiplication with clock gating

Country Status (1)

Country Link
GB (1) GB2576282B (en)

Citations (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US4799183A (en) * 1985-10-24 1989-01-17 Hitachi Ltd. Vector multiplier having parallel carry save adder trees
US20120287989A1 (en) * 2011-05-13 2012-11-15 Madhukar Budagavi Inverse Transformation Using Pruning For Video Coding
US20130138711A1 (en) * 2011-11-29 2013-05-30 Junji Sugisawa Shared integer, floating point, polynomial, and vector multiplier
US20140365548A1 (en) * 2013-06-11 2014-12-11 Analog Devices Technology Vector matrix product accelerator for microprocessor integration

Patent Citations (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US4799183A (en) * 1985-10-24 1989-01-17 Hitachi Ltd. Vector multiplier having parallel carry save adder trees
US20120287989A1 (en) * 2011-05-13 2012-11-15 Madhukar Budagavi Inverse Transformation Using Pruning For Video Coding
US20130138711A1 (en) * 2011-11-29 2013-05-30 Junji Sugisawa Shared integer, floating point, polynomial, and vector multiplier
US20140365548A1 (en) * 2013-06-11 2014-12-11 Analog Devices Technology Vector matrix product accelerator for microprocessor integration

Also Published As

Publication number Publication date
GB2576282A (en) 2020-02-12
GB201916780D0 (en) 2020-01-01

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