GB2571710A

GB2571710A - Receiver apparatus

Info

Publication number: GB2571710A
Application number: GB1803299.5A
Authority: GB
Inventors: Ahmed Arslan; Berner Stephan
Original assignee: Purelifi Ltd
Current assignee: Purelifi Ltd
Priority date: 2018-02-28
Filing date: 2018-02-28
Publication date: 2019-09-11
Also published as: GB201803299D0

Abstract

A receiver for packet-based communication comprises a front end, a first analogue to digital converter (ADC) 44, a second ADC 32 having a higher power and/or speed than the first ADC, demodulation circuitry 34, and switching circuitry 41. The front end is configured to receive a signal and to produce a receiver signal. The first ADC is configured to read at least a first part of the receiver signal to obtain a first, lower-speed portion of a data packet. The demodulation circuitry is configured to process the first portion of the data packet to determine that the data packet and/or a following data packet comprises high-speed data, and/or that the data packet is directed to a user of the receiver. The switching circuitry is configured to move the second ADC from a lower-power or switched-off state to a higher-power state. The second ADC is configured, in the higher power state, to read at least a second part of the receiver signal to obtain a second higher-speed portion of the data packet. A transmitter configured to send a packet comprising two different speed portions is also claimed.

Description

Receiver apparatus

Field

The present invention relates to a receiver apparatus, in particular a low-power receiver apparatus for optical wireless communication.

Background

It is known to provide wireless data communications by using light instead of radio frequencies to transmit and receive data wirelessly between devices. Data may be transmitted using light by modulating at least one property of the light, for example the intensity of the light. Methods that use light to transmit data wirelessly may be referred to as optical wireless communications (OWC) or light communications (LC).

In Optical Wireless Communication Systems (such as LiFi) the basic scenario involves a number of Access Points (AP) that communicate with a number of Stations (STA). Both the Access Points and the Stations are full duplex devices, capable of transmitting and receiving at the same time.

The AP is connected to the internet and provides both light and data. Each AP is able to communicate with multiple stations at the same time, efficiently sharing the connection between them. Mobile stations can move from one AP to another without losing their connection to the network (the handover is done in such a way that it looks like a seamless transition to the user).

In known OWC systems a station is able to determine whether an AP is in range and/or when an AP is turned on and there is activity on an optical channel.

Optical wireless communication systems (such as LiFi) may provide packet-based communication. In packet-based systems, data is sent using data packets. Data packets may each comprise a low speed preamble followed by a low speed header followed by a high speed payload. Examples of packet-based communication standards include wireless local area network standards such as 802.11 n, ac and ax.

In packet-based systems, known methods for determining packet arrival and/or determining whether an AP is in range include maintaining the station in a high power “on state” at all times, including its optical front end and baseband apparatus, to monitor activity on the channel. This method may be inefficient and waste battery resources. High speed analogue to digital convertors (ADCs) used for the reception of high data rates may use a significant amount of power. This power consumption may be greater than systems such as handheld devices can reasonably sustain.

Another method is to periodically wake up a station to listen on a channel for possible activity and to maintain a low power mode at other times. However, using this method, parts of a data transmission may be missed and power may be wasted when the station is in an inefficient low power mode. The time available to switch from a low power mode to a high power mode may be very small.

Summary

In a first aspect, there is provided a receiver for packet-based communication. The receiver comprises a front end, a first analogue to digital converter (ADC), a second analogue to digital converter (ADC) having a higher power and/or speed than the first ADC, demodulation circuitry, and/or switching circuitry. The front end may be configured to receive a signal via a wireless or wired connection and to process the received signal to produce a receiver signal. The first ADC may be configured to read at least a first part of the receiver signal to obtain a first, lower-speed portion of a data packet. The demodulation circuitry may be configured to process the first, lower-speed portion of the data packet to determine that the data packet and/or a following data packet comprises high-speed data, and/or that the data packet is directed to a user of the receiver. The switching circuitry may be configured, in response to the determining that the data packet and/or a following data packet comprises high-speed data and/or that the data packet is directed to a user of the receiver, to move the second ADC from a lower-power state or switched-off state to a higher-power state. The second ADC may be configured, in the higher-power state, to read at least a second part of the receiver signal to obtain a second, higher-speed portion of the data packet.

Power may be saved by using the first ADC to read the lower-speed portion of the data packet and then switching to the second ADC to read the higher-speed portion of the data packet. The switching between the first ADC and second ADC may be performed substantially without loss of data from the data packet. The switching between the first ADC and second ADC may be timed such that data from the data packet continues to be read when switching from the first ADC to the second ADC, without any of the data not being read.

The moving of the second ADC from the lower-power state or switched-off state to the higher-power state may be in response to the determining that the data packet and/or a following data packet comprises high-speed data and that the data packet is directed to a user of the receiver.

The first ADC and second ADC may be configured to read the data packet substantially without loss of data from the data packet.

The first ADC and the second ADC may have substantially the same resolution. The first ADC and the second ADC may have substantially the same accuracy.

Each of the first ADC and the second ADC may have 12 bit resolution. By having high resolution (for example, 12 bit resolution), each of the first ADC and second ADC may be used to read signals modulated with high order QAM schemes.

The first ADC may have an operating frequency that is less than or equal to 500 MHz, optionally less than or equal to 250 MHz, further optionally less than or equal to 160 MHz. The first ADC may have a sample rate that is less than or equal to 1000 MSPS, optionally less than or equal to 500 MSPS, further optionally less than 320 MSPS. The first ADC may have a sample rate that is greater than 100 MSPS.

The second ADC may have a frequency that is greater than 160 MHz, optionally greater than 250 MHz, further optionally greater than 500 MHz, further optionally greater than 1000 MHz. The second ADC may have a frequency that is less than 2000 MHz.

The second ADC may have a sample rate that is greater than 500 MSPS, optionally greater than 1000 MSPS. The second ADC may have a sample rate than is less than 2000 MSPS.

A sample rate of the second ADC may be at least twice as fast as a sample rate of the first ADC, optionally at least three times as fast.

The second, higher-speed portion of the data packet may have a higher data rate than the first, lower-speed portion. The second, higher-speed portion of the data packet may have a higher bit rate than the first, lower-speed portion.

The first ADC may not be configured to read the second, higher-speed portion of the data packet. The first ADC may be configured such that is cannot read the second, higher-speed portion of the data packet. A sample rate of the first ADC may be inadequate for reading the second, higher-speed portion of the data packet.

The receiver may comprise an optical wireless communication (OWC) receiver. The demodulation circuitry may be operable to apply a decoding and/or demodulation process to receiver signals in accordance with a packet-based OWC communication protocol thereby to extract data from the receiver signals.

The second ADC may comprise a plurality of interleaved ADCs. The first ADC may comprise a selected one of the plurality of interleaved ADCs.

The receiver may comprise a plurality of interleaved ADCs. The first ADC may comprise a first subset of the plurality of interleaved ADCs. The second ADC may comprise a second, larger subset of the plurality of interleaved ADCs.

The lower-power state may comprise a standby state. The standby state may comprise a state from which the second ADC is capable of being turned on more quickly than if the second ADC were in a switched-off state.

The lower-power state may comprise a state having lower power consumption than the higher-power state.

The switched-off state may comprise a state in which at least part of the second ADC is switched off. The switched-off state may comprise a state in which the entire second ADC is switched off.

The first portion of the data packet may comprise a preamble and/or a packet header. The second portion of the data packet may comprise at least part of a packet payload.

The preamble and/or packet header may comprise a code directing the data packet to a predetermined group of receivers. The preamble and/or packet header may comprise a code directing the data packet to the receiver. The preamble and/or packet header may comprise a code directing the data packet to a predetermined user.

The switching circuitry may be configured to move the second ADC from the lowerpower state to the higher power state only if at least one of a) and b):-

a) the data packet is directed to a user associated with the receiver;

b) the preamble and/or header indicates that the data packet and/or a following data packet comprises a higher-speed section of the payload, wherein the higher-speed section of the payload cannot be read by the first ADC.

The demodulation circuitry may comprise a correlator configured to correlate the first, lower-speed portion of the data packet with at least one predetermined code. The correlator may be configured to correlate the first, lower-speed portion of the data packet with the at least one predetermined code to determine whether the first, lowerspeed portion of the data packet comprises the code directing the data packet to the predetermined group of receivers and/or the code directing the data packet to the receiver and/or the code directing the data packet to the predetermined user.

The correlating may be performed at baseband. The correlating may take place without determining any phase offset and/or carrier frequency offset.

The preamble may comprise pseudonoise. The code directing the data packet to the predetermined group of receivers may comprise pseudonoise. The code directing the data packet to the receiver may comprise pseudonoise. The code directing the data packet to the predetermined user may comprise pseudonoise.

The preamble and/or header may comprise a code indicating whether high-speed data is present. The code indicating whether high-speed data is present may comprise pseudonoise. The correlator may be configured to correlate the first, lower-speed portion of the data packet with the at least one predetermined code to determine whether the first, lower-speed portion of the data packet comprises the code indicating whether high-speed data is present.

The first portion of the data packet may further comprise a lower-speed section of the packet payload. The second portion of the data packet may comprise a higher-speed section of the packet payload.

The higher-speed section of the packet payload may have a higher data rate than the lower-speed section. The higher-speed section of the packet payload may have a higher bit rate than the lower-speed section.

The first ADC may not be configured to read the higher-speed section of the packet payload. The first ADC may be configured such that it is unable to read the higherspeed section of the packet payload. A sample rate of the first ADC may be inadequate for reading the higher-speed section of the packet payload.

A time taken to receive the packet header and/or the lower-speed section of the packet payload may be equal to or greater than a time taken for the second ADC to move from the lower-power state to the higher-power state.

The length of the packet header and/or lower-speed section of the packet payload may be equal to or greater than a time taken for the second processing circuitry to move from the lower-power state to the higher-power state. The length of the packet header may be at least twice the time taken for the second processing circuitry to move from the lower-power state to the higher-power state, optionally at least three times.

The time taken to receive the packet header may be less than 5 ps, optionally less than 1 ps. The time taken to receive the packet header may be greater than 0.1 ps, optionally greater than 0.5 ps.

No overhead (for example, dummy data) may be used to fill a time period during switching between the first ADC and second ADC. The switch from the first ADC to second ADC may occur such that there is no period during the receiving of the data packet in which neither the first ADC nor the second ADC is reading data from the data packet.

The first ADC may be further configured to operate in a lower-power state or switchedoff state while the second ADC reads at least part of the second portion of the data packet. The first ADC may be on standby in the lower-power state. The standby state may comprise a state from which the first ADC is capable of being turned on more quickly than if the first ADC were in a switched-off state. At least part of the first ADC may be switched off in the switched-off state. The entire first ADC may be switched off in the switched-off state.

The receiver may further comprise a first memory buffer configured to store signals read by the first ADC and to pass the signals read by the first ADC to the demodulation circuitry. The receiver may further comprise a second memory buffer configured to store signals read by the second ADC and to pass the signals read by the second ADC to the demodulation circuitry.

The passing of the signals read by the first ADC and/or the signals read by the second ADC to the demodulation circuitry may be delayed using the first memory buffer and/or second memory buffer. By using the first memory buffer and/or second memory buffer, the demodulation circuitry may process signals read by the first ADC during a given time period and signals read by the second ADC during the same given time period.

The light may comprise at least one of visible, infrared or ultraviolet light.

The packet-based OWC communication protocol may comprise a LiFi communication protocol. The packet-based OWC communication protocol may comprise an OWC communication protocol supporting full duplex communication.

The front end may be configured to receive light modulated at a modulation rate. The modulation rate may be at least 1 kHz, optionally at least 100 kHz, further optionally at least 1 MHz. The modulation rate may be less than 1 PHz, optionally less than 1 THz, further optionally less than 100 GHz, further optionally less than 10 GHz.

The light may be modulated with a respective modulation scheme comprising at least one of on-off keying (OOK), phase shift keying (PSK), M-ary pulse amplitude modulation (M-PAM), M-ary quadrature amplitude modulation (M-QAM) or orthogonal frequency division multiplexing (OFDM), Discrete Hartley transformation, Wavelet packet division multiplexing (WPDM), Hadamard coded modulation (HCM), pulseposition modulation (PPM), Colour shift keying (CSK), carrier-less amplitude and phase (CAP), discrete multi-tone (DMT). The modulation may be coherent or incoherent.

The receiver may comprise or form part of an OWC access point. The receiver may be integrated into a luminaire.

The front end may comprise an optical front end. The optical front end may comprise a photodetector configured to receive light and to produce detection signals in response to the received light. The optical front end may further comprise receiver circuitry configured to receive and process the detection signals to produce the receiver signals.

The front end may comprise an RF front end. The RF front end may comprise an antenna configured to receive RF signals and to produce detection signals in response to the received RF signals. The RF front end may further comprise receiver circuitry configured to receive and process the detection signals to produce the receiver signal.

In a further aspect, there is provided a method of data receiving by packet-based communication, comprising receiving a signal via a wireless or wired connection; processing the received signal to produce a receiver signal; reading, by a first ADC, at least a first part of the receiver signal to obtain a first, lower-speed portion of a data packet; processing the first, lower-speed portion of the data packet to determine that the data packet and/or a following data packet comprises high-speed data, and/or that the data packet is directed to a user of the receiver; in response to the determining that the data packet and/or a following data packet comprises high-speed data and/or that the data packet is directed to a user of the receiver, moving the second ADC from a lower-power state or switched-off state to a higher-power state; reading, by the second ADC, at least a second part of the receiver signal to obtain a second, higher-speed portion of the data packet, wherein the second ADC has a higher power and/or speed than the first ADC.

In a further aspect of the invention, there is provided a transmitter for packet-based communications comprising a first digital to analogue converter (DAC) and a second DAC, wherein the second DAC has a higher power and/or speed than the first DAC, wherein the transmitter is configured to transmit a first, lower-speed portion of a data packet using the first DAC and a second, higher-speed portion of the data packet using the second DAC.

Features in one aspect may be applied as features in any other aspect, in any appropriate combination. For example, device features may be provided as method features or vice versa.

Brief Description of the Drawings

Various aspects of the invention will now be described by way of example only, and with reference to the accompanying drawings, of which:

Figure 1 is a block diagram of a transmitter and receiver using optical wireless communication;

Figure 2 is a block diagram of a typical receiver apparatus chain;

Figure 3a is a block diagram of a receiver apparatus in accordance with an embodiment;

Figure 3b is a block diagram of a receiver apparatus in accordance with an embodiment;

Figure 4 is a block diagram showing the internal structure of a high-speed ADC in accordance with an embodiment;

Figure 5a is an illustration of a waveform of a packet comprising a low-speed preamble section, a low-speed header section and a high-speed payload section;

Figure 5b is a block diagram showing a process of powering-up a high-speed ADC while receiving the packet of Figure 5a;

Figure 6a is a block illustration of waveform of a packet comprising a low-speed preamble and a high-speed payload;

Figure 6b is a block diagram showing a process of powering-up a high-speed ADC while receiving the packet of Figure 6a;

Figure 7a is an illustration of a wavelength of a short sequence; and

Figure 7b is an illustration of waveform of a detection sequence.

Detailed Description of the Drawings

The term light herein may be used, for example, to refer to electromagnetic waves with wavelengths in a range 1 nm to 2500 nm, which includes ultraviolet, visible light and near-infrared wavelengths.

Figure 1 is a block diagram illustrating principles of optical wireless communication according to embodiments. Figure 1 shows a transmitter apparatus 10 and a receiver apparatus 14. The transmitter apparatus 10 is configured to send wireless optical signals in which information is encoded through an optical communication channel 12 to the receiver apparatus 14. The optical communication channel 12 may be a freespace communication channel. The optical communications channel 12 has a characteristic optical wavelength.

Free space communication channels include transmission of optical signals through air, space, vacuum, liquid such as water or similar.

Transmitters and receivers may be provided on different devices. One type of device that is used is an access point (AP). Access points may provide access to a further network. Another type of device is a station (STA). Stations may be portable or fixed. Without limitation, examples of stations include personal computers, desktops, laptops and smart devices, including mobile devices (for example, mobile phones, tablets or digital book readers). Portable stations may be powered by their own battery resource.

An access point may provide data transmission to and/or from a wired network or a WiFi™ or other wireless network and/or other optical wireless communications network, optionally a LiFi network.

The transmitter apparatus 10 includes a light emitting diode (LED), laser or other suitable light source, and an associated driving circuit to drive the LED or laser to produce the optical signal. The associated driving circuitry includes a digital to analogue convertor configured to provide a modulation signal at a frequency characteristic of an optical light communication signal. A further processor, provided as part of the transmitter apparatus or associated with the transmitter apparatus, modulates data onto a drive current and the driving circuitry provides the drive current to the LED or laser. The LED or laser then produces an outgoing modulated optical wireless communication signal that carries the data.

The receiver apparatus 14 includes a photodiode, or other suitable light detector, with associated circuitry to condition any received signal. The photodiode converts received light to an electronic signal which is then conditioned by the conditioning circuitry. Conditioning may include one or more filter steps; amplification of a weak electrical signal; equalisation of received signals and converting the analogue signals into digital signals using an analogue to digital convertor. The digital signal can then be provided to a further processor, provided as part of the receiver apparatus or associated with the receiver apparatus, to be demodulated to extract communication data. An example of a typical receiver apparatus is described in more detail with reference to Figure 2 where the conditioning circuitry and further processor correspond to an optical front end module and a baseband processor resource.

Any suitable modulation scheme may be used. For example orthogonal frequency division multiplexing (OFDM) modulation schemes are used in some embodiments, and the demodulation is from the OFDM modulation scheme. In further embodiments and without limitation, other modulation schemes may be used, for example on-off keying (OOK), phase shift keying (PSK), M-ary pulse amplitude modulation (M-PAM), M-ary quadrature amplitude modulation (M-QAM), Discrete Hartley transformation, Wavelet packet division multiplexing (WPDM), Hadamard coded modulation (HCM), pulse-position modulation (PPM), Colour shift keying (CSK), carrier-less amplitude and phase (CAP), or discrete multi-tone (DMT). The light may be modulated at a modulation rate between 1 kHz and 1 PHz, for example at a modulation rate between 1 MHz and 100 GHz.

The modulation scheme may form part of an OWC communication protocol, such that the optical signal is produced according to the OWC communication protocol. The OWC communication protocol may be packet-based.

In known transmitter and receiver pairs, the receiver apparatus 14 is switched on and may continually receive light, even when out of range of the transmitter apparatus 10 and/or when the transmitter apparatus 10 is not sending optical signals and/or when the transmitter apparatus 10 is switched off. This may prove to be a drain and/or inefficient use of battery resources of, or associated with, the receiver apparatus.

Before describing a receiver according to a specific embodiment, a typical receiver apparatus and components thereof are described. Figure 2 is an illustration of a typical receiver apparatus 20 for optical wireless communication, which may also be referred to as a receiver chain. The receiver apparatus 20 may be implemented as a PHY (physical layer) chip.

The receiver apparatus 20 of Figure 2 is comprised of a plurality of blocks, which may also be referred to as stages. These blocks are described with reference to Figure 2 and are known standard components of a typical receiver apparatus 20. When provided in the embodiments of Figure 3a and 3b, these components perform substantially the same function as in the system of Figure 2.

The receiver apparatus 20 of Figure 2 has an optical front end 22 and a baseband processing resource 24. The optical front end 22 is configured to detect light and optical wireless communication signals carried by light and produce electrical receiver signals based on the detected light. The baseband processing resource 24 is configured to receive the receiver signals and extract data from the receiver signals.

In the system of Figure 2, the optical front end 22 comprises a photodetector 26 and an amplifier block 28. The baseband processing resource 24 comprises a high-speed analogue to digital converter (ADC) 32 and a demodulator 34. In other embodiments, components shown in Figure 2 may be omitted and/or additional components not shown in Figure 2 may be added to receiver apparatus 20.

The photodetector 26 may be one of: a PIN diode, an Avalanche Photo Diode (APD), a Silicon Photomultiplier (SiPM) or similar. Although referred to as a photodetector, the photodetector 26 can be a single photodetector or a plurality of photodetectors. In some embodiments, the plurality of photodetectors are arranged in an array or a matrix. The photodetector 26 is configured to receive light and convert the received light into an electronic detection signal. In this system of Figure 2, the photodetector 26 receives light and produces a current signal.

The optical front end 22 further comprises an amplifier stage 28. In the system of Figure 2, the amplifier stage 28 comprises a trans-impedance amplifier (not shown), also referred to as a TIA, and a variable gain amplifier (not shown), also referred to as a VGA. The TIA is configured to convert the current signal from the photodetector 26 into a voltage signal. The TIA may be incorporated or integrated into the photodetector 26 itself. The VGA is configured to condition the voltage signal from the TIA so that the voltage signal input to the ADC 32 is as close as possible to the maximum input range of the ADC 32.

The VGA may allow an increased or maximised signal to noise ratio with respect to the quantization noise to be achieved. Quantization noise is generated by the finite resolution of the ADC. With optimal gain control, the ADC is driven at full range and the quantization noise is as small as possible relative to the signal power.

In other embodiments, any suitable amplifier or combination of amplifiers may be used in the amplifier stage 28.

The ADC 32 converts the input analogue voltage to a digital signal. The digital signal comprises digital samples with a fixed or variable sample rate and fixed or variable resolution. The ADC 32 is used to convert signals which may comprise both low-speed and high-speed portions (for example, a given packet may comprise both low-speed and high-speed portions). The ADC 32 is therefore chosen to have a high enough speed to accommodate the highest expected data rates. The ADC 32 may be considered to have a high speed and/or high bandwidth. In the example of Figure 2, the ADC 32 has a bandwidth between 250 MHz and 1 GHz. The ADC 32 has a sample rate between 500 and 2000 MSPS (megasamples per second).

In the example shown in Figure 2, the ADC 32 has 12 bit resolution. The ADC 32 may be considered to have a high resolution.

The samples output by the ADC 32 are processed by the baseband demodulator 34 to demodulate and/or decode signals to extract data. For example, the data may comprise a plurality of data packets, each comprising a respective preamble, header and payload.

Figure 2 shows a typical receiver chain used for receiving light, conditioning detection signals and decoding receiver signals. It will be understood that Figure 2 is illustrative of a typical chain only and other blocks or components may be provided in a receiver chain.

In the system of Figure 2, all components 26, 28, 32, 34 of the receiver chain are turned on at all times. The power consumption of the system of Figure 2 may therefore be high. The system of Figure 2 may be using substantial amounts of power even when no OWC communication is being received by the system of Figure 2. All packets received by the receiver of Figure 2 are processed, even if they are not directed to the receiver 40 (for example, if they are directed to a different receiver). Therefore, the system of Figure 2 may be using substantial amounts of power receiving packets that are not relevant to it.

Figure 3a shows an optical wireless communication receiver apparatus 40 provided in accordance with an embodiment. The receiver apparatus 40 may provide PHY layer functionality. The receiver apparatus 40 may be implemented as a PHY chip.

The system of Figure 3a comprises an optical front end 22 as described above with reference to Figure 2. The optical front end comprises a photodetector 26 and an amplifier stage 28. The system of Figure 3a further comprises a baseband processing resource 42.

The baseband processing resource 42 comprises a low-speed ADC 44, a high-speed ADC 32, a switch 41 configured to switch on the high-speed ADC 32, a switch 43 configured to switch on the low-speed ADC, a selector 45 and a demodulator 34.

The selector 45 provides a binary choice with regard to the signals that are provided to the demodulator for decoding and/or demodulation. Either signals from the low-speed ADC 44 are provided to the demodulator 34, or signals from the high-speed ADC 32 are provided to the demodulator 34.

The receiver apparatus 40 is configured to provide mid-packet switching between the low-speed ADC 44 and high-speed ADC 32 without the loss of data. The receiver apparatus 40 may use the low-speed ADC 44 to read a low-speed portion of a packet and then switch, mid-packet, to using the high-speed ADC 32 to read a high-speed portion of the same packet.

In the present embodiment, the same demodulator 34 is used to decode and/or demodulate signals from both the low-speed ADC 44 and the high-speed ADC 32. In other embodiments, different demodulators may be used for each of the ADCs.

Figure 3b is an illustration of a further embodiment. Receiver 47 of Figure 3b comprises the same components as receiver 40 of Figure 3a (including optical front end 22, lowspeed ADC 44, high-speed ADC 32, switches 41, 43, selector 45 and demodulator 34). Receiver 47 further comprises a first memory buffer 48 configured to buffer signals from the low-speed ADC 44 in memory, and a second memory buffer 49 configured to buffer signals from the high-speed ADC 32 in memory, such that signals from both the low-speed ADC 44 and high-speed ADC 32 can eventually be sent to the demodulator 34.

In the embodiments of Figure 3a and 3b, the high-speed ADC 32 has 12 bit resolution. The high-speed ADC 32 has an operating frequency between 250 MHz and 1 GHz. The high-speed ADC 32 has a sample rate between 500 MSPS and 2 GSPS.

The low-speed ADC 44 has 12 bit resolution, which is the same resolution as the highspeed ADC 32. The low-speed ADC 44 reads at a different speed than the high-speed ADC 32, but with the same accuracy. By having high resolution (in this case, 12 bit resolution), the low-speed ADC is able to be used to demodulate signals modulated with high order QAM schemes.

The low-speed ADC 44 has a lower operating frequency than the high-speed ADC 32. In the embodiments of Figure 3a and 3b, the low-speed ADC 44 has an operating frequency of up to 160 MHz. The low-speed ADC 44 has a lower sample rate than the high-speed ADC 32. A maximum speed at which the low-speed ADC 44 is configured to sample data is lower than a maximum speed at which the high-speed ADC 32 is configured to sample data. In the present embodiment, the sample rate is up to 320 MSPS. In other embodiments, the sample rate may be up to 500 MSPS.

In use, the high-speed ADC 32 is kept on standby by default. When the high-speed ADC 32 is on standby, it is in a state in which its power consumption is low.

A plurality of data packets are received by the receiver 40. For each data packet, a first portion of the data packet (for example, a first portion comprising a preamble and/or a header) comprises information about a user to which the data packet is directed. For example, some data packets may be directed to the one or more users of receiver 40. Other data packets may be directed to users of different receivers. The information about the user may be referred to as identifying data.

We consider the receiving of a single packet. The packet comprises a first low-speed portion which comprises a preamble and/or header, and a second high-speed portion which comprises at least part of a payload.

Initially, the low-speed ADC 44 is turned on and the high-speed ADC 32 is on standby. The low-speed ADC 44 converts the input analogue voltage to a digital signal that comprises digital samples. The samples are processed by the baseband demodulator 34 to demodulate and/or decode signals to extract data.

The demodulator 34 applies a packet identifier to the data extracted from the first portion of the data packet. The identifying data may be in a preamble. For example, the identifying data may be implemented as one or more PN sequences as described in more detail below. The identifying data may be in the header, for example as the receiver address in the header.

The packet identifier is used to identify whether the first portion of the data packet is directed to the receiver 40. A method of packet identification using a correlator is described below.

If the packet identifier indicates that the data packet is directed to the receiver 40, the switch 41 is operated and the high-speed ADC 32 is powered-up from standby. In the present embodiment, an initial part of the first low-speed portion of the data packet (for example, a preamble of the data packet) identifies the data packet as being for the receiver 40. The first low-speed portion also comprises a second part, which may be described as the remainder of the first low-speed portion of the data packet. For example, the remainder of the first low-speed portion may comprise at least part of the header and/or part of the payload of the packet.

The first low-speed portion of the data packet has a length such that the high-speed ADC 32 may be fully powered-up while the remainder of the first low-speed portion of the data packet is being received. The length of the first low-speed portion may be defined such that a transmission time of the first low-speed portion is longer than a power-up time of the high-speed ADC 42.

Once the high-speed ADC 32 is powered-up, the high-speed ADC 32 is used to convert the input analogue voltage for the second, high-speed portion of the data packet. Samples from the high-speed ADC 32 are selected by the selector 45 and processed by the baseband demodulator 34 to extract data from the second portion of the data packet.

After the receiving of the data packet is complete, the high-speed ADC 32 may be powered-down (for example, put into standby) and the low-speed ADC 44 may be selected by the selector 45 and used to process received signals.

If the packet identifier indicates that the data packet is not directed to the receiver 40 (for example, if the data indicates that the data packet is directed to a different receiver), the switch 41 is not operated and the high-speed ADC 32 is not powered-up. The high-speed ADC 32 may remain on standby until a packet directed to a user of the receiver 40 is received.

In the embodiment described above, the first, low-speed portion of the packet comprises identifying data that identifies a user and/or receiver to which the packet is directed.

In further embodiments, the first, low-speed portion of the packet further comprises data that indicates whether the packet comprises high-speed data, or whether the packet only comprises low-speed data. In some embodiments, the data indicating whether the packet comprises high-speed data is included in the header. In other embodiments, the data indicating whether the packet comprises high-speed data is included in the preamble, for example as a further pseudonoise sequence.

In some circumstances, for example if the receiver 40 is configured for lowest power consumption, a data packet may comprise only low-speed data. For example, the payload of the data packet may also comprise low-speed data. The data packet may be considered to comprise a first low-speed portion (for example, comprising a preamble and/or header) and a second low-speed portion (comprising the payload), and may not comprise any high-speed portion.

In some embodiments, the system of Figure 3a or Figure 3b does not turn on the highspeed ADC 44 if a data packet directed to the receiver 40 comprises only low-speed data. The system identifies that the data packet only contains low-speed data and continues to use the low-speed ADC 32 to convert the signal received for the whole packet.

In some embodiments, the system of Figure 3a or Figure 3b turns on the high-speed ADC 32 only if information in the low-speed portion of a packet indicates that the packet comprises high-speed data and is directed to a user of the receiver 40.

By using the low-speed ADC 44 to read a first, low-speed portion of the data packet (for example, a preamble and/or header), power may be saved. The high-speed ADC 32 may be powered-up only if the data packet is directed to the receiver 40 and the data packet is determined to have high-speed content. The high-speed ADC 32 may therefore be powered-up for only a small proportion of the time that the receiver 40 is in use. The reduction in power consumption may be particularly relevant to mobile devices, which may have demanding power requirements.

In some embodiments, the low-speed ADC 44 of Figure 3 is powered-on at all times. In other embodiments, the low-speed ADC 44 may be powered-down by switch 43 (for example, turned off or put on standby) when the high-speed ADC 32 is powered-on at switch 41.

In the embodiments of Figures 3a and 3b, the high-speed ADC 32 is on standby, not switched off, to reduce power-up time. In other embodiments, the high-speed ADC 32 may be switched off at switch 41.

In some embodiments, a mode of operation is used that may be described as an extreme low power mode. In the extreme low power mode, at the cost of latency, the high-speed ADC 32 is put in power off. When a high speed payload is detected, the high-speed ADC 32 is turned to standby for a next packet.

In some embodiments, a low-speed portion of a packet (for example, a preamble and/or header of the packet) contains information about a following packet or packets. The information may comprise a speed of the following packet or packets. The high speed ADC 32 may be switched on for one or more packets in response to information in an initial packet.

Therefore, information in a low-speed portion of a packet may prompt the switching on of the high-speed ADC 32 for a) the packet itself; b) the packet immediately following; c) a given number of packets; and/or d) all packets that follow until the system receives a signal to switch off the high-speed ADC 32. In some embodiments, information regarding subsequent high speed packets and/or a high speed packet end signal may be located in a proprietary MAC header.

In the embodiment of Figure 3a, the selector 45 in receiver 40 switches between using first processing circuitry comprising the low-speed ADC 44 and demodulator 34, and using second processing circuitry comprising the high-speed ADC 32 and demodulator 34. The second processing circuitry has a higher speed and higher power consumption than the first processing circuitry.

The systems of Figures 3a and b may provide a dynamic ADC switching system for receiving data using a packet-based wireless communication protocol. A low-speed, high-resolution ADC 44 detects a low speed portion of a packet comprising a packet preamble and/or header. The system reads the first low speed portion of the packet comprising the preamble and/or header and identifies that the packet is for the receiver and contains high-speed sections of the payload. The system powers up the highspeed ADC during a remainder of the first low-speed portion of the packet. The highspeed ADC is fully powered-up to receive the high-speed packet payload. Optionally, the low-speed ADC will remain on to read the low-speed portion of the payload. Optionally, the high-speed ADC will not be switched on if the payload only contains a low-speed signal, or the STA is not the intended recipient.

The system of Figure 3a or 3b may reduce idle mode power consumption. The system may increase efficiency. The system may maintain low latency and low power blocks.

Figure 4 is an illustration of a high-speed ADC 50 in accordance with an embodiment. The high-speed ADC 50 comprises a plurality of low-speed ADCs 52 which operate in an interleaved fashion. Each of the low-speed ADCs 52 has a sample rate that is a fraction, for example in this embodiment one fifth, of the overall sampling rate of the high-speed ADC 50. The high-speed ADC 50 further comprises a plurality of switches 54, each of which is configured to switch on and off a respective one of the low-speed ADCs. Figure 4 also shows a switch 56 which is configured to switch on and off the whole high-speed ADC 50.

In the embodiment shown in Figure 4, one or more low-speed ADCs 52 are kept on to provide low-speed ADC functionality, while the rest of the low-speed ADCs 52 are powered down. For example, as a default, a single low-speed ADC 52 may be switched on. The single low-speed ADC 52 that is switched on may provide the functionality of the low-speed ADC 44 described above with reference to Figure 3a.

When high-speed ADC functionality is required, the remaining low-speed ADCs 52 are powered on to provide the high-speed ADC functionality. The full high-speed ADC 50 is switched on in time to receive the payload. The full high-speed ADC 50 may be switched on when a packet preamble and/or header is identified.

In further embodiments, a single low-speed ADC 52 is switched on by default. One or more further low-speed ADCs 52 are switched on when higher-speed functionality is required. The number of further low-speed ADCs 52 that are turned on may be fewer than the total number of ADCs 52.

If fewer ADCs 52 are switched on than are present in the full ADC 50, it may be considered that a partial high-speed ADC has been switched on. For example, the system may determine a minimum number of low-speed ADCs 52 that are required to read a given payload, and may switch on that number of low-speed ADCs 52. By switching on only a subset of the ADCs 52, power consumption may be kept to a minimum.

In other embodiments, a first subset of the low-speed ADCs 52 is switched on to provide a lower-power mode (for example, a default mode and/or a mode in which lower-speed data is read) and a second, larger subset of the low-speed ADCs 52 is switched on to provide a higher-power mode (for example, a mode in which higherspeed data is read).

Each of the low-speed ADCs 52 has the same sampling rate. The higher overall sampling rate of the high-speed ADC 50 is achieved by offsetting the times at which each of the low-speed ADCs 52 samples the signal. The samples obtained by the multiple low-speed ADCs 52 are combined to provide a set of samples with a higher effective sampling rate.

A start signal is provided to each of the ADCs 52 to instruct the ADCs 52 when to sample a signal and start analogue to digital conversion. The start signals are shifted in time with respect to each other. In the high-speed ADC 50 shown in Figure 4, conversion start signals are shifted by 72° parallel to output.

In other embodiments, any suitable low-speed and high-speed ADC may be used. For example, the low-speed ADC 44 and high-speed ADC 32 may be separate components.

A data packet may be designed to facilitate use of the combination of a low-speed ADC 44 and a high-speed ADC 32 as described above with reference to Figure 3.

Figure 5a is an illustration of a waveform of a data packet in accordance with an embodiment. The data packet comprises a low-speed preamble 60, a low-speed header 64 and a high-speed payload 66.

The preamble 60 is intended for frame detection and/or synchronization, initial channel estimation and OFDM symbol alignment. In the present embodiment, the preamble 60 is specified as a 160-sample time domain sequence having the duration equivalent of two OFDM frames).

In the embodiment of Figure 5a, the preamble comprises at least one pseudonoise (PN) sequence. A pseudonoise sequence may be a sequence of values that appears to be random, for example a sequence of 1 and -1 values which appears to be random like noise. One example of a pseudonoise sequence is {1,1,-1,1,1,1,-1,-1,-1,-1,-1,1,1,1...}.

If a pseudonoise sequence is correlated with itself, the correlator output produces a main peak and sidelobes. The suitability of a pseudonoise sequence (for example, its suitability for use to convey information in a packet) may be determined based on the level and/or polarity of the sidelobes produces when the sequence is correlated with itself. Typically, a packet is considered to be detected when the output of the correlator exceeds a certain threshold. If the sidelobes are high, the margin against false detections may be low, because the sidelobes may be mistaken for the main lobe.

In the present embodiment, the system operates at baseband. It is known that the polarity of the main lobe is positive. Therefore, the pseudonoise sequence is selected so that the positive sidelobes are as small as possible.

Any suitable method of selecting pseudonoise sequences may be used. For example, for short sequences, all possible combinations may be used and compared. For longer sequences, random sequences may be tried, with a constraint on positive sidelobes.

A sequence as shown above has a flat spectrum over the whole bandwidth (white). However, the channel has a low pass response. In some embodiments, the pseudonoise sequence is oversampled and pulse shaped such that it fits better into the channel response. The pulse shape may be any suitable shape, for example a rectangle or something more smooth.

A plurality of preamble sequences have been defined, where different nodes communicating to each other can adopt different sequences. The sequences have very low cross-correlation to each other, which may reduce or eliminates the possibility for false packet detection between interfering nodes and enabling interference estimation, which in turn may enable interference management techniques at the higher MAC layer.

Barker codes are a subclass of PN sequences that have particular properties. In the present embodiment, the PN sequence in the preamble comprises a PN sequence that is not a Barker code.

The low-speed preamble 60 is followed by the low-speed header 64, which may also be referred to as a PHY-frame header. The header 64 contains information that is used for demodulating the subsequent payload 66. The header 64 fits into an integer number of OFDM symbols and is transmitted using a single, predefined set of modulation and coding parameters, i.e. 1 bit/symbol with code rate

It may be considered that the data packet comprises a first, low-speed portion which comprises the preamble 60 and the header 64; and a second, high-speed portion which comprises the payload 66. In other embodiments, some or all of the payload may be included in the first, low-speed portion of the data packet.

The first, low-speed portion 60, 64 of the packet has a lower rate of data transmission than the second, high-speed portion 66 of the packet. The current or voltage level of the first, low-speed portion 60, 64 varies more slowly with time than the current or voltage level of the second, high-speed portion 66.

The data packet of Figure 5a is designed to be used in combination with the receiver apparatus of Figure 3a. A duration of the low-speed portion of the data packet is greater than a power-up time of the high-speed ADC 32 (where the duration of the lowspeed portion is measured as a time taken for the low-speed portion to be transmitted) For example, the length of the low-speed portion may be a multiple of the power-up time of the high-speed ADC 32. The power-up time may be a time taken for the highspeed ADC to move from a standby state to a fully operational state.

By choosing a length of the low-speed portion that is greater than (optionally, a multiple of) the power-up time of the high-speed ADC 32, it may be the case that no portion of the packet is corrupted or lost while the high-speed ADC 32 powers on.

For example, a system tolerance may be a microsecond delay for power up. The length of the header may be at least a microsecond.

Figure 5b is an illustration of a timeline for reading a data packet as shown in Figure 5a using the receiver apparatus of Figure 3 (which comprises a high-speed ADC 32 and a low-speed ADC 44, each having 12 bit resolution). The time axis of Figure 5b is drawn to the same scale as the time axis of Figure 5a, such that corresponding points on the time axes of Figure 5a and 5b are representative of the same time.

Line 70 represents a power level of the low-speed ADC 44. Line 72 represents a power level of the high-speed ADC 32. Arrows 74, 76 and 78 represent events on the timeline.

Initially, the low-speed ADC 44 is powered on and the high-speed ADC 32 is on standby. At a time shown by arrow 74, a packet identifier identifies the data packet as being directed to the receiver 40. The identifying of the packet is based on the lowspeed preamble 60.

At the time shown by arrow 74, the switch 46 is turned on and the high-speed ADC 32 starts powering up. The system continues to read the data packet using the low-speed ADC 44. While the high-speed ADC 32 is powering up, the system is reading the lowspeed header 64.

At a time shown by arrow 76, the high-speed ADC 32 is fully powered-up. The highspeed ADC is fully-powered up in time to read the high-speed payload section 66..

At a time shown by arrow 78, the low-speed ADC 44 is powered-down. It may be considered that the low-speed ADC 44 is powered-down at a time at which the lowspeed ADC 44 is no longer required (because the high-speed ADC 32 is being used).

By powering down the low-speed ADC 44 when it is not required, a greater power saving may be obtained.

In the embodiment of Figures 5a and 5b, a combination of low-speed and high-speed ADCs is used. A high-speed ADC 32 is on standby (not switched off) until just before the payload arrives, to reduce power-up time. A low-speed, low-bandwidth preamble 60 and header 64 is received by a low-speed ADC 44 (which has low power and high resolution). The preamble 60 is detected and identified as for the device using a packet identifier. The high-speed ADC 32 is switched on at this point, ready to receive the high-speed section 66 of the payload 62. The low-speed, low-power, highresolution ADC 44 is capable of reading low-speed sections of the payload.

Based on the information in the preamble and/or header, a decision may be made about whether or not to turn on the high-speed ADC at all, or whether to keep the highspeed ADC in standby mode throughout the whole payload.

In some embodiments, information about whether the packet contains high-speed data is included in the header. If the preamble indicates that the packet is directed to the receiver and at least part of the header indicates that the packet contains high-speed data, the high-speed ADC is switched on. For example, the high-speed ADC may be switched on after part or all of the header has been received.

In some embodiments, information about whether the packet contains high-speed data is included in the preamble. For example, information about whether the packet contains high-speed data may be included as a further PN sequence. One PN sequence may indicate low-speed content and another may indicate high-speed content.

The system of Figure 3a, operated as shown in Figures 5a and 5b, may reduce idle power consumption and increase efficiency. The high-speed ADC 32 only reads the high-speed payload 66. The low-speed ADC 44 reads the preamble 60 and packet header 64. In other embodiments, the low-speed ADC 44 may also read a low-speed section of payload. If the packet only has low-speed payload data, then the whole packet may be decoded using the low-speed ADC 44.

Furthermore, in the system of Figure 3a there may be substantially no data loss, for example data loss caused by switching from the low-speed ADC 44 to the high-speed ADC 32. No overhead (for example, dummy data) is added to fill a time period during switching.

Figures 6a and 6b illustrate an alternative system in which it is possible that such data loss may occur in some circumstances.

Figure 6a is an illustration of a prior art data packet comprising a low-speed preamble 80 and a high-speed payload 82. The low-speed preamble 80 may comprise a binary Barker code.

A receiver used to receive the data packet of Figure 6a may have a low power listening mode with a receiver path comprising a low-power, low-resolution ADC used to read a preamble only. A separate receiver path may comprise a high-power, high-resolution ADC which is powered on from off to read the data packet payload.

The low-power low-resolution ADC is unable to read any of the packet payload. The low-power low-resolution ADC is only useful for packet detection. It cannot demodulate signals modulated on any QAM scheme.

Figure 6b is an illustration of a timeline for reading the data packet of Figure 6a using a receiver having a low-power, low-resolution ADC and a high-power, high-resolution ADC as described above. A first line 90 represents a power level of the low-power lowresolution ADC. A second line 92 represents a power level of the high-power highresolution ADC. Two arrows 94, 96 represent different points on the timeline, and bracket 98 indicates a time period on the timeline. The time axis of Figure 6b corresponds to the time axis of Figure 6a.

At a time indicated by arrow 94, the packet is identified using the low-speed, lowresolution ADC. The high-speed, high-resolution ADC starts powering up (for example, from a switched off state). At a time indicated by arrow 96, the high-speed highresolution ADC is fully powered up. However, in the example shown, the high-speed high-resolution ADC is fully powered up too late to receive all of the payload 82. The payload 82 has started to be received before the high-speed high-resolution ADC is powered up. At a time period indicated by bracket 98, the low-power low-resolution ADC is incapable of reading the high-speed payload

In the example shown in Figures 6a and 6b, if the time period between identifying a data packet(s) directed to the wireless receiver and the high-power, high-resolution ADC being fully switched on is too short, some of the packet payload may be missed. The low-power, low-resolution ADC may only be capable of reading the preamble. The low-power, low-resolution ADC may only be suitable for packet detection and not for decoding the payload 82.

In alternative embodiments, a receiver similar to that described above with reference to Figure 3 may be used for radio-frequency communications, for example Wi-Fi. For example, the optical front end may be replaced with an RF front end in which the photodetector is replaced with an antenna. The receiver may comprise a low-speed ADC and high-speed ADC.

The receiver may use a packet-based wireless communications protocol for use in the local area network (LAN), for example 802.11 and subsets. Packets may be received and processed as described above, with the system powering up the high-speed ADC on identification that a packet is directed to the receiver and comprises high-speed content. The header may have a length such that the high-speed ADC is powered-up during the transmission of the header.

In 802.11, the PHY preamble field is used for synchronization. The PHY header contains information necessary for demodulating the subsequent frame payload. The PHY header usually conveys information about the type of modulation, the coding rate as used in the rest of the packet, and the number of octets in a PSDU that the MAC is currently requesting the PHY to transmit.

We turn again to the data packet of Figure 5a. As described above, the preamble 60 of the data packet of Figure 5a comprises pseudonoise (PN) sequences and does not comprise a Barker code. The pseudonoise sequences used have higher resolution than a Barker code. The pseudonoise sequences may be considered to be optimised for a baseband application, rather than for a carrier application.

In the embodiment of Figure 5a, the preamble comprises a first PN sequence ΡΝϊ and a second PN sequence PN₂. The first PN sequence ΡΝτ is common to a group of receivers. For example, the group of receivers may be a group of receivers that all receive packets from a given AP. All packets emitted by the same AP may have the same PNt sequence.

The second PN sequence PN₂ is unique to each user. Each user has a corresponding PN₂ sequence. A given PN₂ sequence is only used for packets that are to be transmitted to the user to whom that PN₂ sequence is allocated. In some circumstances, multiple users may share a receiver.

In other embodiments, a third PN sequence PN₃ may be used to indicate whether highspeed data is present.

A packet identifier is implemented in the demodulator 34, and is used to identify at least one of the pseudonoise sequences PN^ PN₂.

The packet identifier comprises a correlator which is configured to perform crosscorrelation of data extracted from the data packet with the PN₂ sequence allocated to the user (i.e. to the receiver 40). If the PN₂ sequence generates a correlation peak in the correlator, the high-speed ADC 32 is turned on. Otherwise, the high-speed ADC 32 remains off (or on standby). The low-speed ADC 44 may be switched on at the end of the packet to wait for a next packet. The high-speed ADC 32 may be switched off at the end of the packet.

In RF, a different type of packet detection may be used. In 802.11, the preamble comprises 10 short OFDM training symbols and 2 long OFDM training symbols. A short OFDM training symbol comprises 12 subcarriers. A long OFDM training symbol comprises 53 subcarriers (including the value 0 at DC).

A short sequence is used for packet detection. The short sequence is a signal that comprises short repeating segments. An example of a short sequence is shown schematically in Figure 7a.

The signal shown in Figure 7a is divided into four repeating segments 100. The RF receiver delays the signal, and correlates the delayed signal with the incoming signal such that a segment n + 1 is correlated with its preceding segment n. The correlation creates a detection signal 102 as shown in Figure 7b.

The RF receiver may also perform a coarse frequency and phase offset estimation using the correlation process described above with reference to Figures 7a and 7b.

One difference between the correlation described above for RF communications and a PN-sequence-based detection for optical wireless communication according to an embodiment is that in optical wireless communication no up-conversion or downconversion takes place. Therefore, in an optical wireless communication embodiment, no phase offset or carrier frequency offset is present.

In some circumstances, the short-sequence-based algorithm used in Wi-Fi may not work well at baseband. The short-sequence-based algorithm may be susceptible to periodic interference. Such periodic interference may cause false packet detections if the period of the interference fits the length of the segments of the short sequence. The PN sequence may not be susceptible to periodic interference in this manner.

The robustness of the detection of a PN sequence may be determined by the length of the sequence.

The use of a PN sequence may allow an AP to address certain STA by using a matching sequence or sub-sequence.

PN-sequence-based detection may allow fine timing estimation to be performed together with packet detection. In an embodiment, a packet is detected when the correlator output exceeds a threshold. Fine timing estimation searches are performed around the detection point to find the maximum of the correlation.

Although reference is made above to a high-speed ADC and a low-speed ADC, it should be understood that the terms high-speed and low-speed are relative and are used to refer to the difference in speed between the two ADCs. In other embodiments, both the low-speed ADC and the high-speed ADC may have higher (or lower) speeds than the exemplary ADCs described. References to high-speed and low-speed may be taken to refer to a relatively higher speed and a relatively lower speed. Similarly, references to high-speed and low-speed sections of the data packet may be taken to refer to relatively higher- and relatively lower-speed sections of the data packet.

Although the description above refers to a receiver, a similar system may be applied to a digital-to-analogue converter (DAC) for low-power transmission. A transmitter may comprises a low-power, low-speed DAC and a high-power, high-speed DAC. The high power, high-speed DAC may be switched on and off to optimise transmission. A latency of transmission may not be particularly affected. By using a high-power, highspeed DAC only for high-speed content, power consumption of the transmitter may be reduced.

A skilled person will appreciate that variations of the enclosed arrangement are possible without departing from the invention. Accordingly, the above description of the specific embodiment is made by way of example only and not for the purposes of limitations. It will be clear to the skilled person that minor modifications may be made 10 without significant changes to the operation described.

Claims

CLAIMS:

1. A receiver for packet-based communication, comprising:

a front end;

a first analogue to digital converter (ADC);

a second analogue to digital converter (ADC) having a higher power and/or speed than the first ADC;

demodulation circuitry; and switching circuitry;

wherein:

the front end is configured to receive a signal via a wireless or wired connection and to process the received signal to produce a receiver signal;

the first ADC is configured to read at least a first part of the receiver signal to obtain a first, lower-speed portion of a data packet;

the demodulation circuitry is configured to process the first, lower-speed portion of the data packet to determine that the data packet and/or a following data packet comprises high-speed data, and/or that the data packet is directed to a user of the receiver;

the switching circuitry is configured, in response to the determining that the data packet and/or a following data packet comprises high-speed data and/or that the data packet is directed to a user of the receiver, to move the second ADC from a lowerpower state or switched-off state to a higher-power state; and the second ADC is configured, in the higher-power state, to read at least a second part of the receiver signal to obtain a second, higher-speed portion of the data packet.

2. A receiver according to Claim 1, wherein the moving of the second ADC from the lower-power state or switched-off state to the higher-power state is in response to the determining that the data packet and/or a following data packet comprises highspeed data and that the data packet is directed to a user of the receiver.

3. A receiver according to Claim 1 or Claim 2, wherein the first ADC and second ADC are configured to read the data packet substantially without loss of data from the data packet.

4. A receiver according to any preceding claim, wherein the first ADC and the second ADC have substantially the same resolution and/or accuracy.

5. A receiver according to any preceding claim, wherein a sample rate of the second ADC is at least twice as fast as a sample rate of the first ADC.

6. A receiver according to any preceding claim, wherein the receiver comprises an optical wireless communication (OWC) receiver, and the demodulation circuitry is operable to apply a decoding and/or demodulation process in accordance with a packet-based OWC communication protocol thereby to extract data from the receiver signal.

7. A receiver according to any preceding claim, wherein the second ADC comprises a plurality of interleaved ADCs and the first ADC comprises a selected one of the plurality of interleaved ADCs.

8. A receiver according to any preceding claim, wherein the lower-power state comprises a standby state.

9. A receiver according to any preceding claim, wherein the first portion of the data packet comprises a preamble and/or a packet header, and the second portion of the data packet comprises at least part of a packet payload.

10. A receiver according to Claim 9, wherein the preamble and/or packet header comprises at least one of a), b) and c):-

a) a code directing the data packet to a predetermined group of receivers;

b) a code directing the data packet to the receiver;

c) a code directing the data packet to a predetermined user.

11. A receiver according to Claim 10, wherein the demodulation circuitry comprises a correlator configured to correlate the first portion of the data packet with at least one predetermined code to determine whether the packet header comprises the code directing the data packet to the predetermined cell and/or the code directing the data packet to the receiver.

12. A receiver according to Claim 10, wherein the correlating is performed at baseband.

13. A receiver according to any of Claims 8 to 12, wherein the packet preamble comprises pseudonoise.

14. A receiver according to any of Claims 8 to 13, wherein the first portion of the data packet further comprises a lower-speed section of the packet payload, and the second portion of the data packet comprises a higher-speed section of the packet payload.

15. A receiver according to Claim 14, wherein the first ADC is not configured to read the higher-speed section of the packet payload.

16. A receiver according to any of Claims 8 to 15, wherein a time taken to receive the packet header and/or the lower-speed section of the packet payload is equal to or greater than a time taken for the second processing circuitry to move from the lowerpower state to the higher-power state.

17. A receiver according to any preceding claim, wherein the first ADC is further configured to operate in a lower-power state or switched-off state while the second ADC reads at least part of the second portion of the data packet.

18. A receiver according to any preceding claim, further comprising a first memory buffer configured to store signals read by the first ADC and to pass the signals read by the first ADC to the demodulation circuitry, and a second memory buffer configured to store signals read by the second ADC and to pass the signals read by the second ADC to the demodulation circuitry.

19. A receiver according to any preceding claim, wherein the light comprises at least one of visible, infrared or ultraviolet light.

20. A receiver according to any preceding claim, wherein the packet-based OWC communication protocol comprises a LiFi communication protocol and/or an OWC communication protocol supporting full duplex communication.

21. A method of data receiving by packet-based communication, comprising:

receiving a signal via a wireless or wired connection;

processing the received signal to produce a receiver signal;

reading, by a first ADC, at least a first part of the receiver signal to obtain a first, lower-speed portion of a data packet;

processing the first, lower-speed portion of the data packet to determine that the data packet and/or a following data packet comprises high-speed data, and/or that the data packet is directed to a user of the receiver;

in response to the determining that the data packet and/or a following data packet comprises high-speed data and/or that the data packet is directed to a user of the receiver, moving the second ADC from a lower-power state or switched-off state to a higher-power state;

reading, by the second ADC, at least a second part of the receiver signals to obtain a second, higher-speed portion of the data packet, wherein the second ADC has a higher power and/or speed than the first ADC.

22. A transmitter for packet-based communications comprising a first digital to analogue converter (DAC) and a second DAC, wherein the second DAC has a higher power and/or speed than the first DAC, wherein the transmitter is configured to transmit a first, lower-speed portion of a data packet using the first DAC and a second, higher-speed portion of the data packet using the second DAC.