GB2570943A

GB2570943A - Improvements in or relating to a bitmap of a pre-emption indication

Info

Publication number: GB2570943A
Application number: GB1802346.5A
Authority: GB
Inventors: Liu Guang
Original assignee: TCL Communication Ltd
Current assignee: TCL Communication Ltd
Priority date: 2018-02-13
Filing date: 2018-02-13
Publication date: 2019-08-14
Also published as: GB201802346D0

Abstract

In a wireless communication network, bitmap bits for a pre-emption indication which is associated with a time period of at least two slots are generated by grouping one or more down link symbols into one or more symbol groups; splitting each symbol group that spans at least two slots into two sub-symbol groups; re-grouping the symbol groups with the sub-symbol groups; and generating a preemption indication bit for each symbol group. The method ensures that a symbol group which is represented by a single bit does not span a slot boundary. In one embodiment each sub-symbol group is merged with a symbol group of the same slot via a logic OR of the corresponding pre-emption indication bits. In another embodiment a symbol group that spans a slot boundary is replaced by two sub-symbol groups.

Description

Improvements in or relating to a bitmap of a pre-emption indication

Technical Field

Embodiments of the present invention generally relate to wireless communication systems and in particular to devices and methods for enabling a wireless communication device, such as a User Equipment (UE) or mobile device to access a Radio Access Technology (RAT) or Radio Access Network (RAN), particularly but nor exclusively improvements in or relating to a bitmap of a pre-emption indication.

Background

Wireless communication systems, such as the third-generation (3G) of mobile telephone standards and technology are well known. Such 3G standards and technology have been developed by the Third Generation Partnership Project (3GPP). The 3^rd generation of wireless communications has generally been developed to support macro-cell mobile phone communications. Communication systems and networks have developed towards a broadband and mobile system.

The 3rd Generation Partnership Project has developed the so-called Long Term Evolution (LTE ®) system, namely, an Evolved Universal Mobile Telecommunication System Territorial Radio Access Network, (E-UTRAN), for a mobile access network where one or more macro-cells are supported by a base station known as an eNodeB or eNB (evolved NodeB). More recently, LTE is evolving further towards the so-called 5G or NR (new radio) systems where one or more cells are supported by a base station known as a gNB.

In 5G, Ultra-Reliable Low Latency Communication (URLLC) is defined as one of the key target scenario to be supported according to Section 6.0 of 3GPP TR 38.913 v0.4.0:. This indicates “The families of usage scenarios for I MT for 2020 and beyond include:

eMBB (enhanced Mobile Broadband) mMTC (massive Machine Type Communications)

URLLC (Ultra-Reliable and Low Latency Communications)”

For URLLC, a low latency is expected and the target for user plane latency should be 0.5ms for upload (UL), and 0.5ms for down load (DL).

For URLLC, a high reliability is expected according to Section 7.9 of 3GPP TR 38.913 vO.4.0:

“A general URLLC reliability requirement for one transmission of a packet is 1-1 O'⁵ for X bytes (e.g., 20 bytes) with a user plane latency of 1ms.

As a result, it is clear that URLLC services require an extremely high reliability and a short latency. To support URLLC services, 3GPP has agreed to support pre-emption at least in DL.

Referring to figure 1, in one slot of 14 symbols, the control region is at the beginning of the slot, at most 3 symbols can be configured and the data region is all the remaining symbols. As can be seen in figure 1, some or all resources of eMBB UE’s DL transmission may be punctured. If the pre-emption is not indicated to the eMBB UE, the pre-empted part is included within the receiving procedure and as a result, in most cases, the decoding will fail. To solve this problem, it was agreed to introduce a pre-emption indicator (PI) to indicate to eMBB UE which parts of the original scheduled data region are punctured so that the eMBB UE can null these parts in its receiving procedure and accordingly its DL decoding performance can be improved.

PI is carried by a group common Downlink Control Information (DCI). The PI will include a bitmap which will indicate which parts of the data region are punctured. PI is transmitted every 1, 2 or 4 slots which is configurable. On the time frequency resource block of PI periodicity by active Bandwidth, Part (BWP), two types of bitmap are defined and shown in figure 2. One is 14 x 1 which means the time span is split into 14 parts and the BWP is split into 1 part (equivalent to no splitting at all), and the other is 7 x 2 which means the time span is split into 7 parts and the BWP is split into 2 equal size parts. Without considering Cyclic Redundancy Check (CRC), at least 14 bits are required for the PI. Which bitmap to use can be configured by upper layer signaling.

The detailed procedure to generate a bitmap is given in TS 3GPP 38.213 Section 11.2.

“If the value of INT-TF-unit is 0, 14 bits of a field in DCI format 2_1 have a one-to-one mapping with 14 groups of consecutive symbols from the set of symbols where each 2 of the first ^NwT LMnt/¹⁴J·¹⁴ symbol groups includes ΓΜντ/¹⁴! symbols, each of the last ^14_λαιντ ⁺ΙΛινι7¹⁴_|·¹⁴ symbol groups includes LMnt/¹⁴J symbols, a bit value of 0 indicates transmission to the UE in the corresponding symbol group and a bit value of 1 indicates no transmission to the UE in the corresponding symbol group.

If the value of INT-TF-unit is 1, 7 pairs of bits of a field in the DC! format 2_1 have a one-to-one mapping with 7 groups of consecutive symbols where each of the first ^int -kiN_T/⁷J·⁷ symbol groups includes Γ^ιντ/⁷! symbols, each of the last 7-Nint +I#intM⁷ symbol groups includes LMnt/⁷J symbols, a first bit in a pair of bits for a symbol group is applicable to the subset of Γ^β™7²Ι first PRBs from the set of prbs, _a second bit in the pair of bits for the symbol group is applicable to the subset of last L^bint/²J prbs from the set of ^Bint PRBs, a bit value of 0 indicates transmission to the UE in the corresponding symbol group and subset of PRBs, and a bit value of 1 indicates no transmission to the UE in the corresponding symbol group and subset of PRBs.”

In principle, two bitmaps are generated in the same way so Bitmap 1 (i.e., the value of INT-TF-unit is 0) is used as an example in figure 3 to understand how it works. Assuming PI periodicity is two slots, within these two slots, symbols reserved for UL are excluded from the bitmap. The number of DL symbols in two slots (Nint) is 20 and accordingly, 14-bit bitmap is generated from 14 symbol groups with “each of the first ^ϊντ -LMnt/¹⁴J·¹⁴ (=ρ) symbol groups includes ΓΜντ/¹⁴! (=2) symbols, each of the last ^14_λαιντ + L^Tnt/¹⁴-!· ¹⁴ symbol groups includes LMnt/¹⁴J (=1) symbols.

An issue associated with the current bitmap design is that when symbol #10 of slot #i is pre-empted, bit #5 of the bitmap will indicate “no transmission” (in other word preempted) and the relevant eMBB UEs will interpreted that both symbol #10 in slot #i and symbol #0 in slot #i+1 are both pre-empted which will result a false Negative Acknowledgement (NACK) report and then retransmission of the transport blocks (TB(s)) in slot #i+1, which still may be decodable in most cases.

A possible solution was proposed and is discussed with reference to figure 4. 14 bits are first allocated to each slot according to the ratio of the number of DL symbols in each slot over the number of total DL symbols, in this example, 8 bits = round (14*11/20) are allocated to slot #i, and 6 bits = round (14*9/20) are allocated to slot #i+1. Within each slot, symbols are grouped into symbol groups in a similar way as defined in the specs. Whist this solves the problem it is very complex to implement and as such is unlikely to be a preferred solution to the overriding problem.

The present invention is thus interested in seeking to solve at least some of the outstanding problems in this domain.

Summary

This Summary is provided to introduce a selection of concepts in a simplified form that are further described below in the Detailed Description. This Summary is not intended to identify key features or essential features of the claimed subject matter, nor is it intended to be used as an aid in determining the scope of the claimed subject matter.

According to a first aspect of the present invention there is provided a method for enabling a wireless communication device to access services provided by a Radio Access Network, the method comprising: generating bitmap bits for a pre-emption indication which is associated with a time period of at least two slots by; grouping one or more down link symbols into one or more symbol groups; splitting each symbol group that spans at least two slots into two sub-symbol groups; re-grouping the symbol groups with the sub-symbol groups; and generating a pre-emption indication bit for each symbol group.

Preferably, the symbol groups are regrouped by merging a sub-symbol group and a symbol group.

Preferably, merging the sub-symbol group and the symbol group is carried out via a logic OR of the corresponding pre-emption indication bits of the symbol group and the sub-symbol group.

Preferably, the symbol group and the sub-symbol group are from the same slot and adjacent to each other in time.

Preferably, the symbol groups are regrouped by replacing the symbol group that spans two or more slots with the corresponding two sub-symbol groups.

Preferably, the steps are repeated until there are no symbol groups that span two or more slots.

Preferably, the generated bitmap bits are mapped to the corresponding positions in the bitmap.

Preferably, the Radio Access Network is a New Radio/5G network.

According to a second aspect of the present invention there is provided a base station.

According to a third aspect of the present invention there is provided a User Equipment

Preferably, when a pre-emption indication bitmap is received, the UE will interpret the bits which correspond to a symbol group spanning two slots to determine transmission or no transmission.

According to a fourth aspect of the present invention there is provided a nontransitory computer readable medium having computer readable instructions stored thereon for execution by a processor to perform the method of another aspect of the present invention.

The non-transitory computer readable medium may comprise at least one from a group consisting of: a hard disk, a CD-ROM, an optical storage device, a magnetic storage device, a Read Only Memory, a Programmable Read Only Memory, an Erasable Programmable Read Only Memory, EPROM, an Electrically Erasable Programmable Read Only Memory and a Flash memory.

Brief description of the drawings

Further details, aspects and embodiments of the invention will be described, by way of example only, with reference to the drawings. Elements in the figures are illustrated for simplicity and clarity and have not necessarily been drawn to scale. Like reference numerals have been included in the respective drawings to ease understanding.

Figure 1 is a diagram showing the principles of pre-exemption indication, according to the prior art.

Figure 2 is a diagram showing example bit maps, according to the prior art.

Figure 3 is a diagram showing the principles of pre-exemption indication and bit mapping, according to the prior art.

Figure 4 is a diagram showing a prior pre-exemption indication, according to the prior art.

Figure 5 is a diagram showing a first method of a bitmap of a pre-emption indication, for according to an embodiment of the present invention.

Figure 6 is a diagram showing a second method of a bitmap of a pre-emption indication, for according to an embodiment of the present invention.

Detailed description of the preferred embodiments

Those skilled in the art will recognise and appreciate that the specifics of the examples described are merely illustrative of some embodiments and that the teachings set forth herein are applicable in a variety of alternative settings.

The present invention relates to a method of generating bitmap bits for pre-emption indication. The symbol group which spans two slots is further split into two subsymbol groups by the slot boundary, two pre-emption indication bits are generated for both sub-symbol groups and these two bits are used to do logic OR with two bits from adjacent symbol group respectively in the bitmap. The adjacent symbol group and sub-symbol group must be from the same slot.

Compared with previous proposals, this method is simpler, easy to understand and requires less changes to the formal standard specifications.

In this invention it is assumed that some resources in both the control region and the data region are used by a RS (Reference Signal) for channel estimation or measurement. The data region is scheduled by the control region and could be shared by several UEs. When a URLLC packet is received from an upper layer after the control region, it is not possible for the gNB to schedule a transmission from the control region, and the solution to support URLLC is to pre-empt the data transmission (typically to eMBB UEs) of one or more symbols in the time domain and a number of RBs in the frequency domain may be punctured and replaced with URLLC transmission(s).

Referring to figure 5, a symbol group (#5) is one which span two slots and is split into two sub-symbol groups by the slot boundary. In other words, sub-symbol group #5A including symbol #10 of slot #i and sub-symbol group #5B including symbol #0 of slot #i+1, 1 bit is generated for the each sub-symbol group and used to do logic OR with the bit of the adjacent symbol group of the same slot. This means that there is a logic OR between the bit for symbol group #4 and the bit for sub-symbol group #5A; or between the bit for symbol group #6 and the bit for sub-symbol group #5B. The generated bits are mapped to the corresponding positions in the bitmap. The “logic OR” effectively enlarges the symbol group, and the generated bits will be same by enlarging for example symbol group #4 by merging symbol #10 of the same slot and symbol group #6 by merging symbol #0 of the same slot.

At the UE side, when a PI bitmap is received, it will first interpret the bits which correspond to a symbol group spanning two slots. In this example, the UE will check bit #5 first, if it indicates “0” (i.e., transmission), in which case there will be no difference from the specified method in standards above. If the check indicates “1” (i.e., no transmission), the UE will further check bit #4 and bit #6 which can be used to understand where the pre-emption happened, i.e., slot #i only if bit #6 indicates “0”, slot #i+1 only if bit #4 indicates “0” or both slots if both bit #4 and bit #6 indicate

When symbol #10 of slot #i is pre-empted, bit #4 will indicate “no transmission” while bit #6 will indicate “transmission”. As a result, the UE can know that pre-emption happens in symbol #10 of slot #i but not in symbol #0 of slot #i+1.

This can be further described in the following manner. If the value of INT-TF-unit is

0, 14 bits of a field in DCI format 2_1 have a one-to-one mapping with 14 groups of the first ^nt ^_ΙΑιντΛ⁴_|·14 consecutive symbols from the set of symbols. Each of symbol groups includes Γ^λ\ν·ι/^Ι4Ί symbols, each of the symbol groups includes IAint/¹⁴J symbols, a bit value of 0 corresponding symbol group and a bit transmission to the UE in the corresponding symbol group, two slots, this symbol group is split into two sub-symbol groups by the slot boundary, last ¹⁴-^INT indicates transmission to the UE in the value of 1 indicates no

If a symbol group spans a transmission indication bit is generated for each sub-symbol group and used to do logic OR with the bit from the adjacent symbol group of the same slot.

If the value of INT-TF-unit is 1, 7 pairs of bits of a field in the DCI format 2_1 have a one-to-one mapping with 7 groups of consecutive symbols. Each of the first Ynt-LMnt/⁷J·⁷ symbol groups includes Γ^Λίχ-Ί·/⁷Ί symbols, each of the last ⁷ I'm· +L^A m/⁷J·⁷ symbol groups includes LNnt/⁷J symbols. A first bit in a pair of bits for a symbol group is applicable to the subset of Γ^β™7²1 first Physical Resource Blocks (PRBs) from the set of ^Λ[νι PRBs, a second bit in the pair of bits for the symbol group is applicable to the subset of last I-AntAJ prbs from the set of ^Λ[νιPRBs, a bit value of 0 indicates transmission to the UE in the corresponding symbol group and subset of PRBs, and a bit value of 1 indicates no transmission to the UE in the corresponding symbol group and subset of PRBs. If a symbol group spans two slots, this symbol group is split into two sub-symbol groups by the slot boundary, a pair of transmission indication bits are generated for each sub-symbol group and used to do logic OR with the pair of bits respectively from the adjacent symbol group of the same slot.

A UE is not required to monitor DCI format 2_1 in slot ^m ' ^in case no PDSCH is detected in any serving cell configured by higher layer parameter INT-cell-to-INT /y^slot · T within the last ^{symb INT} symbols prior to the first symbol of the control resource set in slot ^m ’ .

In an alternative embodiment, the present invention refers to figure 6. Assuming all symbols come from Tint slots so there are totally Tint -1 slot boundaries between two adjacent slots. First all symbols are grouped into 14-( Tint -1) symbol groups exactly as the specified method as show in figure 3 and a symbol group that spans two slots are further split into two symbol groups by the slot boundary and these two newly obtained symbol groups are used to replace the original symbol group. This step is repeated until there is no symbol group that spans two slots. For the same example as in figure 3, 20 symbols come from 2 slots, so there is only one slot boundary, after the 1^st step all symbols are grouped into 13 (=14-1) symbol groups as shown in figure

6. An identification is made that symbol group #5 spans two slots, it is further split into two symbol groups which are used to replace the original symbol group #5. Finally, 14 symbol groups are obtained with no one spans two slots. The 14 PI bits are allocated to each symbol group as specified by the standards.

It is possible that the number of symbol groups that span two slots is less than the number of slot boundaries. In that case, the final number of symbol groups, Λ/, may be less than 14 (or 7, according to configuration). The first Λ/ (or 2*Λ/, according to configuration) bits of a field in DCI format 2_1 have a one-to-one mapping with Λ/ symbol groups and not used bits from one 14-bit PI field can be reserved for future usage.

The above second method can be similarly described as follows. If the value of INTTF-unit is 0, /Vint symbols from Tint slots are first grouped into 14- Tint +1 symbol groups where each of the first Λ/ιντ - Αοογ(Λ/ιντ /(14- Tint +1)).( 14- Tint +1) symbol groups includes ceil(/ViNT /(14- Tint +1)) symbols, each of the last ( 14- Tint +1) - Λ/ιντ + Αοογ(Λ/ιντ /(14- Tint +1)).( 14- Tint +1) symbol groups includes Αοογ(Λ/ιντ /(14- Tint +1)) symbols and then each symbol group that spans two slots is further split into two symbol groups by the slot boundary and these two symbol groups are used to replace the original symbol group. 14 bits of a field in DCI format 2_1 have a one-toone mapping with 14 symbol groups, a bit value of 0 indicates transmission to the UE in the corresponding symbol group and a bit value of 1 indicates no transmission to the UE in the corresponding symbol group.

If the value of INT-TF-unit is 1, Λ/ιντ symbols from Tint slots are first grouped into 7Tint +1 symbol groups where each of the first Λ/ιντ - ίΙοοΓ(Λ/ΐΝτ /(7- Tint +1)).( 7- Tint +1) symbol groups includes ceil(/ViNT /(7- Tint +1)) symbols, each of the last ( 7- Tint +1) - Λ/ιντ + Αοογ(Λ/ιντ /(7- Tint +1)).( 7- Tint +1) symbol groups includes Αοογ(Λ/ιντ /(7- Tint +1)) symbols and then each symbol group that spans two slots is further split into two symbol groups by the slot boundary and these two symbol groups are used to replace the original symbol group. 7 pairs of bits of a field in the DCI format 2_1 have a one-to-one mapping with 7 symbol groups, a first bit in a pair of bits for a symbol group is applicable to the subset of Γ^β™7²Ι first PRBs from the set of ^Λ[νιPRBs, a second bit in the pair of bits for the symbol group is applicable to the subset of last L^bint/²J prbs from the set of ^Λ[νι PRBs, a bit value of 0 indicates transmission to the UE in the corresponding symbol group and subset of PRBs, and a bit value of 1 indicates no transmission to the UE in the corresponding symbol group and subset of PRBs.

A UE is not required to monitor DCI format 2_1 in slot ^m ' ^in case no Physical Downlink Shared Channel (PDSCH) is detected in any serving cell configured by y^SlQt . J, higher layer parameter INT-cell-to-INT within the last ^{symb INT} symbols prior to the first symbol of the control resource set in slot ^m'.

The above described embodiments relate to a bitmap of a pre-emption indication, but can equally apply to other situations, such as for example transmission indication and/or HARQ-ACK feedback.

Although not shown in detail any of the devices or apparatus that form part of the network may include at least a processor, a storage unit and a communications interface, wherein the processor unit, storage unit, and communications interface are configured to perform the method of any aspect of the present invention. Further options and choices are described below.

The signal processing functionality of the embodiments of the invention especially the gNB and the UE may be achieved using computing systems or architectures known to those who are skilled in the relevant art. Computing systems such as, a desktop, laptop or notebook computer, hand-held computing device (PDA, cell phone, palmtop, etc.), mainframe, server, client, or any other type of special or general purpose computing device as may be desirable or appropriate for a given application or environment can be used. The computing system can include one or more processors which can be implemented using a general or special-purpose processing engine such as, for example, a microprocessor, microcontroller or other control module.

The computing system can also include a main memory, such as random access memory (RAM) or other dynamic memory, for storing information and instructions to be executed by a processor. Such a main memory also may be used for storing temporary variables or other intermediate information during execution of instructions to be executed by the processor. The computing system may likewise include a read only memory (ROM) or other static storage device for storing static information and instructions for a processor.

The computing system may also include an information storage system which may include, for example, a media drive and a removable storage interface. The media drive may include a drive or other mechanism to support fixed or removable storage media, such as a hard disk drive, a floppy disk drive, a magnetic tape drive, an optical disk drive, a compact disc (CD) or digital video drive (DVD) read or write drive (R or RW), or other removable or fixed media drive. Storage media may include, for example, a hard disk, floppy disk, magnetic tape, optical disk, CD or DVD, or other fixed or removable medium that is read by and written to by media drive. The storage media may include a computer-readable storage medium having particular computer software or data stored therein.

In alternative embodiments, an information storage system may include other similar components for allowing computer programs or other instructions or data to be loaded into the computing system. Such components may include, for example, a removable storage unit and an interface , such as a program cartridge and cartridge interface, a removable memory (for example, a flash memory or other removable memory module) and memory slot, and other removable storage units and interfaces that allow software and data to be transferred from the removable storage unit to computing system.

The computing system can also include a communications interface. Such a communications interface can be used to allow software and data to be transferred between a computing system and external devices. Examples of communications interfaces can include a modem, a network interface (such as an Ethernet or other NIC card), a communications port (such as for example, a universal serial bus (USB) port), a PCMCIA slot and card, etc. Software and data transferred via a communications interface are in the form of signals which can be electronic, electromagnetic, and optical or other signals capable of being received by a communications interface medium.

In this document, the terms ‘computer program product’, ‘computer-readable medium’ and the like may be used generally to refer to tangible media such as, for example, a memory, storage device, or storage unit. These and other forms of computer-readable media may store one or more instructions for use by the processor comprising the computer system to cause the processor to perform specified operations. Such instructions, generally referred to as ‘computer program code’ (which may be grouped in the form of computer programs or other groupings), when executed, enable the computing system to perform functions of embodiments of the present invention. Note that the code may directly cause a processor to perform specified operations, be compiled to do so, and/or be combined with other 11 software, hardware, and/or firmware elements (e.g., libraries for performing standard functions) to do so.

The non-transitory computer readable medium may comprise at least one from a group consisting of: a hard disk, a CD-ROM, an optical storage device, a magnetic storage device, a Read Only Memory, a Programmable Read Only Memory, an Erasable Programmable Read Only Memory, EPROM, an Electrically Erasable Programmable Read Only Memory and a Flash memory

In an embodiment where the elements are implemented using software, the software may be stored in a computer-readable medium and loaded into computing system using, for example, removable storage drive. A control module (in this example, software instructions or executable computer program code), when executed by the processor in the computer system, causes a processor to perform the functions of the invention as described herein.

Furthermore, the inventive concept can be applied to any circuit for performing signal processing functionality within a network element. It is further envisaged that, for example, a semiconductor manufacturer may employ the inventive concept in a design of a stand-alone device, such as a microcontroller of a digital signal processor (DSP), or application-specific integrated circuit (ASIC) and/or any other sub-system element.

It will be appreciated that, for clarity purposes, the above description has described embodiments of the invention with reference to a single processing logic. However, the inventive concept may equally be implemented by way of a plurality of different functional units and processors to provide the signal processing functionality. Thus, references to specific functional units are only to be seen as references to suitable means for providing the described functionality, rather than indicative of a strict logical or physical structure or organisation.

Aspects of the invention may be implemented in any suitable form including hardware, software, firmware or any combination of these. The invention may optionally be implemented, at least partly, as computer software running on one or more data processors and/or digital signal processors or configurable module components such as FPGA devices. Thus, the elements and components of an embodiment of the invention may be physically, functionally and logically implemented in any suitable way. Indeed, the functionality may be implemented in a single unit, in a plurality of units or as part of other functional units.

Although the present invention has been described in connection with some embodiments, it is not intended to be limited to the specific form set forth herein. Rather, the scope of the present invention is limited only by the accompanying claims. Additionally, although a feature may appear to be described in connection with particular embodiments, one skilled in the art would recognize that various features of the described embodiments may be combined in accordance with the invention. In the claims, the term ‘comprising’ does not exclude the presence of other elements or steps.

Furthermore, although individually listed, a plurality of means, elements or method steps may be implemented by, for example, a single unit or processor. Additionally, although individual features may be included in different claims, these may possibly be advantageously combined, and the inclusion in different claims does not imply that a combination of features is not feasible and/or advantageous. Also, the inclusion of a feature in one category of claims does not imply a limitation to this category, but rather indicates that the feature is equally applicable to other claim categories, as appropriate.

Furthermore, the order of features in the claims does not imply any specific order in which the features must be performed and in particular the order of individual steps in a method claim does not imply that the steps must be performed in this order. Rather, the steps may be performed in any suitable order. In addition, singular references do not exclude a plurality. Thus, references to ‘a’, ‘an’, ‘first’, ‘second’, etc. do not preclude a plurality.

Although the present invention has been described in connection with some embodiments, it is not intended to be limited to the specific form set forth herein. Rather, the scope of the present invention is limited only by the accompanying claims. Additionally, although a feature may appear to be described in connection with particular embodiments, one skilled in the art would recognise that various features of the described embodiments may be combined in accordance with the invention. In the claims, the term ‘comprising’ or “including” does not exclude the presence of other elements.

Claims

A method for enabling a wireless communication device to access services provided by a Radio Access Network, the method comprising: generating bitmap bits for a pre-emption indication which is associated with a time period of at least two slots by;

a. grouping one or more down link symbols into one or more symbol groups;

b. splitting each symbol group that spans at least two slots into two sub-symbol groups;

c. re-grouping the symbol groups with the sub-symbol groups;

d. generating a pre-emption indication bit for each symbol group.

The method of claim 1 the symbol groups are regrouped by merging a subsymbol group and a symbol group.

The method of claim 2, wherein merging the sub-symbol group and the symbol group is carried out via a logic OR of the corresponding pre-emption indication bits of the symbol group and the sub-symbol group.

The method of and of claim 2 and claim 3, wherein the symbol group and the sub-symbol group are from the same slot and adjacent to each other in time.

The method of claim 1, wherein the symbol groups are regrouped by replacing the symbol group that spans two or more slots with the corresponding two sub-symbol groups.

The method of claim 5, wherein the steps of claim 5 are repeated until there are no symbol groups that span two or more slots.

The method of any preceding claims, wherein the generated bitmap bits are mapped to the corresponding positions in the bitmap.

The method of any one of the preceding claim wherein the Radio Access Network is a New Radio/5G network.

9. A user equipment, UE, apparatus comprising a processor, a storage unit and a communications interface, wherein the processor unit, storage unit, and communications interface are configured to perform the method as claimed in any one of claims 1 -8.

10. The apparatus of claim 9, wherein when a pre-emption indication bitmap is received, the UE will interpret the bits which correspond to a symbol group spanning two slots to determine transmission or no transmission.

11. The apparatus of claim 10, wherein the UE will check a first bit to determine if there has been transmission in which case the method of claims 1 to 8 are carried out; and if the check indicates no transmission, the UE checks adjacent slots to determine where pre-emption occurred.

12. A base station, BS, apparatus comprising a processor, a storage unit and a communications interface, wherein the processor unit, storage unit, and communications interface are configured to perform the method as claimed in any one of claims 1 -8.

13. A non-transitory computer readable medium having computer readable instructions stored thereon for execution by a processor to perform the method according to any of claims 1-8.