GB2565272A - A load dump - Google Patents

Abstract

The invention relates to a load dump, for example for connection to a dynamic brake resistor, and is especially useful when several motor drives and motors are operating together, interconnected in one system. The load dump includes an energy sink and a controller. The controller actuates a switch to divert current to the energy sink when a threshold is exceeded so as to dissipate excess energy in the sink. The load dump, at switch on, is at a voltage that is intermediate a voltage source and the load. The controller modulates the switch in dependence upon the quantity of energy to be dumped. The controller modulates the frequency of a waveform applied to the load so as to vary an intermediate voltage applied to the load at switch on. An advantage of this is that energy is dissipated at a very rapid rate independent of mains supply voltage.

Description

A Load Dump

Field

The present invention relates to a load dump, for example of the type used with a direct current (DC) link connection for sharing regenerated power between two or more electrically driven units. More particularly the invention relates to a load dump for connection to a dynamic braking resistor. For example, when several motor drives and motors are operating together, are interconnected in one system.

Background

There are increasing incentives to improve the efficiency of electric power conversion equipment. Conventional electric induction motors are said to consume approximately 70% of all electricity used in industry and about 45% of all the electricity used globally. Efforts are being made to improve the operation and efficiency of electrical motors.

Examining the DC link connection highlights other issues. For a conventional motor drive it is the peak value of the supply voltage that is usually of concern. However connect together two DC connections, via a mains rectifier and any input filtering that may be present, can cause severe problems if all power of the connected drives is routed through the input circuit of one of the drives as this leads to current and power overloading issues.

Prior Art

Conventional motor drives do not cope well when connected together (via a so-called DC link) or when connected with regeneration equipment. Consequently elevated voltages can occur during motor deceleration.

The design of a conventional motor drive tends to include a rectified front end and direct connection to a DC link capacitor (charged to the peak of the input voltage) with a 3 phase half bridge output circuit connected to this. In order to use the DC link it is standard practice to ignore any integral rectified front end and use an external front end that is capable of running a total load of all the drives and motors connected to it.

So far as handling motor deceleration is concerned, the usual technique is to operate the motor as a generator by altering the phasing of applied waveforms to the motor in the case of permanent magnet or switched or variable reluctance motors, and altering the applied waveform frequency in the case of induction motors. The consequence of this is that the voltages across the motor and motor drive increases beyond their normal operating voltages. As such motor winding insulation has to be able to cope with this additional voltage stress and the voltage rating of the drive components have to be rated higher than their normal operating voltage in order to cope with this.

Consequently this so-called overvoltage on regeneration, caused by the deliberate braking of the motor, requires careful regulation so as not to exceed motor or . component peak voltage limitations or cause triggering of any circuitry that is designed to shut down in case of an overvoltage for other reasons.

This is one reason why the DC link capacitor has to be large, as it can accommodate the voltage ripple that occurs during braking, and so that the instantaneous peak braking voltage does not drop below the input voltage, thus wasting input power in the braking resistor.

Another factor that systems had to protect against was to guard against input voltage peaking at excessively high voltages, risking over voltage issues (both for the motor and components) as well as risk triggering automatic over voltage protection systems.

At best it can be said that the DC link and sharing of regenerated energy between drives has been handled by using extra components and connections, but was not always a reliable solution to many of the problems encountered in regenerative braking systems. Furthermore a drive powered directly from a DC bus, for example in an aircraft, may have additional restrictions on current flowing back into a local ‘DC grid’. Such applications require a motor drive configured to have a one way current capability. There are also significant penalties attached to voltages present in such motor drives under all operating conditions. These are, for example, fail safe issues, voltage margin ratings, resistance to cosmic ray degradation and reduced ionisation voltages at elevated altitudes.

An aim of the invention is to provide a reliable motor braking system without high voltages being developed either across the motor or within the motor drive itself.

Summary of the invention

According to a first aspect of the invention there is provided a load dump for connection to a load includes: an energy sink and a controller the controller actuates a switch to divert current to the sink when a threshold is exceeded so as to dissipate excess energy in the sink characterised in that the load dump, at switch on, is intermediate a voltage source and the load.

Considering a single motor being driven by a single motor drive then the motor drive topology used allows for the braking resistor to be placed between the variable voltage stage and the 3 phase half bridge output stage. This allows the midpoint clamping of voltage to occur and it is this midpoint clamping of voltage within the drive which achieves a motor braking system at low voltages.

Under normal conditions an intermediate voltage is at a potential less than the input voltage. As the phase angle or frequency is altered, to effectively brake the motor, the motor becomes a generator and the voltage rises. The input variable voltage stage is controlled under these conditions so as not to allow this increased voltage to be passed back to the input of the variable voltage stage.

Advantageously the switching device that is connected to the motor braking resistor is switched into operation to dissipate this braking energy without excessive voltage build up occurring. This so-called dynamic regeneration has a significantly greater tolerance range than conventional braking techniques.

At its limit the midpoint voltage is typically between zero volts and a maximum peak rating that is permitted by lesser rated components and the motor insulation. A typical value is between 50 and 80% of the nominal maximum drive supply voltage. Comparing this with a conventional drive, where the clamping voltage is in the region of 115 to 120% and the overvoltage trip is around 125% of the nominal peak supply voltage so as to accommodate supply voltage tolerances.

Preferably the DC link voltage is operated around the midpoint between the variable voltage circuit and a 3 phase half bridge inverter which is required for the operational speed and the load of the motor.

Thus for correct operation of different motors, under different load conditions, the input voltages are different.

Preferred embodiments of the invention will now. be described with reference to the Figures in which: «

Brief Description of the Drawings

Figure 1 illustrates a block diagram of a quasi-sine resonant drive;

Figure 2 illustrates a more detailed circuitry of power components of the quasi-resonant drive of Figure 1;

Figure 3 illustrates a basic control concept of how a quasi-sine waveform to a motor is modified in relation to motor speed;

Figure 4a illustrates a typical motor phase voltage for an unmodified quasi-sine voltage applied to the motor;

Figure 4b illustrates an example of a typical motor current for an unmodified quasisine voltage applied to the motor;

Figure 5a illustrates a typical motor phase voltage for a modified quasi-sine voltage applied to the motor at low speed;

Figure 5b illustrates a typical motor current for a modified quasi-sine voltage applied to the motor at low speed;

Figure 6a illustrates a typical motor phase voltage for a modified quasi-sine voltage applied to the motor at high speed;

Figure 6b illustrates a typical motor current for a modified quasi-sine voltage applied to the motor at high speed;

Figure 7 shows one phase of a waveform applied to a motor running at high speed with retarded turn on of a complementary switch;

Figure 8 shows one phase of a waveform applied to a motor running at high speed with minor complementary switch turn on retardation;

Figure 9 shows one phase of waveform applied to a motor running at high speed with complementary switch turn at ideal instant;

Figure 10 shows one phase of a waveform applied to a motor running at high speed with premature complementary switch turn on;

Figure 11 shows a block diagram of a quasi-sine motor drive;

Figure 12A shows a starter circuit for the self-adjusting drive circuit;

Figure 12B shows spare components and inter-wiring information for the self-adjusting drive circuit;

Figure 12c shows a reset circuit for the self-adjusting drive circuit;

Figure 12d shows a threshold detector and logic circuit for the self-adjusting drive circuit;

Figure 12e shows an auxiliary gate driver output circuit (hard and soft) for the self-adjusting drive circuit;

Figure 12f shows a main gate driver output circuit (hard and soft) for the self-adjusting drive circuit;

Figure 13 is an overall view of a turn on circuit shown in Figures 12c and 12d;

Figure 14 shows a circuit diagram of a starter isolation circuit for the self-adjusting drive circuit;

Figure 15 shows an auxiliary gate driver output circuit in its low output state for the self-adjusting drive circuit;

Figure 16 is a circuit diagram of part of the self-adjusting drive circuit for enabling soft turn-on or hard turn-on of a driven switch;

Figure 17a shows an under-energised resonant waveform and block diagram of inputs required to enable oscillation.

Figure 17b is an overall diagrammatical representation showing a sequence of events that enables oscillation to occur;

Figures 18a to 18h show portions of a circuit diagram of a self-adjusting control circuit;

Figure 19 illustrates a sequence of events that enables oscillation to occur where output voltage is 50% or less of input voltage;

Figure 20 illustrates current excursions for operation of a control circuit that allows net current in or out of drive connections of a driven circuit;

Figure 21 is a table showing current and efficiency values for different output loads;

Figure 22a is an example of a circuit used for sensor-less current measurement;

Figure 22b shows a theoretical waveform output obtained with the circuit in Figure 22a;

Figure 22c shows a theoretical waveform output obtained with the circuit in Figure 22a;

Figure 23 shows an actual waveform output obtained over more than one cycle, with the circuit in Figure 22a;

Figure 24 shows an actual waveform output obtained within one cycle, with the circuit in Figure 22a;

Figure 25 shows an actual waveform output obtained for a single cycle, with the circuit in Figure 22a;

Figure 26a shows a diagram indicating optimum loss with respect to slip of induction motor;

Figure 26b shows a diagram indicating optimum loss with respect to advance angle for a permanent magnet (PM) or switched or variable reluctance (SVR) motor;

Figure 27 is a diagram showing drive configured as a simulated inductor;

Figure 28 is a diagrammatical overall view of a whole motor system including: a drive module, a power drive system; and a motor system;

Figure 101 is a circuit diagram of a synchronous Buck converter;

Figure 102 is signal timing diagram for the synchronous Buck converter in Figure 101;

Figure 103 is a circuit diagram of a first embodiment of a switching supply including a feedback controller;

Figure 104 is a circuit diagram of a second embodiment of a switching supply with capacitor (C1) and including a feedback controller;

Figure 105 is a circuit diagram of a second embodiment of a switching supply with z capacitor (C2) and including a feedback controller;

Figure 106 is a circuit diagram of another embodiment of the switching supply without a feedback processor and with capacitor (C2);

Figure 107 is a circuit diagram of the switching supply without the feedback processor to illustrate operation of components with power switch Q1 switched on;

Figure 108 is a circuit diagram of the switching supply without the feedback processor to illustrate operation of components with power switch Q2 switched on;

Figure 109 shows signal timing diagrams for the switching supply;

Figure 110 is signal timing diagram for the start-up phase;

Figure 111 shows an under-energised resonant waveform and block diagram of inputs required to enable oscillation.

Figure 201 illustrates a voltage waveform of a conventional transistor at switch on;

Figure 202 shows an idealised voltage waveform of a conventional transistor at switch on;

Figure 203 is a diagrammatical view of the idealised voltage waveform (shown in Figure 202) and depicts how a variation in capacitance affects waveform shape;

Figure 204 is a circuit showing a capacitor that varies its capacitance in dependence on a variation of an applied input voltage across the capacitance;

Figure 205 is a diagram indicating how nested components are used to smooth a waveform during operation of a device;

Figure 301 is a diagrammatical view of a conventional power switch drive circuit arrangement;

Figure 302 is a diagrammatical view of an example of a power switch input circuit with hard switching;

Figure 303 is a diagrammatical view of an example of a power switch input circuit controlling a resonant switching device;

Figure 304 is a diagrammatical view of an example of an energy recovery power switch drive circuit (with its mid-point switched);

Figure 305 is a diagrammatical view of an example of an energy recovery power switch drive circuit (with its mid-point switched, dual rail);

Figure 306 is a diagrammatical view of an example of an energy recovery power switch drive circuit (bridge switched);

Figure 307 is a timing diagram for the circuit in Figure 306;

Figure 308a to Figure 308f show diagrammatical views of alternative supply configurations for an external power supply;

Figure 309 shows in a diagrammatical form how parasitic capacitance (or Miller capacitance) is used to provide power an external circuit;

Figure 310 is a timing diagram of the circuit in Figure 309 and shows timing requirements for enabling scavenging from reverse transfer capacitance;

Figure 311 is a diagrammatical view illustrating an example of a negative supply current technique that is deployed in a scavenging circuit;

Figure 312 is an example of a circuit for achieving soft start-up;

Figures 313a to 313d are graphs showing current and voltage profiles against time for a power switch input current using an energy scavenging circuit;

Figure 401a shows an example of a conventional pulse width modulated (PWM) motor drive circuit; - .

Figure 401b shows an additional.switch to minimise input current surge in the motor drive circuit of Figure 401 a;

Figure 402a and 402b illustrates current waveforms that occur with the drive input circuit shown in Figure 401a;

Figure 403 shows an example of a PWM drive with line reactors;

Figure 404 shows an example of a current waveform from the PWM drive with line reactors shown in Figure 403;

Figure 405 shows in block diagram form, an example of a resonant voltage conversion circuit;

Figure 406 shows in block diagram form, an example of a resonant frequency conversion circuit;

Figure 407 shows in block diagram form, an example of a split function voltage control/frequency control quasi sine motor drive;

Figure 408 shows examples of graphs of power factor and crest control with split function drive for the circuit of Figure 407;

Figure 409 is an example of a three phase bi-directional (AC to DC or DC to AC) power supply;

Figure 410 shows an example of a functional diagram of a system including the motor drive of Figure 407 and the supply circuit of Figure 409;

Figure 411 is a graph showing ranges of power factor and crest control obtained using the system in Figure 410;

Figures 412a to 412e are functional diagrams showing alternative system capabilities, handling energy flows, operating in different modes;

Figure 413 is a circuit for limiting in-rush current at phase input; and

Figures 414a and 414b are examples of alternative circuits for limiting in-rush current between an active front end and a DC connection.

Figure 501 shows load dump position across intermediate voltage point.

Detailed Description of the Drawings

Figure 1 illustrates a block diagram of a quasi-sine resonant drive. Here it is shown that the output part of the circuit, consisting of the variable frequency stage, the slew rate capacitors and the motor itself forms a resonant circuit. In order for the system to operate correctly a self-adjusting turn on of the appropriate switch is required which occurs in this quasi sine form of output. Sensors may be shown connected to the motor giving an indication of speed. This can also give an indication of torque ripple if differentiated. Alternatively motor information can be calculated or derived from other measurable parameters. The variable voltage part of the circuit, shown at figure 1, is typically also a resonant voltage conversion topology. By using these two techniques together, extremely high efficiencies can be obtained.

Figure 2 illustrates a more detailed circuit showing power components of a quasi-resonant drive circuit. Figure 2 shows a three phase half bridge frequency determining circuit with slew rate capacitors C6, C7 and C8 arranged in parallel with their outputs connected to the motor. The voltage amplitude of the generated waveforms at the output is determined by the variable voltage part of the circuit.

In operation, at the appropriate time determined by control circuitry (shown in Figure 1), one of the output drive transistors, Q3, (shown in Figure 2), is turned off quickly. The current that was flowing prior to switch off of Q3 transfers to charging or discharging slew rate capacitors C6 and C8 until the voltage across switching device Q4 becomes reverse biased, at which instant diode D4 switches to conduct. Diode Q4 may be either intrinsic or external to the now reverse biased switching device.

Control circuitry (shown in Figure 1), now turns on switch Q4, (shown in Figure 2) and maintains it on until it is switched off quickly. This repeats the resonant switching process. This same resonant process occurs on both of the other phases of the output; or as many phases that are appropriate for the motor/generator that is being controlled (Figure 2).

The operation of output circuit, the variable frequency circuit part of Figure 2, is essentially determined by a controller (figure 1) which acts to force outputs to go off at a predetermined instant. Referring to Figure 2 switches Q3 to Q8 are switched on again by detecting the instant when the voltage across a switch is at zero potential, thereby ensuring no “shoot through” currents can occur. Therefore switch on occurs with no voltage potential across a switch. This ensures that there are no transient (voltage x current x dt) losses.

This type of operation, where the devices are turned off by the waveform frequency control mechanism (figure 1) and turned back on again by the natural resonance, ensures that all component values and tolerances are automatically taken into account in order to derive optimum input parameters to drive a system (motor), for every switching transition that occurs. Further, in one embodiment, this can be achieved without the need for a microprocessor type hardware or software burden.

The variable voltage element, shown in Figure 2 of the circuit, includes switches Q1 and Q2 and associated other components which are also operated in a resonant mode. As configured the variable Voltage circuit provides a voltage step down function from the supply across C1.

Figure 3 illustrates the basic control concept of how the quasi-sine waveform to the motor is modified in relation to motor speed. Figure 3 shows the speed of the motor going from stop to full speed. At low speeds, the amplitude of the quasi sine waveform is modulated by the voltage of the variable voltage stage which supplies the variable frequency stage. This voltage variation is timed so as to effectively cause a reduction in torque ripple. The voltage variation information is either supplied by calculation from voltages and currents within the control section of the motor drive as shown in Figure 1 and/or supplied by a shaft speed sensor (shown in Figure 1) which is used to determine rotational position and/or speed of the motor itself.

The aforementioned method of reduction of torque ripple also effectively reduces motor losses due to current harmonics inherent in the application of a quasi-sine waveform. This is because the instantaneous voltage modification of the voltage waveform has the effect of reducing the amplitude of harmonic currents as well as minimising the torque ripple. As the frequency applied to the motor increases, the effect of capacitors C6, C7 and C8, (Figure 2) is to minimise the slew rate, and also modify negative effects of the quasi-sine waveform by making the voltage waveform have a definite slew rate. This tends to drive the current waveform to be more sinusoidal.

There is also an opportunity to optimise the efficiency of an induction motor/drive combination by adjusting the applied voltage, frequency and slip of the motor to the sweet spot combination giving a given motor output power and speed for the least power supplied to the input of the drive. For an induction motor incorporating permanent magnets running at synchronous speed, as well as permanent magnet or switched/variable reluctance motors, the option of slip is not possible as the shaft frequency is the same as the drive frequency. However, it is possible to alter the advance angle with respect to the applied voltage. One way of achieving this is by altering the phase of the applied voltages relative to the motor rotor position with respect to stator poles, so that the conditions at which the so-called efficiency ‘sweet spot’ occurs can be selected.

These aforementioned are methods of achieving quasi-sine performance almost to ‘pure’ sine wave standard. They are not only suitable for induction motors but are also suitable for permanent magnet motors and switched/variable reluctance motors under certain conditions of use.

Figure 4a illustrates a typical motor phase voltage for an unmodified quasi-sine voltage applied to the motor. This is shown without the shunt slew rating capacitors fitted so the current waveform in Figure 4b is dictated entirely by the motor impedances. The voltage applied to the motor is also constant during each segment of the switching waveform.

Figure 4b illustrates a typical motor current for an unmodified quasi-sine voltage typical of Figure 4a applied to motor in figure 1. The relationship between a fundamental frequency and harmonics of the resultant current is dependent on many variables.

To minimise the current harmonics, so as to effectively minimise torque ripple and reduce resistive losses throughout the motor system as defined in Figure 28, several techniques can be used either on their own or concurrently. The voltage amplitude of the waveform itself can be modulated with a voltage waveform that effectively attempts to null the generation of harmonic currents.

Shunt slew rate capacitors C6, C7, C8 in figure 2 tend to modify transitions of the voltage waveform, thus the voltage waveform (from which the motor current waveform is derived) already has a reduced harmonic content and, in combination with the motor impedances at that speed and load, the resultant current harmonics are reduced further.

Also the harmonics of the motor current can be minimised if the control of the voltage of the waveform is made to simulate the characteristics of an inductor as shown for example in Figure 27. The net effect is to provide a low pass filter in combination with the slew rate capacitors and the motor impedances. Note that this effective voltage supply impedance capability is potentially fully adjustable to give the effect of a wattless resistance, a wattless inductance and/or a wattless capacitance. Wattless in this context implies that the circuitry is capable of simulating near perfect impedance. All these parameters may be varied dynamically and may exist concurrently. For example by measuring the actual power to the motor and/or the speed/change of speed of the motor, waveform modification can be performed continuously throughout each part of the applied waveform to minimise torque ripple and harmonic motor currents.

In a particularly preferred embodiment of the device its operation using pure sine waves would result in very efficient operation. However in practice, for an induction motor where there is asymmetry either in flux linkages (according to mechanical variations in relation to rotational position) or due to differences in a flux generating capability between each winding, there is the opportunity to compensate for these non-linear errors or other errors by waveform modification. Permanent magnet motors would be enhanced by this waveform modification capability and switched/variable reluctance motors even more so.

Figure 5a illustrates a typical motor phase voltage for a modified quasi-sine voltage applied to the motor at low speed. Here the voltage waveform is modified by varying the voltage of the variable voltage stage of the drive. This voltage modification has the effect that when combined with the actual impedance of the motor, at the given speed and load, then the current drawn by the motor has a more benign waveform.

I

This means that there are lower amplitude current harmonics in the motor. Voltage

I modification is relatively easy to achieve at low frequencies but becomes progressively more difficult to do at higher frequencies depending on the full power bandwidth of the variable voltage part of the drive and the maximum speed (frequency) of the drive itself.

Figure 5b illustrates a typical motor current for a modified quasi-sine voltage applied to the motor at low speed. Because the voltage applied to the motor in Figure 5a has a modified shape, the resultant motor current approximates to a sine wave or whatever shaped wave is required to obtain the desired motor current characteristics.

I

Figure 6a illustrates a typical motor phase voltage for a modified quasi-sine voltage applied to the motor at high speed. Here the effect of the slew rate capacitors can be used to slow the rate of voltage transition between the switching states of the frequency stage of the drive. In Figure 6a the voltage from the variable voltage stage is kept constant. In practice it is possible to combine the effects of slew rate limiting and instantaneous voltage modification to obtain an optimum result of derived motor current. Note that the effective impedance of the variable voltage stage is important because it is loaded by the motor impedance in parallel with the capacitive impedance of the shunt slew rate capacitors. This is where giving the variable voltage stage an inductive impedance characteristic is of additional benefit.

Figure 6b illustrates a typical motor current for a modified quasi-sine voltage applied to the motor at high speed. This shows how the actual motor current is starting to approach a wave shape with a very low harmonic content.

Figure 7 shows one phase of waveform applied to a motor running at relatively high speed with turn on using an opposite (complementary) switch for example Q4 in figure 2 where the turn on signal to Q4 is too slow. Figures 7 to 10 show the importance and effect of correct timing of the turn on point of the opposite switch in relation to the turn off of the first switch. The Figures also show the slew rate clearly and, because the motor speed is fast, the opposite transition occurs and the cycle repeats itself. This sequence of events, of the transition from one voltage state to the other, is identical at different voltages, currents and frequencies. The sequence is also the same sequence that occurs in the variable voltage part of the circuit shown in figure 2 as it operates to maintain a given output voltage. In Figure 7 in particular, the timing of switching of the opposite switch Q4 in figure 2 is shown as having been delayed from switch on at the right time.

Figures 7 to 10 show the effect of the resonance of the shunt capacitors. C6, C7, C8 in figure 2 during operation. Considering one of the 3 phase outputs to the motor in figure 2, when Q3 is turned off, the motor phase current is being maintained by a combination of the displacement current in C6 and C8 and the forward conduction of the parallel diode D4 across the opposite switch Q4. When this current is reversed and flows into the motor and if switch Q4 is not closed then resonance occurs in the opposite direction of the voltage applied to the motor. When the switch Q4 conducts either before D4 is in conduction or after the motor phase current has changed direction then there is a very rapid change of voltage across switch Q4 that occurs at the same time with a large current pulse (not shown) in switch Q4. This current pulse can reach destructive levels if switch turn on time is very short and the switch impedance is low enough.

Even if when this potentially destructive switching is not a problem, the switching devices experience significant repetitive transient switching losses that are proportional to: volts x current x switching time. There are therefore significant issues with sharp edge of such voltage transitions with cable resonances, EMC radiation and dV/dt stress applied to motor windings.

Figures 12a to 12f depict automatic turn on circuitry to achieve optimum turn on timing of its associated power switching device. The circuit is used in an example of an automatic self-adjusting motor drive system.

Figure 11 shows optimisation of the operation of controlling power in or out of a synchronous or non-synchronous motor/generator/alternator in order to achieve maximum overall efficiency (least losses) of the combination of the drive and motor/generator/alternator consistent with other desired parameters.

Figure 8 shows one phase of waveform applied to a motor running at high speed with turn on of opposite switch, for example Q4 in figure 2, very slightly too slow. As the opposite device Q4 is turned on closer to an optimum instant, undesirable voltage transitions become smaller (lower amplitude) with consequent smaller unwanted harmonics.

Figure 9 shows one phase of waveform applied to a motor running at high speed with turn on of opposite switch Q4 at an ideal instant. The waveform is the ideal voltage waveform. It is important that the turning on of the opposite device Q4 occurs at some point when the motor current is still flowing through the forward conduction of the diode connected across the opposite device. Ideally if the switching device is also capable of conducting current in the reverse direction (for example a field effect device) then it is advantageous to turn the switching device on as soon after the forward conduction of the diode has taken place. This is beneficial from a losses point of view if the value of (reverse current x device on resistance) is less than the voltage drop across the diode at this current level. Also switching in this manner allows for ease of optimising the On switching time of the opposite switch Q4.

Figure 10 shows one phase of waveform applied to a motor running at high speed with turn on of opposite switch Q4 very slightly too early before the resonance has forward biased D4. Here the opposite device has been switched on slightly in advance of the optimum turn on time. The resonance has not yet delivered the voltage to opposite device Q4 to drive it negative. When this occurs it gives rise to a high transient current in the opposite device Q4; causes excessive device switching losses: and is the source of problems associated with a fast edge, rather than the relatively smooth and slow edges associated with the resonant circuit operation. Note that the correct timing of the on switching event is not related directly to the frequency of the drive. The correct time to turn the switch on is at instant shown in Figure 9.

Figure 11 shows a block diagram of a quasi-sine motor drive. This shows the position of a self-adjusting switching device driver described as a self-triggering turn ‘on’ circuit. In Figure 11 there are 3 motor phases so there are 6 switching devices shown as 1 to 6. Each of these switches is controlled by 6 self-triggering turn on circuits which are more fully described with reference to the circuit in Figure 12. It is possible to drive switching devices 1 to 6 directly on and off by calculating switching criteria. However the self-triggering drive circuit described inherently compensates for turn on timing for each switching event and thereby automatically takes into account variables that would make a calculation based decision too complicated and therefore too time consuming to perform. These variables include: coil, motor, shunt/resonance capacitor, speed, load, voltage, current, temperature or any combination thereof.

Where the individual switching device is shown, there may in fact be several devices in parallel. Under these conditions it may be possible to have (within the switching device drive circuit) one part that detects the instant to switch on the devices and one or more driver circuits, for example one driver circuit for each switch in a parallel arrangement. Furthermore some of the drive circuits need to be floating while others have a common connection and so in some configurations it may be possible to employ circuit redundancy and so save components, cost and weight. Also an overall control microprocessor identified as ‘μ’ may optionally be referenced to the low voltage common terminal connecting switches 2, 4 and 6 of the power circuitry thus eliminating a significant amount of unnecessary signal isolating components.

Figure 12a to f shows a circuit diagram of a complete self-adjusting drive circuit. This design incorporates fundamental aspects of the turn on detection circuitry. It has one input (reset) that is basically a ‘must turn off and stay off’ command input. The circuit in Figure 12 has one input (drain/collector) that measures the voltage across the switching device to be controlled. It has an optional input (starter) that allows the switching device associated with it to be turned on slowly irrespective of any reset and drain/collector status. The circuit in Figure 12 has power supply pins which are nominally at 12 volts. It has one or more outputs to enable the switching devices to be switched on or off.

Figure 13 is an example of a reset circuit of the type that may be used in the circuit detailed in Figure 12. An important feature is the bi-stable element U1a. A reset on pin 4 under normal running conditions overrides any status of the switching device itself. The wiring and polarity of the connection to the reset opto-coupler U6 is failsafe. The voltage detecting circuit for the drain/collector ideally has a variable impedance. The advantage of this is for the detection circuit to present a very low impedance to the switching device drain/collector while diode D8 is reverse biased. This eliminates the possibility of high frequency noise leaking through the reverse biased diode and causing a false zero volt detection to occur. This low impedance can only be overcome when the diode is properly forward biased which can only occur when the voltage across the switching device is about zero volts. The circuit itself operates at low voltage except for the cathode of diode D8.

Figure 14 and Figure 16 show detailed views of the starter circuit used in Figure 12. The way these work is that in mode A, gate of associated switching transistor is turned on slowly so that a current spike (from charging or discharging shunt (C6, C7, C8 in figure 2 for example) or other resonant capacitors) does npt cause a significant current spike in the associated switching device of such an amplitude that it stresses or in a worst case destroys the associated switching device. Actual one shot energy loss here is not detrimental to the associated switching device. With motors, all three phases can be started separately at reduced voltage (and at the same output voltage). Different conditions apply for quasi sine and pure sine drives.

The starter circuit in Figure 14 is operable even if the voltage conditions across the device are considered inappropriate for normal operation of the turn on circuit as shown in Figure 13. Care must be taken to ensure that inappropriate operation of this circuit cannot occur.

Figures 15 and Figure 16 are detailed views of a power transistor drive circuit used in Figure 12. In this particular implementation, the circuitry in Figure 12 is capable of operating two independent power switching transistors. The circuits in Figures 15 and Figure 16 have the capability of either mode a: soft high, or mode b: hard high, operation. In both cases Figures 15 and Figure 16 have a hard/low capability.

In the circuit of Figure 15, the switch driver U5 has two outputs. One output is connected to pin 6 and pulls current out of the associated switching device to turn it off, thereby effectively driving the gate/base low. This output has a very low impedance and thus switches the associated switch very quickly, typically within around a few 10s of nanoseconds. High output from pin 7 is effectively off so no positive current can flow through R5 or R6.

For stability and control reasons it may be beneficial for the soft turn on, mode a, to only use one transistor in an output switch consisting of multiple parallel connected power devices. In this implementation both the circuits shown in Figure 15 and • ’ 1

Figure 16 are capable of doing this. A simple logical modification allows only the circuit in Figure 16 to have a soft turn on mode a.

Figure 16 in mode a operation is a detailed view of a power transistor drive circuit used in Figure 12 with particular attention being paid to its soft turn on capability when there is a high voltage present across the device being switched on. This part of the circuit is used for the initial starting phase of resonant operation. A problem it overcomes is how to start a resonance system that has no inherent mechanism to do this, as turn, on pulses are generated by the action of resonance itself once resonance has been established. Therefore simply enabling the transistors does not switch them on as none of the switches Q3 to Q8 (figure 2) are unlikely to be sitting in a suitable quiescent state with no voltage across them.

Under these conditions, the voltage of the switching transistor is unknown and so the zero voltage detecting circuit is inhibited. When the soft start input is enabled, mode a operation, there are two switches in a totem pole like output configuration. The other switching device in the totem pole is turned off so there is no possibility of a shoot through condition occurring. D4 inhibits a so-called ‘strong pull up’. This leaves R20 to limit the input current into the combined capacitance of both the input capacitance and the Miller of reverse transfer capacitance of the switching device as it turns on.

This slow turn on minimises the peak current that results from discharging the shunt capacitance across the switching device. In the sequence of operation of the startup, the system firstly applies off pulses to both top and bottom transistors of the totem pole like output configuration, selects a transistor to turn on and applies a switch on current to the soft start input which bypasses latch U1a in Figure 12d and applies a soft start pulse to the selected transistor. This soft on pulse bypasses the latch U1a in Figure 12d and ‘hard on’ driver so as to apply a soft pulse in order to avoid capacitive current from the shunt capacitor from destroying the selected transistor.

To start the three phase quasi-sine system it may be necessary to initialise the system and set it up for commutation by connecting one phase of the motor to the positive rail and the other two phases to the negative rail in order to inject current into the motor to enable resonant commutation to commence once the appropriate

Off’ pulses are initiated. For the quasi sine implementation, for minimum components it is convenient to turn on one of the pull up output transistors as they tend to be at a high voltage potential and so require isolated drive capability. The other two legs of the 3 phase half bridge are switched to the common negative rail and therefore do not require extra isolation components.

Figure 16 in mode b operation, is a detailed view of a power transistor drive circuit used in Figure 12 with particular attention being paid to its hard (fast) turn on capability when there is a negligible voltage present across the device being switched on. Here pull up transistor Q3 is enabled, D4 is reverse biased, and R11 is switched high so a strong turn on current to the switching device is provided via R17. This is the normal turn on mechanism that is enabled by the voltage across an appropriate switching device reaching zero volts. This soft or hard turn on option is required for both the circuitry involved in driving and controlling the variable voltage stage Q1 and Q2 in Figure 2 as well as the circuitry involved in driving and controlling the variable frequency stage Q3 to Q8 also depicted in Figure 2.

Figures 17a and 17b depicts diagrammatically a sequence of events that enables oscillation to occur. When the circuit is at rest, all switching devices have their resets enabled. To start the resonant circuit it is initially required to generate pulses of a suitable duration and apply them to the appropriate switching devices while other switching devices not required for the initialising process are still held in their reset conditions. This tends to charge up inductors in the circuit with sufficient current to enable a positive voltage rail to negative rail excursion to be able to occur with the associated resonant capacitors shunted across the switching devices. At this moment the opposite switches have to be enabled so that when the original switching devices are turned off, voltage detection circuitry operates correctly by detecting a very near zero state and turn the opposite switching device on. From this point circuits (shown for example in Figures 2, 12a-f and 18a and b) continue to resonate. The opportunity to allow for the turn on time of the drive circuit can be allowed for by triggering its inception at a voltage point in advance so allowing for delays.

The strategy adopted is always to be turning off the appropriate devices when a target current is achieved. This is decided by the control system shown in Figures 18a and b. The fact that devices are resonating gets it turned on again.

This method of commutation can be controlled by software. In such an embodiment there is little chance of ‘shoot through’ caused by uncertainty of device switching speeds and tolerances. Therefore this method of commutation eliminates all overlap and dead band timing issues that conventional switching systems suffer from.

Because of the way the resonant circuit (in Figure 17b) operates, any stray or inherent capacitance of the switching devices, motor, cable or inductors or any other components connected to node, in this case the junction of the common connection between Qt and Qb in Figure 17b that is being switched, is in parallel with an additional capacitance component required to make the circuit function correctly. A normal switching topology finds these stray and inherent capacitances .to be significantly detrimental to idealised operation and so introduces a significant power loss as well as circulating currents and EMC issues. 1

The turn off pulse to switching device driver circuit Figure 12c reset on PL5 has to be of a duration that is sufficient for an associated switching transistor connected to PL2 in Figure 12f to be switched off (cease conducting) and so that voltage across the collector/drain of this switching transistor to have risen sufficiently so that the voltage zero detection circuit connected to Q drain/collector on Figure 12c does not allow this switching transistor to be turned on again when turn off pulse (Figure 12c) is removed. The duration of this pulse is very small compared to the pulse repetition frequency of consecutive reset pulses applied to reset PL5 in Figure 12c so this is relatively straightforward to implement. Additional blanking gating or status feedback of latch U1a in Figure 12d could be reported back to control circuitry in Figure 18a and 18b and could be used here if necessary for ultra safety critical requirements such as aerospace.

Figure 17a shows an under energised resonant waveform and block diagram of inputs required to enable oscillation. It is a requirement for correct operation of the resonant circuit shown in Figure 17b that at all times there is sufficient stored energy in the Inductance shown in Figure 17b to ensure correct rail to rail commutation.

Occasional use of the soft input PL1 in Figure 12a could be used to provide the soft voltage change shown as Vadd in Figure 17a.

Figure 17b shows the power stage that is controlled by the control ^circuit Figure 18a-h.

Figure 18 shows a circuit diagram of self-adjusting voltage control circuit. This is used in the variable voltage section as shown in Figure 2. In order to derive the desired voltage, variable volts output, from the circuit in Figure 2, the control circuit (shown in Figures 18a-h) compares an output voltage with the required target voltage shown in Figure 18a. From this it ensures that off pulses, applied to the two switching devices Q1 and Q2, (shown in Figure 2) in order to maintain the output voltage at a desired level. A reset circuit as shown in Figures 12a to 12f for a resonating circuit (of the type shown in Figure 2) includes a control circuit operative to continually reset a latch in order to force the latch to an off state, whereby the condition of an output transistor, for example Q1 in figure 2, which is controlled by latch U1a in Figure 12d is switched off. Shortly after switch off of transistor Q1, the control circuit in Figure 12a tq 12f isolates the reset signal so that transistor Q1 is not triggered on again until the voltage across device Q1 reaches zero.

The circuit shown in Figure 18a and b is analogue but it could be converted partly or completely to a digital domain if required. The fundamental aspects of operation would be unchanged. In Figure 2, the variable voltage supply output is capable of operation from one voltage rail to the other and has a full power bandwidth of several kHz in this configuration. The full power bandwidth can be increased to many kHz. The resonant operation used has no inherent high frequency limitation. The high frequency range is limited primarily by turn off speed of the switching devices.

The switching devices have to turn off completely, within a few percent of their rise time, which is dictated by slew rate capacitance and operating current. Switch off times slower than this tend to waste power in the switching devices as they have to handle a repetitive switching loss where there is both voltage and current present for a period of time in the switching device. The resonant operation overcomes this under normal conditions, effectively by bypassing the current that is present as the device turns off, into becoming the charging or displacement current of the resonant shunt capacitors both deliberate and parasitic.

The circuit in Figure 18 a-h has several important features and functions. Controlling a resonant circuit so that it always resonates under all conditions of applied input power voltage, desired power output voltage and desired output current requires a radically different kind of control strategy. This is especially so if extremely high levels of conversion efficiency are to be achieved.

Loop gain stability under all conditions has been one of the most difficult issues to control: This is particularly so where a high full power bandwidth is required as near to critical damping as possible whilst still maintaining operation of a resonant circuit.

Assuming that the desired target voltage is presented to the circuit (in Figure 18a) as a 0 to 5 volt value with a midpoint of 2.5 volts. Knowing what the power input mean voltage value is, then the centre point of the voltage output (which is half the voltage input) can be set by adjusting an 8 bit attenuator pad U4 and U13. Any error between the attenuated output voltage and the target input voltage is developed as an error signal from the differential amplifier U10b as shown in Figure 18a. This error is developed across C6 after modification for loop gain and the response time by the variable gain elements controlled by U14 a, b and c. This error voltage is amplified by amplifier U7a which nominally sits at 2.5 volts if the input and attenuated output voltages are identical. Any deviation from this tends to cause the voltage at U7a to vary from 0 to 5.0 volts.

It is important to consider the idling state of variable voltage resonant circuit shown in figure 2 while it is running at a particular voltage output but where no net current is being drawn from its output terminal. The control circuit in figure 18a and b gives an output voltage that is exactly equivalent to the current flowing in the coils of the output inductor L2a,b in Figure 2. The circuit shown in Figure 18g is discussed in greater detail below and in combination with Figures 22a, b and c. Under these conditions the timing of the off pulses to the switching devices Q1 and Q2 is arranged so that the current in the inductor builds up to a certain positive level at which point outputs from circuit U3a and b in Figure 18h toggle and coil current drops to zero and then increases to an equal and opposite value to the current on the previous half cycle.

At the corresponding negative point the outputs of U3 a and b again toggle and the coil current in L2a,b in Figure 2 becomes less negative, crosses zero and increases to its original positive value again. This cycle then repeats. Any minor errors in currents and timing result in the variable volts output voltage drifting up or down and the voltage discrepancy causes the off times of each switching device Q1 and Q2 to be altered slightly. This tends to force the variable volts output voltage to its correct value. This continual oscillation and shuttling of current back and forth has sometimes been considered wasteful but the inherent losses are so small in this kind of resonant topology. Even with relatively small output powers, in relation to full power capability, the overall efficiency is extremely high. The offset circuit comprises two comparators U3a and U3b in Figure 18h which compare two adjustable voltages so that when power is required, a feedback controller U7a offsets the voltages by a predetermined amount in order to derive more/less power which is proportional to the offset.

Because of the unusual topology and the control strategy adopted the variable volts output circuit shown in Figure 2 operates in all four quadrants. In the circuit in Figures 18a and 18b, a careful analysis of the voltage outputs of U5a and b, U7a and b, and the networks on pins 2, 3, 5 and 6 on comparators U3a and U3b identify that the outputs 1 and 7 of U3 provide the correct off pulses when required.

Figure 19 depicts the sequence of events that enables oscillation to occur where output voltage is 50% or less of input voltage. A particular problem that has to be overcome in this resonant topology is that when current flows from the output, say the variable volts output in Figure 2 and the output voltage is at about 50% or less of Vmax, where Vmax is the voltage at A, there is required an injection of negative current (lrev) introduced into the resonant inductor L2a,b for resonant commutation to occur. Without this negative current, there is not enough energy to resonate shunt capacitors C4 and C5 so that the opposite switching device is reverse biased sufficiently to trigger the on pulse and ensure lossless commutation to continue.

This negative current lrev needs to be increased as the output voltage decreases., This negative current is derived from the specific operation of amplifier U*5a and depends on the output polarity of U7b and the network values at input of comparator U3. The configuration in Figure 18a and b also allows for normal operation where output voltage is 50% or higher and the current flows into the output terminal.

Figure 20 shows the coil L2a,b current excursions for operation of the control circuit Figure 18a and 18b for allowing net current in or out of variable voltage output connections in Figure 2. When the variable voltage circuit in Figure 2 is in its resonant idling mode, the current flowing into and out of resonant inductor L2a,b is equal and opposite, thus giving no net current flow either into or out of the variable volts output terminal. As current is drawn from the variable volts output terminal, the output voltage tends to fall and feedback circuit U10b, U7a and associated components acts to offset the switching points at turn off for comparators U3a and U3b. In turn these results in a higher value of positive current, and a lower value of negative current, flowing thus giving the desired net current outflow. Initially the control circuit in Figure 18a and 18b, attempts to maintain the same overall switching frequency, typically up to the point that the coil current doubles in the positive direction and drops to zero on the negative phase of the cycle.

If more current is required then the positive current increases to its maximum of, say 4 times peak idle current, while still maintaining its minimum current at zero. Consequently when more power is required it is necessary to reduce the input frequency of this system. This is helpful as the coil losses increase due to the higher currents but are reduced due to the lower frequency of operation.

As the circuit operates in all four quadrants, for full current in the negative direction the triangular wave is displaced below the zero Current line.

Figure 21 shows the current and efficiency calculations for the level of loading on an output. Figure 21 shows how this unusual effect of efficiency versus loading characteristics that this resonant topology achieves. This efficiency is aided by altering the internal current ramp offset and the frequency change under load to achieve the efficiency range.

Figure 22a is an example of a circuit used for sensor-less current measurement. It overcomes the use of conventional current measurement techniques which introduce series resistance and amplifiers. Alternatively the circuit in Figure 22a may be used to measure the passage of current by the use of a Hall effect principles. It can be difficult to get at the current to be measured itself because of voltage offsets or high dV/dt issues superimposed on the current As a consequence there can be significant power losses as well as measurement time delays which impinge on loop stability and limit the speed of operation of the circuitry.

The use of physical current measuring techniques can also cause problems in layout of the circuit and some of the sensors themselves are sensitive to stray electrical and magnetic fields. From this evolved the necessity to develop an improved current measuring technique.

The block diagram in Figure 22a illustrates where a voltage at the coil terminal A is significantly higher than the voltage at B, then the current into the capacitor C1 at B is closely approximated to (VoltsA/R1). From this it can be calculated that the change in coil current dl is equal to ((C1 x R1)/L) x dVc1 where Vc1 is the voltage change across C1.

So ignoring any offset issues, the voltage waveform across C1 is identical to the current waveform in the inductor L. However it is necessary to include a voltage clamp oh this waveform at every cycle, as an integrator has no absolute DC value.

The next stage in the sensor-less current measuring method is to determine the absolute values of the current and these can be determined at each time the coil current in L2a,b in Figure 2 resonates shunt capacitors C4 and C5 across switching devices Q1 and Q2. At this point the inductor current can be determined from the rate of change of voltage at the instant of commutation. (I inductor/C shunt) = dV/dt at point A.

Cshunt = Cstray + Cdevices + Cdeliberate

Passing the switching edge at point A in Figure 22a through differentiator C2, R2 and associated amplifier, the voltage across C2 and R2 gives a voltage at C which is proportional to the absolute current in inductor L2a,b at the point of switching off. This voltage is then used to restore the direct current (DC) current waveform at B by operating switch D at the zero cross of voltage A.

Figure 22b shows a theoretical waveform output obtained with the circuit in Figure 22a. Here inductor L2a,b has two different current values. The first is at negative going transition and is at a relatively low current. Therefore the slew rate of shunt capacitors C4 and C5 is relatively long. This lengthy slew rate translates to a relatively small voltage at C. The second transition occurs at a high inductor current and so the slew rate is relatively fast. This faster slew rate translates into a much narrower, but higher amplitude, pulse at C.

Figure 22c shows a theoretical waveform output obtained with the circuit in Figure 22a. Here the relationship between the voltage at B and the inductor L2a,b current related voltage C is DC restored at the clamping point D.

Figure 23 shows an actual waveform output obtained with the circuit in Figure 22a. It shows the voltage at C derived from the inductor current at the switching point superimposed on the voltage waveform at B.

Figure 24 shows an actual waveform output obtained with the circuit in Figure 22a. Figure 24 shows an expanded trace of the voltage waveform at B superimposed with inductor voltage at A as it crosses the zero volts axis. It can be seen that a DC restore clamping point, shown as two vertical lines in figure 24, derived from this zero point is the optimum point to perform DC restoring as it occurs at the peak of voltage waveform at B.

Figure 25 shows an actual waveform output obtained using the circuit in Figure 22a. Referring to Figure 23c this illustrates the desirability of performing DC restore at the inductor zero voltage point. Here a very non symmetrical inductor voltage A is used and the zero crossing point very closely identifies the peak of the current waveform at B.

Figures 26a and 26b show graphs resulting from calculations relating to losses and operational voltages in order to highlight the operation of seeking the sweet spot of optimum voltages, frequencies and phasing in order to derive a user specified shaft power from motor shown in Figure 1 for the least power drawn from the supply shown as input in Figure 1.

Figure 26a is a typical sweet spot graph for an induction motor where voltage, frequency and slip are plotted against total motor system loss for a given motor speed and load. Figure 26a shows clearly there is a particular combination of reduced volts, increased frequency and hence increased slip giving an optimisation opportunity. f

Figure 26b is a typical sweet spot graph for a permanent magnet motor or variable reluctance motor where voltage and advance angle are plotted against total motor system loss for a given motor speed and load. Figure 26b shows clearly there is a particular combination of reduced volts and increased advance angle so as to provide optimised input drive criteria.

Figure 27 shows a feedback approach for a drive using a simulated induictor, which in combination with the slew rate determining capacitors, forms a low pass filter so as to reduce harmonic currents and torque ripple. This kind of approach has advantages in not requiring any significant software or hardware burden to turn the quasi sine wave form into a near sinewave at all frequencies. The slew rate capacitors C4 and C5 in Figure 2 are chosen to provide an acceptable level of dV/dt which may not be enough to convert the quasi sine to a good sine wave approximation. This is where configuring the output impedance to appear like an inductor has a very important function as the actual inductance value can be made very large at low speeds and frequencies so that the low pass corner point of this LC combination is matched to the speed. This allows a relatively small capacitance to be used to provide correct quasi sine to sine modification over the whole operating speed and frequency range of the motor drive.

Figure 28 In order to understand how a motor drive system is considered, convention has arranged boundaries for the motor in context with the power connection to supply the power for it. Figure 28 shows the boundaries of a complete drive module (CDM), a power drive system (PDS) and a motor system comprising the motor itself and the attached mechanical load. This is included as a requirement of “CE Marking and Technical Standardisation Guidelines” for application to electrical power drive systems. The relevance here is that the overall efficiency of the techniques described is. to be read and understood in the context of the ‘motor system’ in this guide.

It is recognised that further development of an existing pulse width modulator (PWM) drive for motors, which already encounters and creates significant technical obstacles, results in even greater problems to be overcome in order to get it all to work correctly and these further developments may have other undesirable effects as well. In order to introduce the advantages of newer transistor materials, such as silicon carbide (SiC) and gallium nitride (GaN) switching speeds are increasing and associated switching edges are becoming sharper. This more rapid switching imposes greater constraints on design and requires drives to be more complex, mainly due to greater parasitic impedances; as well as subjecting the motor to even more aggressive waveforms than existing ones (that already cause considerable problems in motor design and installation) as a consequence of EMC.

By adopting a drive based on the fundamental principles outlined herein it is possible to revert to lower cost motor materials and also materials that give superior performance as they are only subjected to a fundamental frequency. Motor design is intended to ensure the motor runs on its fundamental frequency without having to

I compromise its design to cope with the issues of pulse width modulation.· Improved design also allows the use of lower quality (and therefore cheaper components) and switched or variable reluctance motors (which would allow for the fundamentally cheaper and physically toughest motor design that switched or variable reluctance motors offer compared to induction or permanent magnet motors) as existing torque ripple problems are overcome.

Figure 101 shows an example of a synchronous Buck converter which comprises a power switch illustrated by transistor Q1 and an auxiliary switch illustrated by transistor Q2. A DC supply provides a constant voltage Vin. Output stage consists of an inductor shown as coil L and an output capacitor C4 in series. A load impedance, Z|Oad, is connected in parallel with the output capacitor C4. The junction between Vin positive and the power switch Q1 is referred to herein as the top rail. The voltage of the top rail is Vin. Junction at the output to the auxiliary switch Q2 and the negative of Vin is referred to herein as the bottom rail. The voltage of the bottom rail is ground in many, but not all, applications.. For the purposes of the present embodiment the voltage of the bottom rail is zero.

Referring again to Figure 101, the mutual junction of switch Q1, switch Q2, and coil L is designated junction Q and the voltage at this junction is VQ. The junction of coil L and output capacitor C4 and load impedance Zload is designated the output junction. The voltage at this junction is designated Vout. The current passing from junction Q through coil L to the output junction is designated IL.

Connected in parallel across switches Q1 and Q2 are protection diodes D1 and D2. Protection diode D1 is in parallel with switch Q1 and protection diode D2 is in parallel with switch Q2. Protection diode D1 is arranged to block current if the voltage at the top rail is higher than the voltage at junction Q. Current only flows through diode D1 if the output voltage VQ is greater than Vin + D1 diode forward voltage drop across Q1.

Protection diode D2 is arranged to block current if the voltage at junction Q is higher than the voltage of the bottom rail. Current only flows through diode D2 if VQ is less than the bottom rail voltage less the D2 diode forward voltage drop voltage across Q2.

As illustrated in Figures 101 to 110 inclusive, the current IL flowing through the inductor L is considered positive when it flows from junction Q to the output junction. That is inductor current IL is said to be ‘forward’ when it is flowing from junction Q to the output junction. The current IL flowing through the inductor L is considered negative when it flows from the output junction Q to junction Q. That is inductor current IL is said to be ‘reversed’ when it is flowing from the output junction to junction Q. If the inductor current IL is said to be increasing positively, it means that its magnitude is increasing while it is flowing forward. If the inductor current IL is said to be “increasing negatively”, it means that its magnitude is increasing while it is flowing reversed.

Figure 102 shows a signal timing diagram for the synchronous Buck converter. It shows the way that voltages and currents change in this circuit over time. Using Figure 101 for reference, initially the voltage VQ and Vout are zero; the top rail voltage is Vin; the bottom rail voltage is zero; current IL is zero; and switches Q1 and Q2 are both off. In the first mode the power switch Q1 is turned on and the auxiliary switch Q2 is off. Then voltage VQ is equal to the top rail voltage Vin. If switch Q1 is a transistor, then voltage VQ is not exactly equal to Vin due to semiconductor effects. The current IL, through the inductor, rises. This rising current charges the output capacitor C4. The voltage Vout rises. Upon reaching an upper desired level for IL, power switch Q1 is turned off and auxiliary switch Q2 is turned on.

In the second mode the power switch Q1 is off and auxiliary switch Q2 is switched on. Voltage VQ is equal to the bottom rail voltage which is zero. If switch Q2 is a transistor, then voltage VQ is not exactly equal to zero due to semiconductor effects. The current IL through the inductor falls because the voltage Vout is higher than VQ. Although the current IL through the inductor is falling, it is still flowing into output capacitor C4 through output junction. Therefore the voltage on the capacitor C4 continues to rise initially. However if auxiliary switch Q2 is left on long enough, the current through the inductor L eventually drops to zero. Therefore the voltage at the output junction Vout keeps rising until the current through the inductor L reaches zero, at which instant voltage Vout stops rising.

If continuous operation of the circuit in Figure 101 is required, it is important that the coil current is not allowed to fall to zero, and under these conditions auxiliary transistor Q2 is turned off and Q1 is switched on again while current is flowing through the coil L, thereby enabling the cycle to repeat. Note that this means there are problems associated with this such as reverse recovery losses in D2 and switching losses in Q1 due to the simultaneous presence of voltage and current in Q1 as Q1 is switched.

If discontinuous operation of the circuit in Figure 101 is required, the coil current is allowed to fall to zero; at which point in time the auxiliary transistor Q2 is turned off and transistor Q1 is turned on thereby enabling the process to repeat. The first mode is then repeated with the power switch Q1 on and auxiliary switch Q2 switched off.

By continuous repeated operation of the first and second mode of operation the output voltage Vout rises to the desired voltage and is maintained around the desired voltage by the controller in Figure 101 adjusting the drive timing to transistors Q1 and Q2 on and off thereby effectively adjusting the inductor current value IL.

An example of a prior art drive circuit is described by Panda, Pattnaik, and Mohapatra in the International Journal of Power Management Electronics, Volume 2008, Article ID 862510, in the article entitled “A Novel Soft-Switching Synchronous Buck Converter for Portable Applications”. Such prior art switching converters suffered from: auxiliary switches being turned off whilst they conducted current. This resulted in switching losses and EMI. The power switch that is described with reference to Figure 101 and is one of the preferred embodiments described herein. - >

It operates with higher peak current stress and more circulating current, as well as active and passive circuits that are more complex than existing power circuits.

Although developments in switch mode supplies have resulted in designs of considerable ingenuity, they normally suffered from increased complexity, cost or exotic components.

Figure 103 shows an embodiment of the switching supply in addition to the elements and connections of the synchronous Buck controller. The circuit also comprises a first switch capacitor C1 connected in parallel across the terminals of the first switch Q1; a second switch capacitor C2 connected in parallel across the terminals of the second switch Q2; and a rail capacitor C3 connected between the top rail and the bottom rail.

The switching supply also comprises a feedback controller. The feedback controller receives inputs. The switching supply sends a control output, that is based on the values and timing of the inputs, which turns the switch Q1 on or off or and sends a control output signal which turns the switch Q2 on or off. Figure 104 shows a second embodiment of the switching supply. The second embodiment is similar to the first embodiment except that there is no second switch capacitor C2 present. Likewise in the circuit in Figure 104, there is no first capacitor C2 connected in parallel across the bottom rail and junction Q.

Figure 105 shows a third embodiment of the switching supply. The third embodiment is also similar to the first embodiment except that there is no first switch capacitor C1 present. Likewise there is no first capacitor C1 connected in parallel across the top rail and junction Q.

The operation of the switching supply according to the invention is described below. The circuitry has to operate in several different modes. There are a defined set of principles that need to be followed to start the circuit correctly. There is also a second set of principles, that are required to operate the circuit at steady state with an output voltage less than half the input voltage. Furthermore there is a third set of principles to operate the circuit at steady state with an output voltage greater than half the input voltage. These principles are related to the overall current flow in L.

For the sake of simplicity, the circuit shown in Figure 105 is discussed in detail below. Capacitors C1 and C2 both are effectively in parallel one with another and are connected across either switching transistor Q1 and Q2. They are represented as two capacitances so that there is effectively a capacitor connected to each switching device Q1 and Q2 so as to minimize the region and physical area of circulating currents during device switching events. For minimum electromagnetic interference issues the path taken and consequent area of this path are important. Assuming the value of C2 is the parallel value of C1 and C2 in Figure 103.

The startup of circuit in Figure 105 is now described with reference to Figure 110 for the first cycle of startup. Initially the voltage VQ and Vout are zero; the top rail voltage is Vin; the bottom rail voltage is zero, and current IL is zero. Switches Q1 and Q2 are off. The voltage across C2, Which is effectively in parallel to both Q1 and Q2, is also zero. In the first mode, mode 1, the power switch Q1 is turned on and the auxiliary switch Q2 is switched off.

In a preferred first mode the power switch Q1 is turned on ‘softly’. That is power switch Q1 is partially opened to let current slowly seep through at a rate of typically a small fraction of the rated current of Q1. Note that consideration of the second breakdown characteristics of Q1 need to be allowed for during this slow turn on transition. If Q1 is a transistor, turning it on softly means that its resistance is gradually decreased. The advantage of the soft start is low in-rush currents and less stress on switch Q1. It can be seen that Q1 has to provide a charging current for C2 to charge from zero volts to the top rail voltage. ,A fast turn on here may lead to a potentially destructive high peak current in switch Q1 and this circuit arrangement prevents this from occurring. Note that the transient heat dissipation that occurs in this relatively inefficient switching action is not an issue as it ideally only occurs once with subsequent switching transitions being in a much more efficient mode.

Referring again to Figure 103, after the power switch Q1 is turned on, capacitor C2 is charged to the top rail voltage Vin almost immediately and voltage VQ is equal to the top rail voltage Vin. If switch Q1 is a transistor, then voltage VQ may be just slightly less than Vin due to semiconductor effects.

The circuit in Figure 103 is now described in its second mode of operation.

Current IL through the inductor rises. This rising current charges the output capacitor C4. The voltage Vout rises. The near step increase in voltage at VQ at the start of the first mode causes the output voltage Vout to rise.

The shape of the wave forms over time, including voltage VQ, voltage Vout, and current IL are shown in the signal timing diagram of Figure 110. Upon the first to occur of either of the following events power switch Q1 is turned off. The first event is the current through the inductor rises to a predetermined maximum, ILmax. The second event is an upper desired level for Vout is reached.

The maximum current in inductor L (ILmax) is limited by magnetic saturation, overheating of the inductor L, exceeding the peak current rating of Q1 or any other limiting parameter chosen. The second mode ends and the third mode begins when power switch Q1 is turned off. Preferably Q1 is turned off quickly. When this occurs Q1 is turned off and the resistance of switch Q1 increases quickly. At this instant inductor current IL, that was flowing through Q1, is transferred to flow through capacitor C2.

In the third mode the power switch Q1 is off and the auxiliary switch Q2 is also off.

At the beginning of the third mode the inductor current IL continues to flow which draws down the voltage VQ by draining charge off capacitor C2. Voltage VQ decreases according the relation between voltage and a resonating series circuit of the inductor L and capacitors C2 and C4. An advantage of drawing charge from capacitor C2 is that there is no resistive power loss. If this function were to be provided by the turn off of Q1, in the usual manner, the simultaneous application of voltage across and current through the switching device would result in a substantial power loss only limited by the speed of the switching event itself.

When the voltage VQ decreases to· a relatively small level, below the bottom rail voltage, the protection diode D2 in switch Q2 is suddenly forward biased. This small relatively level is about 0.7 V and depends on the particular specification of diode D2. Therefore the voltage at VQ.drops to a minimum voltage of about -0.7 V and can fall no further. Detection of this predetermined minimum level of voltage VQ is a criterion for turning Q2 on.

Referring again to Figure 105 and 110 upon detection of the predetermined minimum level of voltage VQ, auxiliary switch Q2 is turned on quickly. This is now the beginning of the fourth mode. Advantageously by turning auxiliary switch Q2 on at this time the voltage drop across switch Q2 is minimal because the current that was flowing through D2 can now be routed through Q2 if its impedance to this current is less than that presented by diode D2.

The action of the circuitry at the end of mode 2 and during mode 3 has therefore effected a lossless transition of VQ from the top rail voltage to the bottom rail voltage with a waveform shape dictated by the resonant values of C2, L2 and C4, and by the rail voltage and coil current at the moment of switching. Switching losses are substantially reduced and are limited to losses in the equivalent series resistances (ESR) of the components involved. Radio frequency interference is considerably reduced due to the lower dV/dt of the switching edge. All stray and parasitic capacitances in the circuit are additive to the effect of the shunt capacitance C2. This means that any stray capacitance that is effectively connected to the node at Vq such as the capacitance of Q1 in its off state for example.

The third mode ends and the fourth mode begins when auxiliary switch Q2 is turned on. At this time Q1 is off and Q2 is on.

Because the voltage VQ is about zero volts, which is less than the output voltage, Vout, the current IL through the inductor L continues to decrease. Depending on the output voltage Vout, which is the voltage on capacitor Cout, switch Q2 stays on until either of the two criteria a) or b) below occurs. a) The point in time where the inductor current IL reaches zero and when the output voltage Vout is in the range of being greater than or equal to half the top rail voltage Vin.

In practice, to allow for resonance losses, Vout needs to be slightly greater than half the top rail voltage Vin to allow a successful rail to rail resonance to occur. b) When the output voltage Vout is in the range of less than half the top rail voltage Vin, to just slightly greater than half the top rail voltage Vin, the switching behaviour of Q2 is modified. In order to route enough energy into C2 so as to commutate VQ from the bottom rail to the top rail, it is necessary to inject energy into the inductor L to achieve this.

By allowing switch Q2 to stay on past the point in time where IL drops to zero, the inductor current IL reverses and increases to a predetermined negative value. The stored energy in the inductor begins to increase again. This is the extra energy required to commutate C2 from the bottom rail to the top rail.

At the beginning of the next mode, which is the fifth mode, switch Q2 is turned off quickly. The advantage of applying criterion a or b to the turn off time of Q2 is that some of the additional energy stored in the inductor L is available to be transferred to capacitor C2 when switch Q2 is turned off. In many cases this additional energy is sufficient to eventually raise the voltage VQ to the value of the top rail voltage a certain amount of time after switch Q2 is turned off.

By this additional delay in turning off switch Q2, a stronger reversal of current is achieved through the inductor than if switch Q2 is turned off immediately upon the current in the inductor reaching zero. This stronger reversal of current through the inductor L causes additional energy to be stored in the inductor.

Advantageously some of the current that flows through the inductor when the value of the current is negative may be drawn from not just capacitor C4 but also a load connected to the output.

The fourth mode ends and the fifth mode begins when switch Q2 is turned off. During mode five switch Q1 is off and switch Q2 is off.

Still referring to Figure 110 waveform is that of a damped sinusoid according to an equation corresponding to the series combination of the inductor L and the capacitor C4 and capacitor C2. Preferably the intrinsic resistance of these components is low enough for a waveform to be that of an under damped sinusoid.

Due the nature of the series LC circuit resonance, the current flowing through the inductor L continues to increase negatively, at the beginning of mode 5 because the voltage VQ is about zero volts, which is less than the output voltage Vout. This adds to the energy already stored in inductor L at the beginning of mode 5 by the negative pre-charge current already flowing.

Since the current IL flowing through the inductor L is zero or negative at the start of mode four depending on whether criteria a) or b) is used to switch off Q2 at the end of mode 4, the current IL flowing through the inductor is negative immediately after mode 5 starts. This negative “reversed” current IL charges capacitor C2 and raises the voltage VQ.

If criterion a) in mode 4 triggers switch Q2off, the voltage VQ eventually rises to the top rail voltage Vin plus an additional small voltage that is enough to forward bias protection power diode D1. This additional small voltage is about 0.7 V above the top rail voltage depending on the particular diode D1. Therefore the voltage VQ is limited to rising to the top rail voltage plus this additional small voltage.

This aspect of the invention therefore detects when protection power diode D1 becomes forward biased. By turning Q1 on fast at this time there is a very low switching loss since voltage drop across power switch Q1 is less than the power diode D1 voltage drop. This is the beginning of mode 2 again.

If criterion b) in, mode 4 triggers switch Q2 off, the voltage VQ may or may not eventually rise to the top rail voltage Vin in addition to the additional small voltage which is sufficient to forward bias protection power diode D1.

If voltage VQ does reach the top rail voltage in addition to the forward voltage drop of the protection power diode D1, then the circuit in Figure 111 detects the peak of the resonance of the voltage QV and when this occurs it turns switch Q1 softly on at this instant.

It is possible that the voltage VQ peaks below the top rail voltage Vin, depending on such factors as: the value of L, the value of C2 and C4, the amount of delay imposed by criterion b), the energy present in the inductor L when Q2 is switched off, the relative values of Vout and the top rail voltage, and the current drawn by any load connected to the output. The circuit in Figure 111 detects if voltage VQ peaks below the top rail voltage plus the forward voltage drop of power protection diode D1 and turns switch Q1 on at this time. Advantageously this is when the voltage drop across switch Q1 is minimized and therefore the switching power loss (and RFI) are also minimized at this time.

Preferably to further minimize any switching loss and RFI, if the voltage VQ peaks below the top rail voltage in addition to the forward voltage drop of diode D1, switch Q1 is turned on “softly”. In this event, the resistance across switch Q1 is reduced gradually. When the voltage VQ rises to the top rail voltage, switch Q1 is then fully turned on fast.

If there is voltage undershoot of the rail target voltage, the circuit (shown in Figure 111) can vary the pre-charge current in the inductor L by increasing the current slightly so as to ensure sufficient energy is available from the inductor to achieve correct commutation for the next cycle. This active monitoring of the resonant voltage at mode 5 allows for the control circuitry in Figure 111 to adjust the reverse or pre-charge current in the inductor L to be just enough or in excess of what is ' required to ensure rail to rail commutation.

At the end of the fifth mode switch Q1 is on and Q2 is off. Then the cycling process is repeated beginning with the second mode.

This is shown in Figure 109. Referring to Figure 105, the total value of capacitance that is required, in parallel with the switching devices Q1 and Q2, may be either one capacitor across one of the switches such as C1 or C2; or two smaller capacitors C1 and C2 each connected across each switching device Q1 and Q2. The desired capacitance value is the sum of these two smaller capacitors.

The input capacitor C3 connecting the top rail to the bottom rail, has a much larger value than the switch shunt capacitor(s) C1 or C2. The choice of how to split the capacitors and capacitance values made in order to minimize circulating RFI currents due to the transfer of inductor current from the transistors Q1, Q2 to the capacitors C1 and C2 and back again during each switching transient. A single capacitor C1 could be connected across Q1 as the highest diverted current normally occurs here.

The switching supply circuit illustrated herein by schematics and timing diagrams Figures 103 - 111, and described in the “summary of the invention”, the “brief description of the figures”, the “description of preferred embodiments of the invention”, and the “abstract” is referred to in the claims as the “modified switching supply circuit described herein”.

Further embodiments of the switching supply circuit that operate according to the abovementioned sequential method of control will be apparent to those skilled in the art. For example capacitor C1, illustrated in Figure 104 as a single element, could be replaced by two or more capacitors in series or parallel, inductor L could be replaced by two or more inductors in series or parallel and so forth.

Figure 106 shows another embodiment of the switching supply with the feedback controller and the connections to the feedback controller removed. Figure 106 shows a simplified overview of circuit components and connections without feedback controller and its connections.

Figure 107 is a circuit diagram of an embodiment of the switching supply with the feedback processor removed to illustrate its operating components with the power switch on.

Figure 108 is a circuit diagram of the switching supply with the feedback processor removed to illustrate the components with the auxiliary switch on. Each embodiment has its advantages in terms of optimizing current flows between the switching devices and associated capacitors depending on voltage transfer ratios and net current flow directions. These have implications on stray inductance, circuitry and component resistance and electromagnetic interference (EMI), both from a perspective of EMI generation and EMI susceptibility.

Figure 109 is a signal timing diagram for the switching supply when the system is running.

Figure 110 is a signal timing diagram for the switching supply when the system is initiating its startup phase.

Figure 111 shows an under-energized resonant waveform and block diagram of inputs required to enable oscillation.

Figure 201 shows a typical switching waveform and the background behind each transition. a) the first transition.

If a circuit, as shown in Figure 101 for example, is running in continuous mode operation, when the device Q1 turns on there is a very high likelihood that another device D2 is exhibiting reverse recovery and that there is a significant current build up at the instant of switching, leading on to the initial transition, which may lead to significant RFI being generated. Figure 201 shows a typical waveform of the circuit in figure 101. b) The slope.

The slope of the waveform here represents, in a normal switching system, a point where significant currents are flowing at the same time as there are voltages across the switching device Q1. (This is especially so in the case when a switching device is turning off while supplying a significant current to inductive load). In the turn on situation of Q1 there may be significant currents flowing in parasitic inductances and capacitances as well. These circulating currents are prolific generators of RFI. The sharpness of the slope at Vq in Figure 101 indicates how many harmonics which may be present and what level of harmonics are required to create this waveform.

There is an optimisation problem at this instant as a sharp edge in the slope indicates that there will be less losses in the switching device, but at the same time tends to create more harmonics and RFI problems. c) The final transition. A sudden arrival of ‘full switch on’ condition of the switching device Q1 in itself therefore creates another problem. Because of stray inductances associated with the switching device, as well as associated components, there is a tendency for voltages to overshoot. This introduces risks of instability (or even catastrophic) operation as a result of. so-called ‘ground bounce’. t · d) rail softness.

This is a measure of how much supply rails are decoupled one from another. If there is a change in current draw from the supply, then the voltage rail connected to Vin experiences transient voltage changes. If there is a certain amount of inductance in series with these components, then this transient voltage change creates a voltage ring that continues for a certain amount of time while decaying depending on the degree of damping. Conversely, depending on the circuitry, a low inductance supply may be problematical if sudden currents occur, such as shoot through, due to incorrect timing of switching devices or as switching devices overcome reverse recovery of an associated component.

Both these disturbances are potential sources of RFI. The continual development and use of switching devices, capable of ever faster transitions, is exacerbating this problem. Having understood the sources of RFI creation by switching devices there is a solution that can be adopted so as to minimise these deleterious effects. The waveforms and problems discussed herein are manifested in a circuit running in continuous operation or hard switching. They can be reduced to a certain extent by operating in a discontinuous mode.

This discontinuous mode normally significantly reduces RFI generation at point Vq in Figure 101 due to reduced reverse recovery transients but it can lead to uncertainty of circuit operation.

Another way in which RFI can be reduced is to adopt a resonant mode of operation. Unfortunately virtually every topology of resonant operation requires components to have a voltage rating to almost twice the highest voltage that is expected to be handled by the circuit or device. This demand places a burden on the cost of the product or a loss in efficiency, due to higher voltage drops of higher voltage rated components.

The resonant topology described below with reference to Figure 103 and Figure 405, has the advantage of only requiring a voltage rating for components being used at the highest voltage present when the circuit is operating; not twice that voltage which was previously the case.

Figure 202 shows an idealised switching waveform. In order to improve RFI performance further the incorporation of non-linear devices (where the capacitance i of the device varies according to the potential difference across the device itself) is shown so as to modify the switching wave shape at its corners a and c on the switching waveform as shown in Figure 202. Modification of wave shape still allows for a fast transition, b, from one switching state to the other and by judicious choice of component values, it is possible to reduce total RFI emission, while still achieving quicker switching times.

Referring to switching waveforms shown in Figure 201 which are associated with a resonant topology,· see Figure 103 and Figure 405, there is an opportunity to modify the wave shape of the switching transient. Firstly slope b) can be adjusted using the total shunt capacitance across the appropriate switching device. Secondly the smoothness or ‘roundness’ of initial transition a) and final transition c), can be adjusted using components that have a ‘variable capacitance related to their voltage’ characteristic.

Figure 203 shows a circuit of key components responsible for an idealised switching waveform. Figure 204 illustrates a typical switching circuit with a mixture of linear and non-linear capacitive components. Figure 203 illustrates a composite of linear action of C1 and C2 in conjunction with the non-linear action of CV1 and CV2.

Figure 204 is a schematic of components, used to generate this shape of waveform and assumes idealised components. The following is an explanation of its operation. For the sake of understanding, the components CV1 and CV2 are shown as a varactor or varicap device. In fact there are many materials that exhibit this ‘variable capacitance related to applied voltage’ phenomenon. Assume switching device Q2 is switched on. At the moment the voltage across CV2 is nominally zero, and therefore CV2 exhibits maximum capacitance value across Q2. Examination of the other components shows that there is also ‘in shunt’ with the capacitance of CV2, the combined value of C2, C1 and the much reduced value of CV1. CV1 has a high reverse voltage so therefore exhibits a very low capacitance.

Referring to Figure 204 and assuming for convenience that there is a current flowing out of L1 into the node B. At this point consider that Q2 is now turned off very quickly. Current now flows from being a real current passing through Q2 to a displacement current that charges combined capacitance of CV2 and C2, + (via C4) C1 and CV1. Voltage then rises at point B. Initially the total capacitance is high so the rate of voltage change given by:

Idt = CV where C is (CV1 + C1+ CV2 + C2), I is coil current L1, dt is the time for a change in voltage at node B and V is the change in voltage over that time interval.

This rate of change of voltage initially is low. However as the voltage across Q2 rises (and consequently the voltage across CV2 rises), the effect of the capacitance of CV2 diminishes and the voltage rises quicker and quicker. Voltage rate rise reaches a maximum rate at about the midpoint between the two supply rails A and D. At this point capacitance of CV1 and CV2 are similar. However as the voltage across Q2 continues to rise the voltage across CV1 reduces. This causes the capacitance of CV1 to increase so that the inductive current from L1 now causes the voltage at node B to increase more slowly. At the point that the voltage at B reaches the top rail A, the capacitance of CV1 is now at a maximum. This increase in total capacitance again produces the desired rounded shape to the transition point of the switching waveform. This sequence is repeated when the top switch Q1 is turned off and the voltage at node B goes in the reverse direction.

Circulating current loops and RFI generation

Figure 205 shows an example of a physical representation of Q2 with the other components that are in parallel with C2 included. If the idealised switching device Q2 is considered, it would represent the shortest path length and therefore the minimum stray inductance, if the component represented by CV2 could be fitted within the switching device package as a co-package along with the component represented by D2.

It can be seen that as the current shifts from Q2 to the non-linear capacitive element CV2 that the electric field caused by this redirection of current flow is minimised the closer the non-linear capacitive element is to the idealised switch. This effect confines the highest RFI producing function to the shortest path thus reducing its transmitting area.

The package inductances Ls2 and Ls3 and the wiring inductances Ls4a and Ls4b, as well as Ls5a and Ls5b, mean that the current takes a little time to build up in C2. However, the value of CV2 at zero to very low voltage is ideally chosen to be higher than C2 which gives this current time to establish. The extra inductors Ls6 and Ls7 mean that the shunt capacitance of CV1 and C1 are effective a short time interval later. This progressive current build up, and the fact that each network has a lower resonant frequency, result in a controlled spectrum of RFI.

The highest frequencies have, because of this variable capacitance method of rounding of the waveform edges, a smaller amount of energy than they would have if they were sharper transitions and this minimises radiation. As the circuit becomes larger in surface area, the potential emission frequencies are lower so the radiation issues are minimised despite the transmission area having increased.

Figure 301 is a block diagram of a conventional power switch gate drive, circuit, Q1 and Q2, connected to a power switching device Q3. Figure 301 explains the general principles of conventional gate drive circuit operation. The interface and logic elements of a gate drive circuit (not shown) receives an ‘on’ or ‘off command and this then switches Q1 and Q2 so that for ‘on’, Q1 is on and Q2 is off. Conversely, when the command is for ‘off then it switches Q1 off and switches Q2 on. Assuming the power switch device Q3 is off, Q2 is on and potential Ve is nominally at Vb. Vf is at some significantly higher potential.

At the ‘on’ command, Q2 switches off and Q1 switches on. Input current flows from C1 via R1 and charges input capacitance Ciss until switch Q3 starts to conduct. At this point there is an output voltage transient change of Q3. Vf, via the reverse transfer capacitance Crss, now absorbs nearly all of the available input current. When the output voltage Vf is nominally equal to Vb, the voltage Ve can continue to rise in order to turn Q3 fully on.

It can be deduced from the operation of Q1 and R1, and the voltages Va and Ve, that the current profile of this method of operation is not ideal. At the instant that the switch device Q3 is turning on, the input current is already reduced. At the point that the switch device Q3 is now turned on, the voltage at Ve is rising but at a slower and slower rate as the current to charge Ciss is rapidly tailing off. This can lead to unnecessary switching device resistive losses. The operation of the drive circuit transistor Q1 in Figure 301. requires a considerable amount of available energy to drive the input capacitances of the switch device Q3 in order to change the voltage Ve.

At the ‘off command, Q2 and R2 take the energy from input terminal of Q3. All of this energy is wasted in Q2 and R2. Again the current profile of the input current is not ideal for efficient switching of Q3 especially as the effect of Crss occurs at a relatively low value of Ve where the available current from Q2 and R2 is significantly reduced.

Figure 302 shows a circuit power switch input current flowing with the power switch hard switching. This is the normal operation of a power switch device Q3. The operation of the circuit is as described in Figure 301. However there is another issue to be considered.

Referring to Figure 302, the circuit includes an inductor L1 and a diode D10. Current IL flows from the inductor L1 into D10. As Q3 is turned on this current has to be diverted into Q3 away from flowing into D10. Two problems occur here. The first is that the full current from L1 flows through Q3, around the same time as the full voltage Vf is present. Secondly there is a so-called reverse recovery characteristic of D10 to overcome. This excess current requirement can cause RFI issues as the reverse recovery current is overcome and the voltage Vf suddenly starts to fall.

During ‘hard switching’ conditions of Q3 the effects of the input capacitance Ciss and the reverse transfer capacitance Crss both occur around the same time. The input current is therefore a combination of currents generated by these two parasitic capacitances. This is the same for both turn on and turn off of Q3.

Figure 303 shows an example of a power switch input current that flows with power switch resonant switching. The current input current flows are different for the power switch device Q3 when it is operated in a resonant mode. The input capacitance charging and discharging currents occur at a different time to the currents assdciated with the reverse transfer capacitance Crss in conjunction with the voltage change across Q3.

When Q3 is in its turned off condition, Q2 is on and R2 is connected across the input of Q3 and the voltage Ve is Vb. At the same time inductor L1 and diode D10 are also connected in the circuit (shown in Figure 303) and a resonant capacitor C5 is positioned across Q3. Assuming current IL flows from inductor L1 into D10. Assuming the voltage Ve is Vb (Q2 on) and that after a period of time that the current IL ceases flowing into D10, then a resonant circuit (comprising L1 and C5) now causes voltage Vf, across Q3 and C5, to reduce until the voltage Vf is equal to Vb. The current, caused by the reverse transfer capacitance, while voltage Vf is reducing to Vb, flows through Q2 and R2 and so maintains voltage at Ve nominally at the level of Vb. Power switch Q3 is now turned on by a current flowing via Q1 and R1. It is evident that the current flowing out of the junction of R1 and R2 now only has to charge the input capacitance Ciss of Q3. This therefore reduces the requirement of power from the external power supply (not shown) to C1.

At the point in time where it is required to turn off switch Q3, to facilitate lossless commutation of the resonant circuit, it is important that Q3 is switched off as quickly as possible. Under these conditions the current, from both the discharging of the input capacitance Ciss and the dynamic effects of the current through the reverse transfer capacitance Crss, are routed to the ground terminal of Q3 at Vb via R2. The stored capacitive energy in both cases is wasted in R2.

Figure 304 shows an example of an energy recovery power switch drive circuit arrangement (mid-point switched). Figure 304 shows the basic concept of an energy recovery circuit that both assists with the speed with which the current can be injected or taken out of the junction of R1 and R2 and the input connected to the switching device Q3, while at the same time significantly minimising the external power required into C1. Circuit 304 achieves this by efficiently delivering energy from the midpoint Vg on C6 of the circuit in Figure 304 into the input capacitances of Q3 when the device Q3 is turned on; and returns this energy from the input capacitances of Q3 when the device Q3 is turned off.

The circuit, shown in Figure 304 reduces the overall net power requirement of the gate drive by approximately a factor of 10. There are still some losses that cannot . be overcome, for example track resistances and effective internal input terminal resistances due to the physical design of the power switch and the resistance of the inductor L2 and S1. Other than these losses the circuit is almost lossless.

Referring to Figure 304 and assuming Q3 is switched off, and the midpoint circuit output voltage and voltage across C6, is Vg which is approximately % Va. Q2 is then switched on, thereby setting Ve to Vd. Gate control signal command then switches from 'off to ‘on’. Switch Q2 is now turned off and S1 is closed. The current Igate in Figure 313d increases through L2 into the input of the power switch Q3. The voltage Ve transits from Vb to close to Va, as L2 resonates with the input capacitance of Q3. At the appropriate instant of resonance, where the voltage Ve comes closest to Va, S1 is turned off and Q1 is turned on. This maintains the voltage Ve at Va. Any shortfall in voltage at the point of Q1 switching on, is made up by extracting energy from C1.

The turn off of Q3 is done in a similar manner. The timing of the control signals to Q1, Q2 and S1 are handled by the section called gate timing control circuitry which is shown in detail in Figure 307 .

Figure 305 shows an example Of an energy recovery power switch drive circuit arrangement (mid-point switched, dual rail). Figure 305 shows the basic concept of an energy recovery circuit that both assists with the speed with which the current can be injected into or drawn from the input to the switching device Q3, while at the same time significantly minimising the external power requirements of C1. This is achieved by efficiently transferring positively charged energy according to capacitor energy storage equation (CV2)/2, in the input capacitances of Q3 when the device is in its ‘on’ state, into an equivalent negatively charged energy in the input capacitances of Q3 when it is in its ‘off state. This also, in the same manner, shuttles energy from negative to positive when turning Q3 back ‘on’ again.

This circuit (Figure 305) can reduce the overall net power requirement of the gate drive by approximately a factor of 10. There are still some losses that cannot be overcome namely track resistances, effective internal input terminal resistances due to the physical design of the power switch and the resistance of inductor L2 and S1.

The timing of the control signals to Q1, Q2 and S1 are handled by the section called gate timing control circuitry.

Assuming Q3 is switched off and voltage Vi is approximately 12 volts and voltage Vj is approximately -12 volts, both relative to Vb. Q2 is on thus setting Ve and Vd to

Vj. Gate control signal command then switches from ‘off to ‘on’. Q2 is now turned off and S1 is closed. Current that flows into the input terminal of Q3 now builds up through L2 and the voltage Ve goes from Vj to close to Vi as L2 resonates with the input capacitance of Q3. At the appropriate instant of resonance, where the voltage Ve comes closest to Vi, S1 is turned off and Q1 is turned on. This maintains the voltage Ve at Vi. Any shortfall in voltage at the point of Q1 switching on, is made up by taking energy from C1. The turn off of Q3 is done in a similar manner.

Figure 306 shows an example of an energy recovery power switch drive circuit arrangement (bridge switched). Figure 306 shows the basic concept of a different .embodiment of the gate charge recovery mechanism. The circuit in Figure 306 works in a similar manner to the circuit in Figure 304 however the midpoint circuit C6 and S1 in Figure 304 is replaced by intelligent timing commands, controlled by a microprocessor for example, (not shown) applied to the switching points of Q1, Q2, Q4 and Q5, The timing commands and their order are shown in the Table in Figure 307.

Assuming Q3 is off and the voltage Va is approximately 12 volts and voltage Vh is Ve, Q2 is switched on which acts to set Ve to Vb. Gate control signal command then switches from Off to ‘on’. Q2 is now turned off and Q4 is turned on. The current now builds up through L2 into the input of the power switch Q3 and the voltage Ve goes from Vb to close to Va as L2 resonates with the input capacitance of Q3.

At an intermediate point in the resonance, Q4 is turned off and the inductive current flowing through L2, flows via D5. At the appropriate instant of resonance, where the voltage Ve comes closest to Va, Q1 is turned on. This maintains the voltage Ve at Va. Any shortfall in voltage at the point of Q1 switching on is made up by taking energy from C1. Any excess energy in L2 at this point is returned to Cl.

The turn off of Q3 is done in a similar manner.

The determination of intermediate points in the circuit operation (the ‘going on’ intermediate voltage is likely to be different to the ‘going off intermediate voltage) may be adjustable by the timing circuit as too low a threshold results in there not being enough energy stored in the inductor to ensure rail to rail change on the input to Q3. However too much energy stored in the inductor ensures rail to rail change on the input to Q3 with any surplus being returned back to C1.

Figure 307 is a Table showing switch timing of an energy recovery power switch drive circuit arrangement (bridge switched).

Figure 308 shows an example of external power supply sources. There are many ways to supply the power necessary to operate the switching device Q3 and its associated circuitry. ' l

The problem which has to be overcome is that often switching device Q3 is floating at a different potential to the source of supply, or in an even worse case requires a separate voltage while the switching device itself is toggling between high voltages and at high frequency and with extremely sharp transitions. This places demands on how power is supplied.

Power is Supplied either by direct connection to a source, for example a transformer, or via a diode recharging circuit in the case of the top (high level) switching devices in half bridge design for example. Power can also be provided by a resistive ‘bleed’ from a high voltage rail, although this is often wasteful.

Alternatively power can be provided from a high voltage circuit associated with the switching device itself, for example via a capacitive coupler as in Figures 308a, 308b and 308c. This power supply option has the advantage that there is more power available, the faster the circuit (in Figure 301 for example) operates. This ensures that as power demand increases with faster switching speeds, more power is available.

These types of power supply waste power in the switching devices (when operated in continuous mode) because of the extra capacitive loading. However in resonant operation of the switching devices, Figure 303 for example, then because this extra capacitance is in parallel with (and can even be part of the resonant capacitance), the desired resonant capacitance no extra losses are introduced.

Figure 309 illustrates how power switch parasitic capacitance or reverse transfer capacitance (Miller capacitance) is used to provide power refresh to the power switch drive circuit of Figure 309.

When a power switching device, of the type Q3 shown in Figure 301, operates in a circuit where the instant of turning it on or off coincides with the voltage across the device that is charging, then the charging and discharging of its input capacitance and the reverse transfer capacitance, occur more or less simultaneously. Therefore practically it is difficult to separate one from the other. Under resonant operation of the switching device Q3 (figure 303) however this becomes reasonably straightforward to implement and enables use of energy in the reverse transfer / capacitance to supply power to the input drive circuit.

Considering the operation of the switching device Q3, in Figure 303, operating at resonance, it is important that when Q3 is required to be in its off state, the input Ve of Q3 is held nominally at zero voltage with respect to the source terminal. If Q3 experiences an increasing voltage transition on its drain, the reverse transfer capacitance drives voltage Ve positive on the input terminal at the junction of R1 and R2. In order to maintain switching device Q3 off, voltage Ve has to be clamped to the source terminal so that Ve does not rise and start to cause Q3 to go into conduction. This is done by ensuring Q2 is on when there is an increasing voltage at Vf. However when drain of Q3 experiences a decreasing voltage transition, (Vf reducing), on the drain this actually causes the input voltage Ve to the switching device Q3 to become more negative. Under this condition it is not necessary to clamp Ve to the source as it is already less than zero. This voltage change Ve of the input of the switching device Q3 represents a net gain of energy drawn from the reverse transfer capacitance which can then be stored in the input capacitance Ciss.

This net gain of energy occurs at every cycle of the switching device. Net energy gains occur in the same order as losses incurred using the resonant gate switching techniques as described above with reference to Figures 303 and 309. If extra power is required for the driver circuitry (for example power to drive an opto-coupler for condition or status monitoring) then additional capacitance can be connected between the drain and the input terminal of the switching device Q3, as this supplements the reverse transfer capacitance effect. This extra capacitance between drain and input terminals of Q3 does not introduce extra switching losses in Q3 because it adds to the resonance capacitance C5 whereas in a non-resonant circuit the charging and discharging currents for this extra capacitance would cause extra resistive losses in the switching transients of Q3.

Figure 309 shows one way the reverse transfer energy can be stored. Here if there is a reducing voltage on the drain of Q3, current flows from input Ve of switching device Q3 through switch Q2 into the reverse capacitance energy storage circuit shown in Figure 309. If however the input to the switching device Q3 is higher than a few hundred millivolts positive, with respect to the source of Q3, then the reverse capacitance energy storage circuit sets the input of Q3 to zero if Q3 is supposed to be in its off state. The desired state of Q3 in this instance is that while the switching device Q3 is in its off state, the input is never allowed to go positive with respect to its source. However, if any negative current appears at the input, it is stored in the reverse capacitance energy storage circuit, shown in Figure 309. A beneficial situation occurs in that the action of the operation of the gate drive circuit (Figure 309), itself performing its primary function as a drive, transfers this energy via Q1 to C1. This energy is then available to both compensate for the losses occurring during switching as well as to provide a certain amount of power to operate circuitry connected to C1. Extra capacitance between the drain and input of Q3 as shown in Figure 311 provides additional power if required. If only a small amount of additional net output power (beyond break-even) is required, there is no need for an extra store for this power as it can be stored temporarily in the actual input capacitance Ciss of the switching device Q3 itself. This is shown in Figure 311 in more detail.

Figure 310 is a table showing timing requirements for scavenging power from a reverse transfer capacitor shown in Figure 309. Here the operation of the switching elements Q1 and Q2 for routing the reverse transfer capacitance energy is described. Both the midpoint circuit and the reverse capacitance energy storage circuits need to be controlled and work together and so are organised by gate timing control circuitry as shown in figure 304. When the voltage is rising across Q3, the displacement current due to the reverse transfer capacitance Crss, is routed to the source of Q3 so that the input voltage is kept nominally at zero. When the voltage across Q3 falls, the current due to the reverse transfer capacitance is routed via the reverse capacitance energy store, shown in Figure 309.

Figure 311 is a circuit illustrating negative current supply techniques for a scavenging circuit. In order for the input to Q3 to be negative in relation to the source of Q3, modifications are required to the circuit shown in Figure 303 in order to prevent the desired negative current and hence negative voltage created by this on the input terminal of Q3 being inadvertently wasted by being shorted to the source of Q3 by undesirable current paths such as substrate diodes (not shown) or reverse conduction or breakdown of other switching components such as Q2 in the driving circuit. Referring to Figure 306 a current is provided that operates switch Q3 by suitable switching of Q1, Q2, Q4 and Q5. However devices Q5, D5, Q2 and D2 do not support negative operation. If Q5, D5, Q2 and D2 are replaced with a composite of active components, for example Q2 in Figure 311, allied with additional (not shown) switching circuits (if appropriate) then correct operation of the scavenging of the reverse transfer capacitance power occurs.

In Figure 311 a cascade transistor (as an example) is shown as Q2 which allows two way current control, voltage blocking of the full on gate input voltage and a measure of negative voltage isolation sufficient for an amount in excess of breakeven of reverse transfer charge, to be stored as a negative voltage in the switching device Q3 input capacitance Ciss.

Figure 312 shows a circuit depicting a soft start capability. In order to be able to start the resonant operation of Q3 in a resonant power control application it is necessary to be able to slowly turn on Q3 once at the beginning of the cycle, see Figure 110. A fast turn on, with a significant voltage across the drain-source junction of Q3, is problematical because a large current flows from the resonant shunt capacitance C5, in position as shown in Figure 303, into the switch Q3. This large current can cause damage to Q3. The solution to this is to turn Q3 on in a current limited mode. One way this is done is by introducing a limited current, set by R3, (with Q1 off) into the input terminal of Q3 and using the reverse transfer capacitance Crss to limit the dV/dt across the shunt capacitor C5.

Figure 313a to 313d show,graphs of current profile against time for power switch input current using energy recovery techniques described above.

Figure 401a shows an example, of a pulse width modulated (PWM) motor drive. Figure 401a illustrates the basic building blocks of a conventional PWM motor drive. This became feasible around the mid 1980s with the development of the insulated gate bipolar transistor (IGBT). This was accepted for motor control as it allowed «. motors to consume less power than direct on line connection, under most conditions. However the IGBT suffered from a number of negative effects which have been accepted and worked around rather than designed out of drive circuits. The motor drive in its latest form has reached a point where it is not easy to improve it in any way. However it is a simple, reliable drive that is used in great quantities worldwide.

Figure 401b illustrates an example of a conventional PWM drive as depicted in Figure 401a but with a series resistor R1 and a shunt relay contact S1 to minimise the turn on surge current that would be drawn from the supply by the DC filter capacitors as shown in figure 401a. Figure 402 illustrates some of the problems suffered by PWM drives, specifically relating to their input current issues., Figure 402b shows the current waveform of one of the inputs, R, in Figure 401a. Amongst the many technical problems the conventional PWM drive causes, the connection between the drive and the utility connection has suffered from several issues. These are: 1) Turn on or connection current surge; 2) Phase current wave shape; 3) Power factor; 4) Crest factor; 5) Neutral harmonics; 6) Brown out or black out reconnection and ride through; 7) Rectifier voltage drop and consequent power loss; 8) Reduced DC output does not allow for generation of sufficiently high voltages to get full power from motor; and 9) There is no opportunity to regenerate from a motor under braking.

Figure 403 shows an example of a conventional PWM drive with line reactors. This shows the incorporation of a line reactor to smooth the input current in each of the input connections between the utility connection L1, L2 and L3 and the motor drive, comprising AC to DC converter, filter and DC to AC inverter, which provides a measure of improvement to the current wave shape. This can be seen in Figure 404 and this can be compared to the current waveform in Figure 402b.

The introduction of line reactors effectively means that the 'double humped’ peak current waveform, as shown in figure 402b, is spread out in time, as shown in Figure 404. This has the effect of reducing the peak current as the period over which the current is drawn from the supply is increased.

However, the introduction of additional circuit inductance, ‘the line reactor’, introduces a phase delay in the current relation to the applied voltage. Also the extra component, the line reactor, introduces extra losses, takes up physical space and adds to the cost of a motor drive system. 1) Phase current wave shape; 2) Power factor; 3) Crest; 4) Neutral harmonics; 5) Extra physical component; 6) Extra cost over basic PWM drive cost; 7) Extra resistance and therefore system power losses; and 8) Inductive lag effects.

Figure 404 shows another example of a conventional PWM drive with line reactors which reduce but does not eliminate input current wave-shape problems.

Figure 405 shows an example of a high efficiency resonant converter device configured for voltage conversion.

The diagrams in Figure 405 show a high efficiency resonant converter circuit and its main power conversion components. In addition to components shown it is understood that an electronic drive circuit, as well as control and auxiliary power components are required to enable the circuit to operate. Due to the symmetrical nature of the circuit (Figure 405) it can be operated in all four quadrants if required. It is appreciated that the circuit can operate in four main modes.

Step down

Here the DC voltage is applied between D and C where D is the more positive terminal. The operation of the switching devices, depicted as NPN transistors, in a resonant mode allows a voltage between zero and the voltage applied at D to be available at terminal A.

Step up

Here the DC voltage is applied between A and C, where A is the more positive terminal. The operation of the switching devices, depicted as NPN transistors, in a resonant mode allow a voltage between the voltage applied at A and a voltage higher than A depending on the operating regime of the resonant circuit to be available at terminal D. DC to AC conversion

Here the DC voltage is applied between D and C where D is the more positive terminal. If the load connected to A has its other connection connected to the midpoint of the voltage between C and D, then the operation of the switching devices, depicted as NPN transistors, in a resonant mode allows the voltage at A to be taken above or below the midpoint voltage and this impresses an AC waveform on this load with a maximum amplitude swing between zero and the voltage applied at D. AC to DC conversion

Here the AC voltage is applied between A and returned to a point between C and a value that is equal to the peak to peak value of the AC signal present on A, where A is always the more positive terminal relative to C. The load is connected between C and D. The operation of the switching devices, depicted as NPN transistors, in a resonant mode allows the voltage at A to be taken above or below the midpoint voltage and this is converted to a DC voltage between C and D.

Figure 406 shows an example of a resonant frequency conversion block. This is a block diagram of a standard resonant frequency conversion block and shows its main power conversion components, including the resonant dV/dt limiting capacitors and a 3-phase motor connected. It is appreciated that ancillary electronic drive circuit, control and auxiliary power components required to make the circuit operate correctly are not depicted. Due to the symmetrical nature the circuit shown in Figure 406 can be operated in all four quadrants if required.

Figure 407 shows a split function voltage control/frequency control circuit for a quasi-sine motor drive. The block diagram is of a complete high efficiency resonant conversion quasi sine drive. Combined voltage control and frequency control can be achieved with a conversion efficiency in the region of around 99%. The 3 phase rectifiers, depicted as diodes in figure 407, introduce diode drop losses of approximately 1.4 volts at the operating current of the drive. In percentage terms this represents a loss of around 0.3%. For a single phase drive, this is closer to 0.6%. These drive losses are comparable with PWM drive losses where the output stage is hard switching at about 4 to 8 kHz directly into the motor.

Figure 408 shows a graph of different power factors and crest control with a split function drive. Referring to Figure 407 using a normal 3 phase supply (not shown) connected to 6 rectifiers and looking at the rectified waveform between C and D, there is a 120 degree window on each % cycle, for conduction as shown in Figure t 408 as νφχ. As the variable voltage drive output A to C (Figure 407) is set at a level that ensures correct motor torque, at a given motor speed, (in conjunction with the optimum setting of the variable frequency controller) it is usual for there to be continuous electrical connectivity possible to each of the 120 degrees for current conduction. By ensuring this is the case the current waveform is able to be ‘tailored’ to adopt the most suitable current at each instant during the cycle thereby optimising the utility power factor, crest factor and associated harmonics.

Figure 409 shows a block diagram of an active front end driver. This takes the place of the 6 diode rectifiers shown in Figure 407. The block diagram in Figure 409 shows how three voltage control blocks are used so as to provide a versatile active front end power conversion system. In this example, a three phase AC to DC conversion is detailed so at least one of the three phases is always positive at any given time and likewise one of the three phases is always negative. During a full mains cycle there are periods where two of the three phases are positive and likewise there are times when two of the three phases are negative. The topology in AC to DC mode, is a composite of synchronous rectification and boost voltage conversion. The circuit in Figure 409 also ensures that the current drawn from the three phase connection L1, L2 and L3 is power factor corrected, has a low crest factor and is supportive of the voltage waveform. In its DC to AC mode the circuit is also capable of full four quadrant operation.

Figure 410 shows Figure 409 with an active front end. Referring to Figure 410 it shows how a multi function motor drive is configured. A DC connection point marked +ve and 0 between the active front end and the voltage control, allows a point of connection that provides a relatively stable and predictable voltage. The active front end in Figure 410 boosts an incoming mains supply connected to the inputs of the active front end to this voltage level. The Voltage controller in Figure 410 can operate from zero volts to Vmax so as to isolate the motor from the voltage present at the DC link connection point.. The voltage controller in Figure 410 is adapted to reduce the.voltage for normal motor operation. It will also operate with current flow in the opposite direction and under these conditions it can also boost the motor output voltage under braking to regenerate kinetic energy from the motor to electrical energy if required. This is then available at the DC power input / output connection for storage or as power for other motors that may share this connection point.

It can be seen that the incorporation of the active front end in Figure 410 converts the motor drive, the combination of active front end, voltage control and frequency control into an energy management mechanism. The active front end, Figure 409, is also suitable for use with a conventional PWM drive. In fact use of the active front end, Figure 409, with a PWM drive as shown in Figure 401b where the six rectifiers are replaced with the active front end, is particularly beneficial as the active front end, Figure 409, can be used in place of line reactors (in Figure 403) which have to be present for a conventional PWM motor drive installation.

In a practical application, the line power may be connected directly to the active front end, Figure 409, and in which case the DC output shown in Figure 409 is connected to the PWM motor drive as shown in figure 401b at its external DC link connection which is directly connected to either end of the DC link capacitor in Figure 401b.

The active front end also can be used to isolate the three phase supply from the DC connection point so that the integrity of the DC supply to the connection point can be maintained during power outage or disconnect conditions of a mains supply.

Figure 411 shows diagrammatically a range of power factor and crest control techniques using an active front end and a split function drive. Because there is a combination of synchronous rectification (active rectification) and step up conversion on each of the three phase inputs, it is possible to perform power factor correction over the full 360 degrees of the waveform. A conventional diode rectifier (not shown) and line reactor (not shown) each only has access to 240 degrees of the waveform l at best. This is represented as the current draw window and allows the possibility of an idealised current waveform to be drawn during the whole of the voltage waveform. The stabilised DC output voltage is just above the peak of the ripple of a theoretical voltage ripple waveform that could be achieved by using a conventional full wave rectification of the three phase input.

Figure 412 shows diagrammatically front end current paths under different modes. Figure 412 shows the way that the active front end, in conjunction with some energy storage capability and the motor drive, can perform several functions. Some of the functions can occur at the same time. The size of the energy storage device (not shown) can be adjusted to suit the functions required. An indication of how energy is transferred to/from the unit, as shown in Figure 410, is detailed in Figure 412.

Figure 413 shows a circuit diagram for limiting inrush current at phase input of active front end shown in Figure 409. The circuit in Figure 409 could be the circuit as shown in figure 405 for example. This conducts current in one direction even if the switching devices, shown as NPN transistors in Figure 405, are off. This is because of the parallel diodes placed across the switching devices in the circuit, which behave either as part of the substrate construction (in the case of a MOSFET) or are added in parallel with the switches, shown as NPN transistors, (in the case of IGBTs).

To avoid inrush current at the instant of connection or reconnection of a supply voltage to input 01 at an active front end of the circuit, it is necessary to incorporate some extra means to eliminate, or at least significantly reduce, the inrush current.

Here an extra switching device is put in series with the line input terminal shown as 01. This extra switching device is connected in the opposite polarity and sense to the existing components in the active front part of the circuit, so if this switching device is turned off, no current can flow into the input of the active front end of the circuit in Figure 413. However it can perform another function in this position. Careful analysis shows that if the switch transistor at the top right‘of Figure 413 is permanently on and the switch transistor at the bottom right of Figure 413 is permanently off, this topology operates in a similar manner to a Buck converter (using the extra diode in parallel with the extra switching device connected to 01) so that power and voltage can be increased in a controllable manner on DC side. Once the DC output is at the peak level of the AC input, the extra switching device connected to 01 can be switched on permanently and the active front end is able to operate in its usual step up (Buck) mode.

Figure 414 shows examples of current inrush limited circuitry added at the junction ' of the +ve connection, shown in Figure 410, between the active front end and DC link. To avoid inrush current at the instant of connection (or reconnection) of the supply voltage to the inputs of the active front end, it is necessary to incorporate some additional means to eliminate, or at least significantly reduce, the inrush current. The circuits (Figure 414a and 414b) behave in very different manner to each other. Figure 414a works very similarly to the switch circuit connected to 01 in Figure 413. However 3 of these switch circuits, one per phase, (it is possible to just use 2 switch circuits for economy purposes) are required to prevent inrush current in Figure 410 for example but because in Figure 414 the extra circuitry is on the DC side of the 3 phase active front end only one extra switching circuit is required. This extra switching circuit in conjunction with the characteristics of the 3 phase active front end ensures complete isolation of current flow under all voltage conditions. In ' Figure 414a the current limiting means is placed between the output of the active Front ends and the DC link connection. Figure 414a shows a modified Buck converter that provides good control of the amount of energy that can be transferred from the active front ends to the DC link. This feature of the invention is very important as it allows reconnection and continuation during ‘brown out’ and blackout conditions without nuisance tripping and therefore offers significant benefits in areas where surety of supply is not always guaranteed.

Figure 414b shows an example of using a conventional resistor and relay to protect against inrush current. A disadvantage with this arrangement is that the resistance value is high in order to limit current inrush when the DC link is at a zero to low voltage at the point of application of the utility to the three phase inputs. This value is too high to allow for normal motor operation so a state exists where the motor has to be disconnected until the DC link has been established at the correct voltage. Also the resistance is present when the voltages are higher on the three phase input side than the voltage present on the DC link even when the switching devices in the 3 phase active front end are off.

Aspects of the invention have been described by way of a number of exemplary embodiments, each exhibiting different advantageous features or benefits; and it is understood that features, components or circuits from two or more of the aforementioned embodiments may be combined together to overcome specific problems or to provide a bespoke solution to a particular problem.

Figure 501 shows load dump position across intermediate voltage point, showing the position of the load dump between the variable voltage block and the variable frequency block. This allows the load dump to operate at an intermediate voltage between zero and the supply input voltage.

In a typical PWM drive (see Figure 401a) the regenerated power appears as an increase in voltage above the supplied input voltage. Thus all the components have to be of a higher voltage rating as a consequence of that. However, the circuit arrangement of Figure of 501 allows this regeneration and load dumping to be done at an intermediate voltage between zero and the supply voltage. Therefore there is not a need for voltage rating of components above what is required for normal motor \ operation.

Claims (10)

Claims

1. A load dump for connection to a load includes: an energy sink and a controller the controller actuates a switch to divert current to the sink when a threshold is exceeded so as to dissipate excess energy in the sink characterised in that the load dump, at switch on, is intermediate a voltage source and the load.

2. A load dump for connection to a load includes: an energy sink and a controller the controller actuates a switch to divert current to the sink when a threshold is exceeded so as to dissipate excess energy in the sink characterised in that the controller modulates the switch in dependence upon a quantity of energy to be dumped.

3. A load dump for connection to a load includes: an energy sink and a controller the controller actuates a switch to divert current to the sink when a threshold is exceeded so as to dissipate excess energy in the sink characterised in that the controller modulates a frequency of a waveform applied to the load so as to vary an intermediate voltage applied to the load at switch on.

4. A load dump according to claim 3 includes: an energy sink and a controller the controller actuates a switch to divert current to the sink when a threshold is exceeded so as to dissipate excess energy in the sink characterised in that the controller modulates the switch in dependence upon a quantity of energy to be dumped.

5. A load dump according to any of claims 1 to 4 wherein a sensor provides an input to the controller to indicate

6. A load dump according to any preceding claim wherein the controller is operative to reduce a supply voltage and operates to dissipate excess energy at the reduced supply voltage.

7. A load dump according to claim 1 or 2 wherein the load is an induction motor.

8. A intermediate load dump according to claim 1 or 2 wherein the load is an permanent magnet motor.

9. A intermediate load dump according to claim 1 or 2 wherein the load is an switched/variable reluctance motor.

10. A load dump according to claim 3 or 4 wherein the controller also modulates the frequency of an applied voltage to the switch in accordance with a user specified rate of change of acceleration/deceleration.