GB2549364A

GB2549364A - Touch sensing device

Info

Publication number: GB2549364A
Application number: GB1701580.1A
Authority: GB
Inventors: Zheng Jianqing; Hu Jicheng
Original assignee: Individual
Current assignee: Individual
Priority date: 2016-02-01
Filing date: 2017-01-31
Publication date: 2017-10-18
Also published as: GB201701580D0

Abstract

Disclosed is a capacitive touch sensing device 100 with a key press cover region 1 comprising key and non-key areas. Underneath the key press cover region is a capacitive sensing layer 2, underneath which is a line layer 3 which has a first region 101 underneath the key area and a second region 103 underneath the non-key area. The line layer also has a signal line 7 connected to capacitive sensing layer in the first region and which extends into the second region. The line layer also has an identification line 11 located in the second region and parallel to the signal line. A logic circuit 5 filters an incorrect sensing state by processing the sensing state of the signal line and the identification line 11. Also, disclosed is a capacitive touch sensing device in which the signal line spirals outward from the centre of the first region.

Description

CAPACITIVE TOUCH SENSING DEVICE

The present invention relates to a capacitive touch sensing device. In particular, the present invention relates to a capacitive touch sensing device which is controlled by a logic circuit.

Capacitive touch sensing technologies are widely available. However, there are at least two common problems with the current fabrication and utilization of capacitive touch sensing devices. One such problem is that wrong signals may be induced by a parasitic capacitor between two signal lines. Another such problem is that wrong/incorrect signals are caused by a user touching non-target induction areas which results in the induction of parasitic capacitance between the signal line and ground line. To avoid these problems, existing capacitive touch sensing devices require adjustment of the sensitivity of the capacitance, and there are some limitations for line configuration modes (such as how the lines are arranged in the line layer). These existing solutions are not effective and limit the density of touch spots, i.e. regions that can sense a touch event applied to the capacitive touch sensing device.

It is one objective of the present invention to implement a capacitive touch sensing device controlled by logic circuit with a simple construction in order to solve the wrong signal problem caused by the parasitic capacitor, or at least provide an alternative to existing capacitive touch sensing devices.

Accordingly, the present invention provides a capacitive touch sensing device comprising: a key press cover region comprising a key area and a non-key area; a capacitive sensing layer arranged underneath the key press cover region; a line layer disposed underneath the capacitive sensing layer and comprising a first region underneath the key area and a second region underneath the non-key area, the line layer further comprising a signal line adapted to be connected to the capacitive sensing layer in the first region and which extends into the second region, and an identification line located in the second region and arranged parallel to the signal line; and a logic circuit adapted to filter an incorrect sensing state by processing the sensing state of the signal line and the identification line.

Advantageously, when the signal line is influenced by the stray capacitance, parasitic capacitance, it will be reflected in the identification line. The logic circuit is able to eliminate these stray/parasitic capacitance influences on the signal line. In addition, the present invention is able to reduce the possibility of recording an incorrect touch as a valid touch on the key area of the capacitive touch sensing device. The states of the sensing area can be determined by the identification lines to avoid the incorrect signal caused by over-sensitivity of the induction capacitor. Hence, the accuracy can be greatly increased. The present invention is also able to filter the incorrect sensing state by logic circuit processing the sensing state of the signal line and identification line, thereby increasing the contact density.

The identification line may have substantially the equivalent capacitance or the equivalent capacitance to the part of the signal line in the second region. The identification line may have substantially the equivalent capacitance to the signal line. The identification line may have the equivalent capacitance to the signal line. The logic circuit may be adapted to filter an incorrect sensing state by determining whether the identification line has been influenced by an outside source.

The logic circuit may be adapted to determine that a touch event has occurred for the key area in response to determining that the sensing state of the signal line indicates a touch event and the sensing state of the identification line indicates that the identification line has not been influenced by an outside source.

The logic circuit may be adapted to determine that a touch event has not occurred for the key area in response to determining that the sensing state of the signal line indicates a touch event and the sensing state of the identification line indicates that the identification line has been influenced by an outside source.

In the first region, the signal line may spiral outwardly from a central area of the first region / form a coil extending outwardly from a central area of the first region. The signal line may be drawn out from the capacitance ends of the capacitive sensing layer, starting at the central area of the first region. Here “capacitance ends” may refer to the terminals of the capacitive sensing layer. For example, if the capacitive sensing layer comprises two lines of printed conductive ink then the “capacitance ends” means the terminals of these two lines. The signal line may coil/spiral outwardly from the central area and exit the first region. Advantageously, this coiled/spiralled arrangement of the signal line increases the sensitivity of the capacitance in the sensing area.

The line layer may further comprise a ground line adapted to be connected to the capacitive sensing layer in the first region and which extends into the second region.

In the first region, the ground line may form the spiral with the signal line / form the coil extending outwardly from the central area of the first region. The ground line may be drawn out from the capacitance ends of the capacitive sensing layer, starting at the central area of the first region. The ground line may coil/spiral outwardly from the central area and exit the first region.

The signal line and the ground line may extend into the second region from spaced apart sections of the first region.

The capacitive touch sensing device may further comprise a capacitance measurement circuit. The capacitance measurement circuit may be adapted to receive the signal line and the identification line as inputs, and may output a signal measurement line and an identification measurement line to the logic circuit. The capacitance measurement circuit may comprise a TCH chip. The signal line and the identification line may be connected to input pins of the capacitance measurement circuit/TCH chip. The output pins of the capacitance measurement circuit/TCH chip may be connected with input pins of the logic circuit. The TCH chip may be a TCH601 chip.

The capacitive touch sensing device may further comprise a reference measurement capacitor adapted to be connected to the capacitance measurement circuit. The reference measurement capacitor may be connected between pins CAP IN and CAP OUT of the TCH chip such as TCH601. The capacitance of the reference measurement capacitor may be between 400 to 4000 times larger than the capacitance of the capacitance sensing layer.

The capacitive touch sensing device may further comprise a central processor, the central processor being adapted to receive the output of the logic circuit. Output pins of the logic circuit may connect with the central processor. Alternatively, the output of the logic circuit will be implemented directly by the capacitive touch sensing device.

The capacitive sensing layer may further comprise an upper conductive ink layer, an intermediate insulating layer, and a lower conductive ink layer.

The key press cover region may comprise a plurality of key areas and a plurality of non-key areas.

For each key area, the line layer comprises a first region underneath the key area, a signal line adapted to be connected to the capacitive sensing layer in the first region and which extends into the second region, and an identification line which is located in the second region and arranged parallel to the signal line.

The logic circuit may be part of a touch key circuit provided in or underneath the line layer. The capacitance measurement circuit may be part of the touch key circuit. The logic circuit may comprise a logic module chip. The logic module chip may contain a NOT logic gate and an AND logic gates or more than one NOT logic gate and more than one AND logic gate.

The capacitive sensing layer, line layer and/or touch key circuit may be sequentially laminated under the key press cover region.

The line layer may comprise a power source/line.

Accordingly, the present invention further provides a capacitive touch sensing device comprising: a key press cover region comprising a key area and a non-key area; a capacitive sensing layer arranged underneath the key press cover region; a line layer disposed underneath the capacitive sensing layer, the line layer comprising a first region underneath the key area and a second region underneath the non-key area, the line layer further comprising a signal line adapted to be connected to the capacitive sensing layer in the first region and which extends into the second region, wherein, in the first region, the signal line spirals outwardly from a central area of the first region.

In the first region, the ground line may form the spiral with the signal line.

Accordingly, the present invention further provides a capacitive touch sensing device controlled by a logic circuit, comprising a cover region provided with key-presses. The capacitive touch sensing device may further comprise a capacitive sensing layer, a line layer, and touch keys circuit are sequentially laminated under the key-presses cover region. The capacitive sensing layer may comprise an upper conductive ink layer, an intermediate insulating layer, and a lower conductive ink layer. The line layer may comprise power, a ground line and a central processor. The line layer may further comprise a touch key circuit. The touch key circuit may comprise a capacitance measurement circuit and logic control circuit, where the capacitance measurement circuit may comprise a TCH chip, and the logic control circuit may comprise a logic module chip. The ground line and the signal line may be drawn out from the capacitance ends of the capacitive sensing layer. The ground and signal lines underneath the key area may extend from the centre of the key area as a starting point and coil/spiral outwardly and spaced apart from one another. The ground and signal lines may be drawn out separately from the key area, such as from diagonally opposite ends of the key area. The ground and signal lines may be drawn out from the key area after the parts of the ground and signal lines which form the coil/spiral have fulfilled/covered a large part or a sufficient amount of area under the key area.

In the line layer, the signal lines underneath the key area may extend into the corresponding area of the line layer underneath the non-key area. These signal lines may be arranged in parallel and may have the equivalent capacitance to an identification line arranged in the corresponding area of the line layer underneath the non-key area. Only the part of the signal line in the non-key area may have the equivalent capacitance to the non-key area. Ground lines and signal lines which draw out from the capacitance of capacitive sensing layer should be connected to the ground line and signal line from line layer respectively.

The input pins of the TCH chip from capacitance measurement circuit may be connected to the corresponding signal line and paralleled identification line of the line layer. The output pins of the capacitance measurement circuit TCH chip may be connected with the input pins of logic module chip. The out pins of logic module chip may be connected to central processor of the line layer.

The chip for capacitance measurement circuit may be TCH601. A reference measurement capacitor C may be connected between pin CAP IN and CAP OUT of chip TCH601. The capacitance of the reference measurement capacitor C may be 400 to 4000 times larger than the corresponding capacitance of the capacitance sensing layer.

The logic module chip from logic control circuit may contain a NOT logic gate and an AND logic gate.

Various combinations of optional features have been described herein, and it will be appreciated that described features may be combined in any suitable combination. In particular, the features of any one example embodiment may be combined with features of any other embodiment, as appropriate, except where such combinations are mutually exclusive. Throughout this specification, the term “comprising” or “comprises” means including the component(s) specified but not to the exclusion of the presence of others.

For a better understanding of the invention, and to show how embodiments of the same may be carried into effect, reference will now be made, by way of example only, to the accompanying diagrammatic drawings in which:

Figure 1 is a sectional schematic diagram of a capacitive touch sensing device according to an example embodiment;

Figure 2 is a schematic diagram of a key area of the capacitive touch sensing device according to an example embodiment;

Figure 3 is a schematic diagram of a capacitance measurement circuit and logic circuit of the capacitive touch sensing device according to an example embodiment;

Figure 4 is a schematic diagram of a logic circuit of the capacitive touch sensing device according to an example embodiment; and

Figure 5 is a schematic diagram of the capacitive touch sensing device according to an example embodiment.

Referring to Figure 1 there is shown a capacitive touch sensing device indicated generally by the reference numeral 100. The capacitive touch sensing device 100 comprises a key press cover region 1 comprising a key area and a non-key area. A capacitive sensing layer generally indicated by the reference numeral 2 is provided disposed underneath the key press cover region 1. A line layer generally indicated by the reference numeral 3 is also provided disposed underneath the capacitive sensing layer 2.

Referring to Figure 2, the line layer 3 comprises a first region 101 underneath the key area and a second region 103 underneath the non-key area. In the first region 101, the line layer 3 comprises a signal line 7. The signal line 7 is connected to the capacitive sensing layer 2 in the first region 101 and extends into the second region 103. In one example, a signal line is drawn out of the capacitance ends of the capacitive sensing layer 2 and connects with the signal line 7 from the line layer 3. While not shown in Figure 2, the line layer 3 further comprises an identification line 11 and a logic circuit 5. The identification line 11 is located in the second region 103 and is arranged parallel to the signal line 7. That is the identification line 11 is arranged parallel to the part of the signal line 7 in the second region 103. The logic circuit 5 filters an incorrect sensing state by processing the sensing state of the signal line 7 and the identification line 11.

Including the identification line 11 arranged parallel to the signal line 7 in the second region 103 means that the identification line 11 is parallel to the part of the signal line 7 in the second region 103. This means that when the signal line 7 is influenced by a stray capacitance or a parasitic capacitance in the second region 103, this capacitance will also be reflected in the identification line 11. In view of this, the logic circuit 5 is able to eliminate these incorrect influences.

For example, if a touch event occurs in the key area then this will be reflected in the signal line 7 and will be processed by the logic circuit 5. If the identification line 11 has not been influenced by an outside source, then the logic circuit 5 will determine that the sensing state of the signal line 7 is valid (i.e. that there has been an actual touch event in the key area).

For example, if a touch event has not occurred but a source of stray or parasitic capacitance or a touch event has occurred in a non-touch area, then a sensing state indicating a touch event will be reflected in the signal line 7. If the identification line 11 and logic circuit 5 were not present, then the capacitive touch sensing device may operate on the assumption that a valid touch even in the key area has occurred because the signal line 7 indicates a touch event. Advantageously, the present invention provides the identification line 11 and the logic circuit 5 which can filter out these incorrect/false touching events and thereby greatly increase the accuracy of the capacitive touch sensing device 100. In particular, as the identification line 11 runs parallel to the signal line 7, it will also be influenced by the source of stray or parasitic capacitance or touch event in the non-touch area. The logic circuit 5 can process the sensing state of the signal line 7 and the identification line 11, and thus determine that an incorrect sensing state is present.

Therefore, when the signal line 7 is influenced by a stray capacitance/parasitic capacitance, it will be reflected in the identification line 11. The logic circuit 5 can therefore eliminate these influences and is also able to reduce the possibility of an incorrect touch. The states of the sensing area can be determined by the identification lines 11, to avoid the incorrect signal caused by over-sensitivity of the induction capacitor. Hence, the accuracy can be greatly increased. The present invention is also able to filter the incorrect sensing state by the logic circuit 5 processing the sensing state of the signal line 7 and identification line 11, thereby increasing the contact density.

The identification line 11 has substantially the equivalent capacitance or the equivalent capacitance to the signal line 7 or the part of the signal line 7 in the second region 103. Since the identification line 11 and the signal line 7 has the same capacitance values, which are parallel with each other in non-key area, when the signal line 7 is influenced by the stray capacitance or parasitic capacitance this influence will be reflected in the identification line 11.

The logic circuit 5 is able to eliminate these influences, and also reduce the possibility of an incorrect touch.

Referring to Figure 2, there is shown an arrangement of the signal line 7 in the first region 101 according to an example embodiment. Here, the signal line 7 spirals outwardly from a central area 105 of the first region 101. In other words, the signal line 7 forms a coil extending outwardly from the central area 105 of the first region 101. The signal line 7 is drawn out from the capacitance ends of the capacitive sensing layer 3. In particular, a signal line extends from the capacitance ends of the capacitive sensing layer 3 and connects with the signal line 7 in the central area 105 of the first region 101. The signal line 7 coils/spirals outwardly from the central area 105 and exits the first region 101. When the signal line 7 exits the first region 101 it is substantially straight. This coiled/spiralled arrangement of the signal line 7 is advantageous in that it increases the sensitivity of the capacitance in the sensing area. As the figure 2 shows, this configuration increased the length of the sensing area as well as the sensitivity of the capacitance.

Referring to Figure 2, the line layer 3 further comprises a ground line 8. The ground line 8 is connected to the capacitive sensing layer 2 in the first region 101 and extends into the second region 103. In one example, a ground line is drawn out of the capacitance ends of the capacitive sensing layer 2 and connects with the ground line 8 from the line layer 3. Like the signal line 7, the ground line 8 spirals outwardly from the central area 105 of the first region 101. In other words, the ground line 8 forms a coil extending outwardly from the central area 105 of the first region 101. The ground line 8 is drawn out from the capacitance ends of the capacitive sensing layer 2. In particular, a ground line is drawn out from the capacitance ends of the capacitive sensing layer 2 and connects with the ground line 8 in the central area 105 of the first region 101. The ground line 8 coils/spirals outwardly from the central area 105 of the first region 101 and exits the first region 101. When the ground line 8 exits the first region 101 it is substantially straight. This coiled/spiralled arrangement of the ground line 8 is advantageous in that it cooperates with the arrangement of the signal line 7 to increase the sensitivity of the capacitance in the sensing area. As Figure 2 shows, this configuration increased the length of the sensing area as well as the sensitivity of the capacitance.

As can be seen in Figure 2, the signal line 7 and the ground line 8 coil/spiral in the same direction and generally form the same coil/spiral shape. The signal line 7 and ground line 8 are spaced apart from one another. The signal line 7 and the ground line 8 extend into the second region 103 from spaced apart sections of the first region 101. In particular, as shown in Figure 2, the signal line 7 exits from the lower left-hand corner of the first region 101 while the ground line 8 exits from the upper right-hand corner of the first region 103. In other words, the signal line 7 and ground line 8 exits the first region 101 from diagonally opposite ends of the first region 101. Other arrangements are within the scope of the present invention. As Figure 2 shows, this configuration increases the length of the sensing area as well as the sensitivity of the capacitance.

In one example, the capacitive sensing layer 2, line layer 3, and a touch key circuit (not shown) are sequentially laminated under the key-presses cover region. The touch key circuit contains a capacitance measurement circuit 4 and/or the logic control circuit 5. In one example, the line layer 3 includes a power source/line (not shown), ground line 8 and a central processor (not shown).

In one example as shown in Figure 1, the capacitive sensing layer 2 comprises an upper conductive ink layer 21, an intermediate insulating layer 22, and a lower conductive ink layer 23. The present invention is not limited to this particular arrangement of capacitive sensing layer 2. The terminals of the upper conductive ink layer 21 and lower conductive ink layer 23 may form the “capacitance ends” which the ground line 8 and signal line 7 in the line layer 3 connect to.

The capacitive touch sensing device 100 comprises a capacitance measurement circuit 4. The capacitance measurement circuit 4 is adapted to receive the signal line 7 and the identification line 11 as inputs, and output a signal measurement line and an identification measurement line to the logic circuit 5. The capacitance measurement circuit 4 may comprise a TCH chip or a TCFI601 but is not limited to any particular form of capacitance measurement circuit. Other forms of TCFI chip and capacitance measurement circuits which perform the desired capacitance measurement circuit function can be used as appropriate.

The capacitive touch sensing device 100 comprises a reference measurement capacitor (not shown) which is connected to the capacitance measurement circuit 4. In one example, the capacitance of the reference measurement capacitor is between 400 to 4000 times larger than the capacitance of the capacitance sensing layer 2.

Referring to Figure 3, there is shown a particular example arrangement of the capacitance measurement circuit 4 and logic circuit 5. In this example, the capacitive touch sensing device 100 has six key areas in the key press cover region 1. As a result, the line layer 3 has six first regions 101 each of which is under one of the six key areas. Each of the six first regions 101 has a signal line 7 which extends into the second region 103. In some examples, the signal lines 7 in the first regions 101 will be arranged in a spiral/coil as shown in Figure 2. In some examples, each first region 101 will have a ground region 8 which may be arranged in a spiral/coil as shown in Figure 2. The second region 103 has an identification line 11 for each of the signal lines 7. Each identification line 11 will be arranged parallel to its corresponding signal line 7.

Therefore, in this example the capacitance measurement circuit 4 has six signal line 7 inputs “Button 1”, “Button 2”, “Button 3”, “Button 4”, “Button 5”, and “Button 6” and six corresponding identification line 11 inputs “Identify 1 ”, “Identify 2”, “Identify 3”, “Identify 4”, “Identify 5” and “Identify 6”.

In this example, the capacitance measurement circuit 4 comprises two TCH601 chips 41, 43. Each TCFI601 chip 41, 43 has a “CAP IN” and a “CAP OUT” pin for connection to a reference measurement capacitor (not shown). Further, each TCH601 chip 41,43 has “KEY 0” to “KEY 5” input pins for receiving three signal lines 7 and the corresponding three identification lines 11 as inputs. Each TCH601 chip 41, 43 of the capacitance measurement circuit 4 further comprises “OUT 0” to “OUT 5” output pins for outputting the signal measurement lines and identification measurement lines.

The logic circuit 5 of this example comprises a logic module chip 50 which has six input pins “SI 0” to “SI 5” for receiving the six signal measurement lines from the capacitance measurement circuit 4 and six input pins “ID 0” to “ID 5” for receiving the six identification measurement lines from the capacitance measurement circuit 4. The logic module chip 50 of the logic circuit 5 has six output pins “OUT 0” to OUT 5” for outputting the results of the logic circuit 5’s determination to a central processor (not shown) of the capacitive touch sensing device 100. In one example, central processor is part of the line layer 3. The logic circuit 5 may also output the results of the logic circuit 5 to an implementation part of the capacitive touch sensing device 100 meaning that the central processor does not have to be present.

Therefore, in this example the signal line 7 of the line layer ( “Button”) and the paralleled identification line 11 (“Identify”) are connected to the input pins “Key 0” to “Key 5” of the capacitance measuring circuit 4 chip TCH 41,43. The output pins “OUT 0” to “OUT 5” of capacitance measuring circuit 4 chip TCH 41,43 are connected to the input pins “SI 0” to “SI 5” and “ID 0” to “ID 5” of logic module chip 50 of logic circuit 5. The output pins “OUT 0” to “OUT 5” of the logic module chip 50 of logic circuit 5 are connected to the central processor of the line layer 3.

Therefore, in this example which uses six key areas, the capacitance measuring circuit 4 uses two TCH601 chips 41, 43. Focusing on the first key area, there is a signal line 7 connected to the first key area and referred to as “Buttonl” and a parallel identification line 11 referred to as “Identifyl”. The TCH601 chip 41,43 has corresponding input pins “KEY 0”, “KEY 1” for connecting to “Button 1” and “Identify 1”. The TCH601 chip 41, 43 has corresponding output pins “OUT 0”, “OUT 1” for outputting the signal measurement line and identification measurement line for “Button 1” and “Identify 1”. The logic module chip 50 of the logic circuit 5 has corresponding input pins “SI 0”, “ID 0” for receiving the signal measurement line and identification measurement line for “Button 1” and “Identify 1”. The logic module chip 50 of logic circuit 5 has a corresponding output pin “OUT 0” for outputting the logic determination result for “Button 1 ” and “Identify 1 ”. The output signal for “OUT 0” is connected to a central processor, or can also be directly output to the implementation part of the capacitive touch sensing device 100. In other words, the logic circuit 5 does not have to be connected to a central processor.

In this example a reference measurement capacitor is connected between the input pins “CAP IN”, “CAP OUT” of chip TCH601, whose capacitance value and desired sensitivity can be adjusted according to the actual circuit. The capacitance of the reference measurement capacitor is between 400 to 4000 times larger than the corresponding capacitive sensing layer 2. Usually the larger the capacitance value, the lower the sensitivity, and the smaller the capacitance value, the higher the sensitivity.

Therefore, in this example a TCH601 chip can receive signals of the three key areas. The logic module chip 50 of the logic circuit 5 can receive signals given from six key areas. It will be appreciated that TCH chip has a variety of model specifications, and the skilled person in the art can select the appropriate size according to the number of the key areas and other factors as appropriate.

Referring to Figure 4, there is shown an example structure of the logic module chip 50 of logic circuit 5. Here, the logic module chip 50 of logic circuit 5 is designed to process the sensing state of six signal lines 7 via input pins “SI 1” to “SI 6” and six identification lines 11 via input pins “ID 1 ” to “ID 6”. The logic module chip 50 of this example shown in Figure 4 could for example be the logic module chip 50 shown in Figure 4 which receives signal and identification measurement lines from the capacitance measurement circuit 4.

For a first key area, the sensing state of the signal line 7 is received via input pin “SI 1” and forms the first input of an AND logic gate 10. The sensing state of identification line 11 is received via input pin “ID 1 ” and forms the input of a NOT logic gate 9. The output of the NOT logic gate 9 forms the second input of the AND logic gate 10. Therefore, in this example, the logic module chip 50 is performing the Boolean operation NOT(“ID 1”) AND “SI 1”. As will be appreciated, a truth table for this example logic module chip 50 provides the following:

Therefore, the logic module chip 50 only returns a True result indicating that the first key area has been touched when the sensing state of signal line 7 input at “SI 1” is True (i.e. a touch has occurred) and the sensing state of identification line 11 input at “ID 1” is False (i.e. a signal has not been induced in the identification line 11). In this way, the arrangement of the identification line 11 parallel to the signal line 7 achieves the effect of filtering out incorrect sensing states. The same structure of logic gates is provided for each key area in this example shown in Figure 4.

Therefore, in this example the logic module chip 50 includes AND gates 10 and NOT gate 9. The signal of the signal sensing/measurement line of the capacitance measuring circuit 4 is directly connected to AND gate 10. The corresponding identification sensing/measurement line of the capacitance measurement circuit 4 is first connected to the NOT gate 9, and then connected to the AND gate 10. The output signal of the AND gate 10 is sent to the central processor or implementation part of the device.

Therefore, in this example, if the key area of key press cover region 1 is touched, the alternation current of the signal line 7 “Buttonl” will be transmitted to the TCH601 chip pin KEYO of the capacitance measuring circuit 4. When the TCH601 chip detects current, its output pin OUT 0” will output a low-level voltage. At this time, if the current on the corresponding identification line 11 does not change, TCH601 chip’s output pin OUT 1” will output a high-level voltage. Corresponding to a low-level output voltage of OUT 0” and high level voltage of OUT 1”, logic module chip 50 outputs a high-level voltage indicating a valid digital signal. If the corresponding identification line 11 is interfered by an outside source, TCH601 chip detects a current, and output pin OUT 1” will output a low-level, which corresponding to a low-level output of OUT 0” and OUT 1”, to filter the incorrect signal.

The present invention is not limited to this particular arrangement. It will be appreciated that different structures of capacitance measurement circuit 4 can be used based on considerations such as the number of desired key areas. In addition, it will be appreciated that the specific arrangement of the logic module chip 50/logic circuit 5 shown is in Figure 4 is only one example of how the logic circuit 5 can filter an incorrect sensing state by processing the sensing state of the signal line 7 and the identification line 11. Different arrangements and types of logic gates could be used to perform the same function as appropriate.

The present invention is not limited to single contact/touch capacitive touch sensing devices, but also applies to multi-touch capacitive touch sensing devices.

Referring to Figure 5, there is shown one example arrangement of the capacitive touch sensing device 100. Here, the capacitive touch sensing device 100 comprises six key areas labelled “Button 1” to “Button 6” arranged in a grid. In the line layer 3, there are ground lines 8 and signal lines 7 exiting the first region 101 underneath the key area and entering the second region 103 underneath the non-key area. In the second region 103 there are identification lines 11 running parallel to each signal line 7. It will be appreciated that in Figure 5, the use of dashes is only intended to distinguish between the different lines. That is, the lines with short dashes are ground lines 8, the lines with longer dashes are identification lines 11, and the continuous lines are signal lines 7.

In one example, the capacitive touch sensing device 100 provides one or more touch sensitive buttons. That is, each key area in the key press cover region 1 acts as a capacitive touch sensing button.

Although a few preferred embodiments of the present invention have been shown and described, it will be appreciated by those skilled in the art that various changes and modifications might be made without departing from the scope of the invention, as defined in the appended claims.

Examples: 1. A capacitive touch sensing device controlled by logic circuit, comprising a cover region provided with key-presses. Capacitive sensing layer, line layer, and touch keys circuit are sequentially laminated under the key-presses cover region. The capacitive sensing layer is composed of an upper conductive ink layer, an intermediate insulating layer, and a lower conductive ink layers. The line layer includes power, ground line and central processor, and a touch key circuit. Touch key circuit comprises a capacitance measurement circuit and a logic control circuit, where the capacitance measurement circuit comprises a TCH chip, the logic control circuit comprising the logic module chip. The ground line and signal line are drawn out from the capacitance ends of the capacitive sensing layer, ground and signal lines in the key area of the centre as a starting point and are coiled/spiralled outwardly in a spaced apart manner, and are drawn out separately from opposed diagonal ends key area after fulfilling the key area.

The line layer in a corresponding non- key area has signal lines arranged in parallel with the equivalent capacitance of the identification line. Ground lines and signal lines are drawn out of the capacitance ends of the capacitive sensing layer and connect with the respective ground and signal lines from the line layer. The input pins of the TCH chip from the capacitance measurement circuit are connected to the corresponding signal line and paralleled identification line of the line layer. The output pins of the capacitance measurement circuit TCH chip are connected with the input pins of the logic module chip, meanwhile, the input pins of logic module chip are connected to central processor of line layer. 2. According to capacitive touch sensing device controlled by logic circuit of example 1, the chip for the capacitance measurement circuit is a TCH601 chip. 3. According to capacitive touch sensing device controlled by logic circuit of example 2, a reference measurement capacitor C is connected between pin CAP IN and CAP OUT of chip TCH601, the capacitance of the reference capacitor C is 400 to 4000 times larger than the corresponding capacitance of the capacitance sensing layer. 4. According to capacitive touch sensing device controlled by logic circuit of example 1, the logic module chip from logic control circuit contains a NOT logic gate and an AND logic gate.

Claims

1. A capacitive touch sensing device comprising: a key press cover region comprising a key area and a non-key area; a capacitive sensing layer arranged underneath the key press cover region; a line layer disposed underneath the capacitive sensing layer and comprising a first region underneath the key area and a second region underneath the non-key area, the line layer further comprising a signal line adapted to be connected to the capacitive sensing layer in the first region and which extends into the second region, and an identification line located in the second region and arranged parallel to the signal line; and a logic circuit adapted to filter an incorrect sensing state by processing the sensing state of the signal line and the identification line.

2. A capacitive touch sensing device as claimed in claim 1, wherein the identification line has substantially the equivalent capacitance to the part of the signal line in the second region.

3. A capacitive touch sensing device as claimed in claim 1 or claim 2, wherein the logic circuit is adapted to filter an incorrect sensing state by determining whether the identification line has been influenced by an outside source.

4. A capacitive touch sensing device as claimed in any preceding claim, wherein the logic circuit is adapted to determine that a touch event has occurred for the key area in response to determining that the sensing state of the signal line indicates a touch event and the sensing state of the identification line indicates that the identification line has not been influenced by an outside source.

5. A capacitive touch sensing device as claimed in any preceding claim, wherein the logic circuit is adapted to determine that a touch event has not occurred for the key area in response to determining that the sensing state of the signal line indicates a touch event and the sensing state of the identification line indicates that the identification line has been influenced by an outside source.

6. A capacitive touch sensing device according to any preceding claim, wherein, in the first region, the signal line spirals outwardly from a central area of the first region.

7. A capacitive touch sensing device as claimed in any preceding claim, wherein the line layer further comprises a ground line adapted to be connected to the capacitive sensing layer in the first region and which extends into the second region.

8. A capacitive touch sensing device as claimed in claim 7 as dependant on claim 6, wherein, in the first region, the ground line forms the spiral with the signal line.

9. A capacitive touch sensing device as claimed in claim 7 or 8, wherein the signal line and the ground line extend into the second region from spaced apart sections of the first region.

10. A capacitive touch sensing device as claimed in any preceding claim, further comprising a capacitance measurement circuit, the capacitance measurement circuit being adapted to receive the signal line and the identification line as inputs, and output a signal measurement line and an identification measurement line to the logic circuit.

11. A capacitive touch sensing device as claimed in claim 10, further comprising a reference measurement capacitor adapted to be connected to the capacitance measurement circuit.

12. A capacitive touch sensing device as claimed in any preceding claim, further comprising a central processor, the central processor being adapted to receive the output of the logic circuit.

13. A capacitive touch sensing device as claimed in any preceding claim, wherein the capacitive sensing layer comprises an upper conductive ink layer, an intermediate insulating layer, and a lower conductive ink layer.

14. A capacitive touch sensing device as claimed in any preceding claim, wherein the key press cover region comprises a plurality of key areas and a plurality of non-key areas.

15. A capacitive touch sensing device as claimed in claim 14, wherein for each key area, the line layer comprises a first region underneath the key area, a signal line adapted to be connected to the capacitive sensing layer in the first region and which extends into the second region, and an identification line which is located in the second region and arranged parallel to the signal line.

16. A capacitive touch sensing device comprising: a key press cover region comprising a key area and a non-key area; a capacitive sensing layer arranged underneath the key press cover region; a line layer disposed underneath the capacitive sensing layer, the line layer comprising a first region underneath the key area and a second region underneath the non-key area, the line layer further comprising a signal line adapted to be connected to the capacitive sensing layer in the first region and which extends into the second region, wherein, in the first region, the signal line spirals outwardly from a central area of the first region.

17. A capacitive touch sensing device as claimed in claim 16, wherein the line layer further comprises a ground line adapted to be connected to the capacitive sensing layer in the first region and which extends into the second region.

18. A capacitive touch sensing device as claimed in claim 17, wherein, in the first region, the ground line forms the spiral with the signal line.

19. A capacitive touch sensing device as claimed in claim 17 or 18, wherein the signal line and the ground line extend into the second region from spaced apart sections of the first region.