GB2545449B - A method and system for controlling transmission of a data stream - Google Patents

Description

TITLE OF THE INVENTION A method and system for controlling transmission of a data stream

FIELD OF THE INVENTION

This invention relates to the field of wireless communication of information and more particularly to wireless communication of video information while complying with an end-to-end latency value.

BACKGROUND OF THE INVENTION

Wireless networking performance can be affected by several factors, such as physical obstructions, network range and distance between devices or wireless network interference generated by systems operating within the same frequency band. A decrease of performance entails transmission errors, i.e., loss of data or reception of erroneous data.

To cope with those errors, the physical or Media Access Control (MAC] layers implement Error Correction Codes [ECC], The physical layer can, for example, implement a convolutional error correction code (such as Viterbi], combined with a block code (such as Reed-Solomon], Alternatively, it can implement a low-density parity-check code. The MAC layer can, for example, implement a Forward Error Correction Code (FEC), or an Automatic Repeat reQuest (ARQ) method. However, despite those ECCs at the physical or MAC level, transmission errors can still subsist at the link or transport layers. If the MAC layer fails to correctly transmit data after several retransmissions, the corresponding transport packet will not be delivered to the transport layer.

As a consequence, in order to obtain an acceptable quality of service, it may be required to implement an ECC at the link or transport layers. At packet level, the ECC can be based on FEC or ARQ method. If the activation of an ECC fails to reduce the error rate below the acceptable threshold, it means that the available network bandwidth is not sufficient to sustain the application data rate. In such a situation, the application data rate requires reduction. A low number of transmission errors is characterized by a low packet error rate. It is defined by the ratio of erroneous or lost packets versus the number of correctly received packets. In addition to a low packet error rate, the application running on top of that network can require a very low transmission latency, i.e., a low delay between data acquisition by the transport layer at a source node and data rendering from the transport layer at a destination node. This may be for example the case of an application dedicated to live video, gaming, videoconferencing, or mixed reality. However, obtaining a low transmission latency together with a low packet error rate is contradictory. An ECC introduces additional transmission latency to the nominal transmission of a packet.

For instance, the FEC is characterized by a FEC window size that corresponds to the number of packets protected by an additional FEC packet. As a consequence, in the worst case, the receiver has to wait for an additional time that corresponds to the FEC window size. Basically, if the FEC window size increases then the maximal transmission latency increases.

The additional latency induced with the ARQ method mainly corresponds to the round trip time (RTT) required to transmit an acknowledgment from the receiver to the transmitter, and to retransmit the missing packet. This time value shall be multiplied by the number of retransmissions allowed. Furthermore, the ARQ method can be characterized by a retransmission window size that corresponds to the time to wait before generating and sending a block acknowledgment. Such parameter is also entitled ‘Flock acknowledgment” in the art and corresponds to the number of blocks acknowledged by a given block. In that case, the additional time value depends both on the RTT and the retransmission window size.

As a first approach to provide low transmission latency combined with a low packet error rate, one may decrease the size of packets in order to decrease the transmission latency of one packet. The transmission rate of packets shall be increased when the size of packets is decreased to support an equivalent application data rate. However, since usual platforms implementing the transport layer do not easily support a packet transmission rate below the millisecond (one packet transmitted every millisecond], such approach is limited. A second approach consists in performing a systematic retransmission, one or several times, of each packet. This guarantees a low packet error rate, without largely increasing the transmission latency. However, such approach entails an increase of bandwidth, and the approach is only applicable when the channel capacity is huge compared to the application data rate to support. Most of the time, bandwidth is a rare resource that is to be shared among different users, and the retransmission of packets for an entire stream is not possible. A third approach is provided by the whitepaper Quality of Service (OoS) Whitepaper. PCS-Series Videoconferencing by Sony which describes a method that switches between FEC-based error control and ARQ-based error control, depending on the packet loss rate of the network. The selection of an ECC is further based on round trip time (RTT): if the RTT is short, an ECC based on the ARQ method is selected, but if the RTT is long, an ECC based on FEC is selected..

Embodiments of the present invention have been devised to address at least the foregoing concern. Let us consider a communication path composed of a plurality of sequenced links defined by nodes. In the case an intermediate node is a relay, the packets are forwarded to the following node without checking missing packets. However, in the case the intermediate node performs data processing, the packets are delivered to the transport layer and missing packets are checked. As a consequence, a link defined by two nodes performing data processing along the path is characterized by an error rate, and a dedicated ECC can be implemented to correct errors of that given link.

In the rest of the document, the term "latency” is used in a general manner to designate a maximal latency. In other words, if data is to be transmitted while respecting a given latency constraint, and if data are received at a latency lower than or equal to that given constraint, then it complies with the latency constraint.

SUMMARY OF THE INVENTION

It is an aim of embodiments of the invention to ensure the selection of an adapted ECC for each link of a path, while respecting a bounded end-to-end latency constraint. In other words, the selection of a relevant ECC is adapted to the error rate of said link, but also has to comply with the end-to-end latency constraint.

To this end, the present invention first provides a method for controlling transmission of a data stream, the method comprising, at a master node: obtaining a maximum latency value, wherein the maximum latency value is to be complied with while transmitting the data stream from a source node to a destination node over a communication path comprising a plurality of links, a link having a status; obtaining a Path Correction scheme (PC] defined by selecting, for each link of the communication path, an Error Correction Code (ECC] from among a plurality of ECCs, an ECC imposing a latency, the selecting of an ECC being adapted to the status of said link, and depending on a comparison between a PC latency value, defined by a total latency of the selected ECCs, and the obtained maximum latency value; and, launching the application of the PC.

In one implementation, the communication path comprises at least at first and second links, and the ECC applied to the first link differs from the ECC applied to the second link.

In one implementation, a different type of ECC is applied to the first link and the second link.

In one implementation, the ECC applied to the first link and the second link is defined by a window size and the window size of the ECC applied to the first link differs from the window size of the ECC applied to the second link.

In one implementation, the status is an error rate.

In one implementation, the ECC is defined by a code rate, and the code rate is determined so as to correct a number of errors determined by the error rate, and the selecting of an ECC comprises adapting the code rate such that the PC latency value complies with the maximum latency value.

In one implementation, the ECC is defined by a window size, and the window size is determined so as to correct a number of errors determined by the error rate.

In one implementation, the ECC is defined by a window size greater than 1, and the selecting of an ECC comprises reducing the window size such that the PC latency value complies with the maximum latency value.

In one implementation, an ECC is selected for a plurality of links, and each link of the plurality equally applies the reducing step.

In one implementation, the reduction step is based on a minimal increase of bandwidth along the communication path.

In one implementation, obtaining a PC comprises determining a plurality of different PCs and selecting a PC among the plurality of different PCs.

In one implementation, selecting a PC comprises obtaining data indicating that at least one link of the communication path gets at least one error burst, and selecting at least one PC among the plurality of PCs comprising the higher number of links with at least one error burst corrected by an ARQ method.

In one implementation, selecting a PC comprises selecting the path correction scheme having the minimum latency value among the plurality of different path correction schemes.

In one implementation, the method for controlling transmission of a data stream further comprises, prior to obtaining a PC, obtaining a non-corrected transport layer error rate for each link of the communication path; determining a path error rate based on the obtained error rates; comparing the path error rate with a predetermined value; and, in response to the comparing step, adapting application data rate of the data stream.

In one implementation, the method for controlling transmission of a data stream further comprises obtaining a corrected transport layer error rate for each link of the communication path; determining a path error rate based on the obtained error rates; comparing the path error rate with a predetermined value; and, in response to the comparing step, adapting application data rate of the data stream.

In one implementation, determining a path error rate comprises selecting the highest error rate among the obtained error rates.

In one implementation, determining a path error rate comprises determining the sum of the obtained error rates.

In one implementation, adapting application data rate of the data stream comprises increasing application data rate of the data stream.

In one implementation, the method for controlling transmission of a data stream further comprises deactivating any ECC applied on each link of the communication path and decreasing application data rate of the data stream.

In one implementation, the method for controlling transmission of a data stream further comprises deactivating any ECC applied on each link of the communication path and decreasing application data rate of the data stream.

In one implementation the launching step comprises sending error correction methods of the selected path correction scheme to nodes of the path; and, sending a message to the source node indicating to apply the selected path correction scheme.

According to a second aspect, the present invention provides a system for controlling transmission of a data stream, comprising: a module configured for obtaining a maximum latency value, wherein the maximum latency value is to be complied with while transmitting the data stream from a source node to a destination node over a communication path comprising a plurality of links, a link having a status; a module configured for obtaining a Path Correction scheme (PC] defined by selecting, for each link of the communication path, an Error Correction Code (ECC) from among a plurality of ECCs, an ECC imposing a latency, the selecting of an ECC being adapted to the status of said link, and depending on a comparison between a PC latency value, defined by a total latency of the selected ECCs, and the obtained maximum latency value; and, a module configured for launching the application of the PC.

Embodiments of the present invention also extend to programs which, when run on a computer or processor, cause the computer or processor to carry out the method described above or which, when loaded into a programmable system, cause that system to become the system described above. The program may be provided by itself, or carried by a carrier medium. The carrier medium may be a storage or recording medium, or it may be a transmission medium such as a signal. A program embodying the present invention may be transitory or non-transitory.

BRIEF DESCRIPTION OF THE DRAWINGS

Figures la, lb, lc and Id depict for illustrative purposes network topologies in which the invention is applicable.

Figure 2a illustrates a functional block diagram of a communication device according to an embodiment of the invention.

Figure 2b depicts an illustration of the protocol stack.

Figure 3a depicts an application of an XOR-based FEC as an ECC.

Figure 3b depicts an application of an ARQ method as an ECC.

Figure 4 illustrates the suitable path correction schemes based on packet error rates. Figures 5a, 5b and 5c are flowcharts of algorithms executed by a master node according to the invention.

Figures 6a and 6b are two sequence diagrams illustrating the application of a path correction scheme according to the invention.

Figures 7a illustrates different types of protocol messages exchanged by nodes when applying a path correction scheme.

Figure 7b and 7c illustrate the progress of the application of a path correction scheme and the corresponding protocol messages.

Figure 8 is a finite-state machine illustrating an algorithm implemented by the source node according to the invention.

Figure 9 is a finite-state machine illustrating an algorithm implemented by an intermediate node according to the invention.

Figure 10 is a finite-state machine illustrating an algorithm implemented by a destination node according to the invention.

DETAILED DESCRIPTION OF THE INVENTION

Figure la represents a first network topology comprising two devices 101 and 102 communicating in a bi-directional manner through wireless link 111 from device 101 to device 102 and wireless link 112 from device 102 to device 101. The device 101 is both the source and the destination node, while the device 102 is an intermediate node performing data processing during a bounded time T.

Such network topology is particularly relevant for a wireless mixed reality system in which the device 101 is integrated in a helmet equipped with video cameras and displays. A first video stream captured by the video cameras is compressed, packetized and wirelessly transmitted through the wireless link 111 to the device 102 that analyses captured images and merges them with synthetic images. This second video stream is compressed, packetized and wirelessly transmitted to the device 101 for display. Video compression can be performed by the H264 standard codec with a maximum output data rate of 100Mbps. Wireless transmission can be based on 802.11ac standard protocol (5GHz frequency band] providing a MAC throughput of 250Mbps.

Let us consider the example of a first video stream of 100Mbps transmitted through link 111 and providing a throughput of 125Mbps, and a second video stream of 100Mbps transmitted through link 112 and providing a throughput of 125Mbps. For each link, a throughput of 25Mbps is available for control data exchange and for the transmission of data related to an Error Correction Code (ECC],

Ensuring a good quality of experience for the user requires a maximum latency between image acquisition and mixed reality display around 100ms. Taking into account the time necessary for video compression/decompression and data processing of device 102, the maximum transmission latency allowed for wireless transmissions can be around 30ms. This maximum latency is shared between link 111 and link 112. Still, for the purpose of good quality of experience, error transmission must be minimized. This second constraint can be presented as obtaining a packet error rate (PER] below a predefined threshold at the transport layer before delivering data to the video decoder. Based on the packet error rate measured during packet reception (i.e., before transport layer error correction], it may be necessary to implement an ECC in the transport layer to obtain a "packet error rate with error correction” below the predefined threshold.

An error correction, entitled Transport Layer Error Correction (TLEC] in the following, is required for both links, but the required correction capacity may be different for each link. The packet error rate (without TLEC) measured on link 111 may be lower or higher than the packet error rate (without TLEC) measured on link 112. This can be due, for example, to some interference produced by another system in the neighbourhood that disrupts one link but not another.

Figure lb represents a second network topology comprising four devices 121,122,123,124 communicating through a path defined by wireless links 131 (from device 121 to device 122], 132 (from device 122 to device 123], 133 (from device 123 to device 124], 134 (from device 124 to device 123], 135 (from device 123 to device 122] and 136 (from device 122 to device 121). The device 121 is a source node, the device 124 is the destination node, while devices 122 and 123 are intermediate nodes performing data processing during a bounded time T1 for device 102 and T2 for device 123.

Such network topology may be considered for wirelessly transmitting a stream captured by a video camera 121 to a display monitor 124. The path defined by links 131,132,133 is used to transmit control data and the packetized video stream. The return path defined by links 134,135 and 136 is used to transmit control data. The wireless links do not necessarily share the same radio channel. As a matter of fact, the devices may be equipped with dual MAC/PHY interfaces, an interface implementing IEEE 802.11ac standard protocol operating on 5GHz frequency band, and an interface implementing IEEE 802.Had standard protocol operating on 60GHz frequency band. For instance, wireless links 131 and 133 may be 802.11ac links, while wireless link 132 may be an 802.llad link.

In such system, the radio transmission conditions can be completely different between 5GHz and 60GHz links. This situation justifies the need to implement a different ECC, above the MAC layer, for each of the 5GHz and 60GHz links.

Figure lc represents a third network topology comprising four devices 141,142,143,144 communicating through wireless link 151 (from device 141 to device 142), wireless link 152 (from device 143 to device 144), wireless link 153 (from device 144 to device 143), wireless link 154 (from device 142 to device 141), and a wired backbone 155. The device 141 is both the source node for a first data stream (sequence of digital data packets) and the destination node for a second data stream, and the device 144 is both the source node for the second data stream and the destination node for the first data stream, while devices 142 and 143 are intermediate nodes. The path defined by links 151,155 and 152 is used to transmit the first data stream and control data. The path defined by links 153,155 and 154 is used to transmit the second data stream and control data.

Such network topology may be considered for a wireless videoconferencing system between two distant locations. The device 141 generates an audio/video stream at a first location, transmits the packetized stream to device 144 in a second location, and renders audio/video stream received from the device 144 in the second location. The device 144 generates an audio/video stream at the second location, transmits the packetized stream to the first location, and renders audio/video stream received from the first location. The transmission along the wired backbone is considered as a bounded latency Lbackbone, i.e., a latency that does not exceed a predetermined maximal value.

Ensuring a good quality of experience for the user requires the packet transmission between devices 141 and 144 to be bound by an end-to-end maximum latency Lmax. The maximal latency value between devices 141 and 144, and the one between devices 144 and 141 should be equal. The maximal latency allowed for the transmission over wireless links 151 and 152 should be equal to Lmax “ Lbackbone. Similarly to Figures la and lb, different ECC can be implemented for each wireless link, but each one is associated to a given latency that must be taken into account during packet transmission.

Figure Id represents a fourth network topology comprising three devices 161,162 and 163, communicating in a bi-directional manner through wireless link 171 (from device 161 to device 162), wireless link 172 (from device 162 to device 163), wireless link 173 (from device 163 to device 162), and wireless link 174 (from device 162 to device 161). The device 161 is the source and the destination node while devices 162 and 163 are intermediate nodes.

The device 163 performs data processing during a predetermined maximal time T, and the device 162 is used as a relay. This topology can be seen as a variant of the one described in Figure la. Assuming all wireless links are sharing the same radio channel, an ECC, above the MAC layer, should only be implemented in device 161 and 163, since device 162 is a relay with almost no buffering delay. As a consequence, links 171 and 172 are considered as a single link, and the total latency value between devices 161 and 163 corresponds to the sum of the latency values of links 171 and 172. Similarly, links 173 and 174 are considered as a single link. A communication network comprising intermediate nodes acting as relays can then be formalized as a simplified network without relays, but only comprising a source node, a destination node possibly similar to the source node, and intermediate nodes processing a data stream. As a consequence, in the following description, we only refer to simplified networks.

The nodes in Figures la to Id may also communicate control data with at least one other which is not represented. This node may be in charge of controlling the transmission of application data from a source node to a destination node according to the invention.

Figure 2a illustrates a functional block diagram of a device according to an embodiment of the invention. A device 200 comprises: - a Random Access Memory 203 (denoted RAM), - a Read-Only Memory 202 (denoted ROM), - a micro-controller or Central Processing Unit 201 (denoted CPU), - a Media Access Controller 2 04 (denoted MAC) - a physical layer module 205 (denoted PHY), - a Protocol Adaptation Layer 206 (denoted PAL). CPU 201, MAC 204, PAL 206 exchange control information through a communication bus 210, on which are also connected RAM 203, and ROM 202. The CPU 201 controls the overall operation of the device as it is capable of executing, from the memory RAM 203, instructions pertaining to (set out in] a computer program, once these instructions have been loaded from the memory ROM 202.

The PAL 206 performs all necessary transformations of application data (like compression, decompression) and can integrate a dedicated RAM for temporary data storage. The PAL 206 achieves the interface between an application (via external interface 212), and CPU 201 through the RAM 203. The data units generated or consumed by the PAL are stored in RAM 203 and are accessible by CPU 201 for packetization before transmission by the MAC 204, and for depacketization after reception by the MAC 204. MAC 204 is in charge of controlling the emission and reception of MAC frames conveying control data and application data according to a protocol. For instance, MAC 204 implements IEEE 802.11ac standard protocol operating on 5GHz frequency band. MAC 204 can rely on a PHY module 205 that embeds a modem, a radio communication module and antenna. The radio module is responsible for processing a signal output by the modem before it is sent out by means of the antenna. For example, the processing concerns frequency transposition and power amplification processes. Conversely, the radio module is also responsible for processing a signal received by the antenna before being provided to the modem. The modem is responsible for modulating and demodulating the digital data exchanged with the radio module. The modem may also integrate a forward error correction codec to reduce the bit error rate.

If we consider the reception side, the modem of PHY 205 collects the radio frames received from the radio module through the antenna, and sends radio frames to the MAC 204. The MAC 204 is able to detect transmission errors by checking Cyclic Redundancy Check (CRC) data computed and inserted by the MAC 204 at the emitter side. At a destination device, for a given received MAC frame, if the CRC computation result is different from the one received, then the MAC 204 can decide to drop this MAC frame as it is very likely to contain one or several erroneous bits. An ARQ (Automatic Repeat request) method may be used to acknowledge received MAC frame and to trigger retransmission by the emitter. The number of retries can be bounded to avoid the introduction of too large delay. CPU 201 is in charge of implementing transport, network and part of link layer with the functions of packetization and depacketization of application data, the packets transmission scheduling, and error correction.

Among the devices in the network, one is identified as a master in charge of defining transmission parameters for the system according to collected packet error rates measured by receivers. Especially, CPU 201 executes algorithms described by flow charts according to certain embodiments of the invention (Figures 5a, 5b and 5c, 8 and 9).

Figure 2b is a representation of the protocol stack according to an embodiment of the invention. The physical layer 221 is implemented by the PHY module 205, and part ofthe link layer 222 by the MAC 204. The link layer 222 is composed of two sublayers: the logical link control layer and the Media Access Control (MAC) layer. For instance, link layer 222 and physical layer 221 are implemented according to the 802.11ac protocol.

The network layer 223 with Internet protocol is optional and responsible for packet routing. Transport layer 224 implements a transport protocol that may be based on UDP (User Datagram Protocol) or RTP (Real-time Transport Protocol) completed by additional mechanisms for flow control and error correction. The application layer 225 contains PAL 206 (see Figure 2a) which may integrate an H2 64 video codec. The data unit generated by a video encoder and consumed (decompressed) by a video decoder is a NAL (Network Abstraction Layer) unit. NAL units are temporary stored in RAM 203. In order to reduce the application data rate, the video coding rate shall be decreased. Conversely, the application data rate increases when the coding rate increases. Adapting the coding rate to the network available bandwidth is known as the rate control function. This function can be managed by CPU 201. Transport layer 224, Network Layer 223, and the logical link control layer can be implemented in software and executed by CPU 201.

The following description focuses on ECCs implemented in the logical link control or transport layers (TLEC) and performed at packet level. However, certain embodiments of the invention implement error correction in MAC or physical layers, and more generally when means are available to modify the transmission latency. For instance, a Reed-Solomon code can be implemented in the link layer in order to reduce the bit error rate, with configurable parameters having an impact on the decoding latency (for error correction). Furthermore, various modulation and coding schemes can be selected at the physical layer: for example, data transmission using QPSK (quadrature phase-shift keying) modulation leads to a transmission latency longer than data transmission using 16QAM (quadrature amplitude modulation).

Ensuring an acceptable quality of service requires adding ECCs in the logical link control or transport layers (TLEC) in order to reduce the Packet Error Rate (PER) down to an acceptable value. At packet level, the ECC can be based on forward error correction (FEC). Forward error correction method is well adapted to real time applications since it does not require complex data processing. Furthermore, latency for packet recovery can be shortened. Figure 3a illustrates an XOR-based forward error correction at packet level. The principle is the following one: a transmitter regularly inserts an FEC packet every N packets, the FEC packet resulting from XOR operation performed with the N packets previously transmitted. If one of the N packets is missing at the receiver side, it can be recovered through an XOR operation with the N-l correctly received packets and the correctly received FEC packet.

Figure 3a illustrates the time at which an ordered sequence of data packets (comprising, for example, packet Pl (301)) is transmitted by the transport layer of a transmitter node, and the time at which the same data packets (one of them being, for example, packet Pl (305)) are received by the transport layer of a receiver node. The nominal packet transmission latency Lu (so the time between transmission and reception of a packet) is illustrated with the position of packets 301 and 305. For instance, this latency value may be Lo=4ms. The packet transmission rate is considered as constant with an interval TP between packet transmissions equal to the value TP = 1ms (one packet transmitted per millisecond).

For the recovery of missing packet, it is assumed a FEC window (Wfec) equal to 5, with a FEC packet Σ1 (303) and Σ2 (304) inserted every 5 transmitted packets. In this example: Σ1= Pl φ P2 φ P3 φ P4 φ P5 and, Σ2= P6 φ P7 φ P8 φ P9 φ P10, with φ indicating the bit per bitXOR operation.

Figure 3a further illustrates a maximum additional latency introduced by FEC, since packet P6 (302) is not correctly received by the receiver but recovered after the reception of the FEC packet Σ2 (306). P6 is recovered through the operation: P6 = P7 φ P8 φ P9 φ Ρ10φ Σ2

Since packet P6 (302) is the first packet of the FEC window, the latency for recovery is maximum. The maximum additional transmission latency introduced by the FEC equals Wfec * TP. The maximum transmission latency for a link is Lo + Wfec * TP. The more the FEC window increases, the more the latency increases.

The time for packet recovery can be negligible if an FEC packet can be progressively generated on-the-fly at the time of packet transmission in the emitter, or at the time of packet reception in the receiver.

Alternatively, a FEC-based ECC comprising a plurality of redundancy packets associated to a window of size k with k an integer > 1 corresponding to a number of packets can be considered. With such ECC, the number of redundancy packets equals n-k, with n an integer > k corresponding to the number of packets of a block, and the code rate is defined by the value k/n. Such ECC permits to recover up to n-k lost packets among the k transmitted packets, thanks to the n-k redundancy packets. The code rate can be determined according to the measured packet error rate before correction. Such ECC is more powerful than an XOR based FEC for error correction.

With a fixed FEC window of size k, the maximum transmission latency increases when the FEC code rate decreases, i.e., when n increases and when more redundancy packets are generated and transmitted. The maximum transmission latency decreases when the FEC code rate increases, i.e., when n decreases and when less redundancy packets are generated and transmitted.

Therefore with such advanced FEC-based ECC, there are two ways of reducing the maximum transmission latency: either by reducing the FEC window k while keeping the same number of redundancy packets as for a XOR based FEC, or by decreasing the number of redundancy packets.

The Automatic Repeat reQuest (ARQ) method is another ECC for data transmission that makes use of acknowledgment and/or negative acknowledgment messages, and timeouts to achieve reliable data transmission. This type of error correction method is well adapted to situations in which errors occur in bursts.

Figure 3b illustrates an ARQ-based error correction method at packet level. It illustrates the time at which an ordered sequence of data packets (comprising, for example, packet P2 (312)) is transmitted by the transport layer of a transmitter node, the time at which the same data packets (one of them being, for example, packet P2 (313)) are received by the transport layer of a receiver node, the time at which each acknowledgment (like ACK 314] is transmitted by the receiver node, and the time at which each acknowledgment (like ACK 315] is received by the transmitter node.

The nominal packet transmission latency Lois illustrated by the position ofthe references 312 (at the transmitter side] and 313 (at the receiver side] of packet P2. The time required to generate and to transmit an acknowledgment is considered to be the same value Lo. Let us consider Lo = 4ms, and a constant packet transmission rate with an interval TP between packet transmissions equal to 1ms (one packet transmitted per millisecond]. In this example, considering an acknowledgment window Wack = N (with N=4 in Figure 3b], an acknowledgment message ACK is then transmitted every N received packet and contains the acknowledgment status of the said N received packets. This condition may be completed by a timer that triggers the acknowledgment when at least one ofthe N packet is not received. As a reminder, an acknowledgement window is also entitled ‘Flock acknowledgment” in the prior art. Figure 3b illustrates an error transmission of packet Pl referenced 311 at the transmitter side which is not received by the receiver. The receiver can detect such error by analyzing a packet sequence number inserted in each packet header. The notification of missing packets is sent by the receiver through an acknowledgment message ACK 314. The reception of this message by the transmitter node is illustrated with the reference 315. After analyzing the content of this message, the transmitter resends Pl through the packet reference 316, and its reception is illustrated by the packet reference 317. The additional latency introduced by the ARQ method is 2*Lo + Wack* TP. The maximum transmission latency for a link is 3*Lo + Wack * TP. The more the ARQ window increases, the more the latency increases. Since for low latency systems, packets are acknowledged immediately (e.g. Wack = 2 or in the best case Wack = 1 if packet arrival time is accurate and if a negative acknowledgment can be generated after a very short timeout condition when a packet is missing], then the approximation of the maximum transmission latency for a link is 3 * Lo + TP. As a consequence, ARQ-based error correction methods are not suitable when Lo is high, since the RTT (which equals 2*Lo) for ACK transmission and packet retransmission becomes penalizing.

One advantage of certain embodiments of the invention is to determine a path correction scheme (PC] composed of (possibly different] transport layer error corrections applied on each link of the path. Considering a communication path composed of N links, and M available ECCs, one path correction scheme among NM possibilities is to be selected. In the following, we are studying the path correction schemes that can be applied on a path composed of two links (for example using the topology illustrated in Figure la), and two ECCs: FEC and ARQ. However, the method is still valid for more complex cases.

The possible path correction schemes are the following, the first ECC being applied on a first link, the second on the second link of the path different from the firstlink: {(FEC, FEC), (FEC, ARQ), (ARQ, FEC), (ARQ, ARQ)}.

The maximum transmission latency on a link configured to apply FEC is Lo + Wfec * TP. The more the FEC window size increases, the more the latency increases. The FEC window size is set according to the Packet Error Rate (PER) of the link on which the correction is applied. Assuming no burst of errors, the minimum and optimal value regarding bandwidth consumption is: Wfec = 1/PER, and the maximum transmission latency on a link configured to apply FEC becomes Lo + (Tp / PER). The maximum transmission latency on a link configured to apply the ARQ method with immediate packet acknowledgment is 3 * Lo + TP.

Let us consider PERI (respectively PER2), the packet error rate measured on the first (respectively second) link. The respective maximum transmission latencies are: (FEC, FEC): Lff = 2 * Lo + (TP / PERI) + (TP / PER2) (FEC, ARQ): Lfa = 4 * Lo + TP * (1+ 1 / PERI) (ARQ, FEC): Laf = 4 * Lo + TP * (1+ 1 / PER2)

(ARQ, ARQ): Laa = 6 * Lo + 2 * TP

Since a constraint to be met is to keep the data path latency lower than a predefined value Lmax, then the path correction schemes above are applicable if they respectively match the following equations:

a. (FEC, FEC): 1/PER1 +1/PER2 < (Lmax -2* Lo)/ TP b. (FEC, ARQ): PERI > TP /( Lmax -4* Lo - TP) c. (ARQ, FEC): PER2 > Tp/( Lmax -4* Lo - TP) d. (ARQ, ARQ): 6* Lo + 2 * TP < Lmax

Figure 4 illustrates a graphical view of those equations. Abscissa axis 400 holds the PERI values, and ordinate axis 401 the PER2 values.

Curve 405 is relative to Equation a, corresponding to the application of a FEC-FEC path correction scheme, and meaning that such path correction scheme is suitable for all pairs of points (PERI, PER2) located above the curve 405, i.e. in areas 412,411, and 408.

Line 404 is relative to Equation b, corresponding to the application of a FEC-ARQ path correction scheme, and meaning that such configuration is suitable for all pairs of points (PERI, PER2) located on the right of the line 404, i.e. areas 407, 408, 410, and 411.

Line 403 is relative to Equation c, corresponding to the application of an ARQ-FEC path correction scheme, and meaning that such configuration is suitable for all pairs of points (PERI, PER2) located above the line 403, i.e. areas 409,410,411, and 412.

Equation c only depends on Lo, but not on either PERI nor on PER2. Thus, the ARQ-ARQ path correction scheme is relevant for all or none of the areas.

For the cases given by Equations a, b and c, the graph illustrates which path correction schemes are suitable, based on the values of PERI and PER2.

Figure 5a is a flow chart of a segment of the program stored in the ROM 202 of a device controlling a communication path according to the invention. This algorithm is executed by a node playing the role of a master node (so a node that controls the communication path), but it is not necessarily a node within the communication path. The present algorithm concerns the generation of a path correction scheme defined by selecting, for each link of the communication path, an ECC from among a plurality of ECCs, while complying with a maximal end-to-end path latency constraint. In a particular embodiment an error correction code to decrease the packet error rate of said link below an acceptable threshold (ideally zero or close to zero), while complying with a maximal end-to-end path latency constraint may be determined.

Step 5000 corresponds to the initialization phase of the system including node discovery, node association, discovery or obtaining of the path from the source node to the destination node, and obtaining a maximum latency to comply with.

Step 5100 corresponds to the verification of communication conditions over the various links along the path in order to determine if a TLEC is necessary or not, and to adjust the application data rate if possible. According to another embodiment, obtaining a new path correction scheme maybe launched after a predetermined interval of time.

In step 5200, a path correction scheme is determined by selecting, for each link of the communication path, one ECC adapted to the status of said link, the selection being further based on the comparison of a PC maximum latency value, defined by the sum of the maximum latencies of the selected ECCs, with the maximum latency value that is to be complied with. In the following, the status of a link corresponds to an error rate or to the detection of error bursts.

Step 5300 corresponds to the application of the path correction scheme determined at step 5200.

Figure 5b is a refinement of the flow chart of Figure 5a. It illustrates an algorithm executed by a device controlling a communication path according to the invention. This algorithm is executed by a node playing the role of a master node, but it is not necessarily a node within the communication path. The present algorithm concerns the generation of a path correction scheme defined by selecting, for each link of the communication path, an ECC from among a plurality of ECCs, while complying with a maximal end-to-end path latency constraint.

Step 5000 corresponds to the initialization phase of the system including node association, discovery or obtaining of the path from the source node to the destination node (for example, as described in the IEEE 802.11η standard), and obtaining a maximum latency to comply with. The maximum latency value is predetermined at the conception of the device 200, and stored in a memory of the device (202, 203). Alternatively, the maximum latency value corresponds to an application parameter that can be set by a user, e.g., at start-up. Then the master node sends a message to a source node that starts transmitting data packets with a combination of transmission rate and size of packets defined to sustain an application data rate. As a result, intermediate nodes of the path receive and transmit packets up to the destination node.

Step 5100 corresponds to the verification of communication conditions over the various links along the path in order to determine if a TLEC is necessary or not, and to adjust the application data rate if possible.

At step 5110, the master node obtains packet error rate values measured for each link of the communication path. These values do not result from the application of a particular ECC implemented at the transport layer, but may correspond, for example, to a PER at the output of MAC layer. Packet error rates are measured by all nodes receiving packets, i.e., by all nodes of the communication path with packet processing at the transport layer, except the source node. A packet error rate corresponds to the average ratio of missing packets among a predefined number of received packets. A missing packet is detected by a receiver node that analyzes the sequence number inserted by a transmitter node in each packet header. The measured packet error rate values are transmitted by the nodes receiving packets to the master node through a dedicated control message, at a regular pace. Each node can also report if the links present one or more error bursts, i.e. it reports the maximum number of consecutively lost packets among the received packets received over a predetermined burst window.

At step 5120, the master node checks if a new data rate (coding rate) has been applied in the system. This can occur, for example, when starting data transmission, but it can also occur if an application data rate adaptation is decided during the process illustrated by Figure 5b (steps 5350, 5150, 5370). If a new application data rate is applied, there may be a need for an error correction activation or adaptation. In addition, at step 5120, the master node compares the current PER values with previously stored PER values. In the case a variation of at least one PER value is detected, it means that the conditions of transmission for at least one link has changed and that there may be a need for an error correction activation or adaptation.

If one of these two conditions is true, then in step 5130 the master nodes determines a data path packet error rate (DP_PER). According to a first embodiment, DP_PER corresponds to the highest value among the received PERs. Alternatively, itmay correspond to the sum ofthe received PERs. Taking the example of figure la, if the node 102 performs video decoding, video processing and video reencoding before transmission, then there should be an acceptable threshold for the packet error rate on link 111 and an acceptable threshold for the packet error rate on link 112. The threshold is defined by the application requirement. It may be the same value for both links, and in that case, the DP_PER corresponds to the highest PER value. If the node 102 does not perform video decoding, then only the packet error rate measured at node 101 is relevant for the application. In that case, the DP_PER is estimated as the sum of PER on both links. The master node checks, in step 5130, whether the current DP_PER value is lower than a maximum acceptable DP_PER value (DP_PER_MAX). If not, the master node determines, in step 5200, a path correction scheme by selecting, for each link of the communication path, one ECC adapted to the status of said link, the selection being further based on the comparison of a PC maximum latency value, defined by the sum of the maximum latencies of the selected ECCs, with the maximum latency value to comply. Obtaining a PC consists in obtaining a PC stored in memory 202 or 203 that may be predetermined at the conception or at the start-up of the system. A possibility consists in applying FEC to each link of the communication path. A maximal latency is defined for each link, based on the maximum path latency, e.g., by dividing the maximum path latency value by the number of links along the communication path. Such maximal link latency value defines a maximum FEC window applicable for a link. Then, the FEC window for each link is adjusted, based on a PER value corresponding to the measured packet error rate for said link without correction at the transport layer. Such implementation offers the advantage to reduce the time and resource processing.

An alternative is illustrated at Figure 5c.

If, at step 5130, the DP_PER value is lower than the DP_PER_MAX value, steps 5140 and optionally 5150 are reached. The master node checks at step 5140 if the DP_PER is much lower than the DP_PER_MAX value. If yes, it means that any TLEC applied along the path can be deactivated (i.e., there is no need for an error correction) and that the transmission medium is under-loaded. As a result, the application data rate may be increased. Therefore, at step 5150, the master node sends a message to each node of the communication path to deactivate the ECCs, and the master node sends a rate control information to the source node. This rate control information will then be provided to the application layer of the source node to indicate it may increase its data rate. Finally, the process restarts at step 5110.

Step 5300 corresponds to the application of the PC determined at step 5200. A preferred embodiment is illustrated by steps 5310 to 5370.

At step 5310, the master node sends to each transmitting node, i.e. each node of the path except the destination node, the corresponding TLEC to apply. According to a particular embodiment illustrated by Figure la, the destination node also corresponds to the source node. If an FEC is selected as ECC for a given link, the corresponding FEC window size is also provided. Similarly, if an ARQ method is selected as ECC for a given link, the corresponding acknowledgment window size is also provided. A control message may be used by the master node to transmit the ECCs to apply.

At step 5320, the master node receives acknowledgement messages from nodes of the path, which confirm that the ECCs have been applied. At step 5330, the master node obtains packet error rate values measured for each link of the communication path. These values result from the application of TLECs at the transport layer. After the reception of the PERs, the master node determines a data path TLEC packet error rate (DP_TLEC_PER) similarly to the one computed at step 5110, except that this one is based on packet error rates measured after the application of a transport layer error correction. This DP_TLEC_PER value is compared, at step 5340, with the maximum allowed PER (same acceptable threshold as in step 5130). If the DP_TLEC_PER value is lower than the threshold, the ECC is efficient, and the master node then checks at step 5360 if the DP_TLEC_PER is much lower than the threshold. If the DP_TLEC_PER is not much lower than the threshold, it means that the applied error corrections are efficient and the whole process restarts at step 5100. If the DP_TLEC_PER is much lower than the threshold, the transmission medium is under loaded, and the application data rate may be increased. The master node sends a rate control information to the source node. This rate control information will then be provided to the application layer of the source node to indicate it may increase its data rate, (step 5370).

If, at step 5340, the DP_TLEC_PER value is higher than the threshold, the ECC is not efficient, since the transmission medium is over-loaded. Such situation occurs when the bandwidth is reduced due to channel noise: consequently, there is no margin to transmit redundancy data corresponding to the application of error correction codes. Therefore, at step 5350, the master node sends a message to each node of the communication path to deactivate the ECCs, and the master node sends a rate control information to the source node. This rate control information will then be provided to the application layer of the source node to indicate it shall decrease its data rate. After sending a request for data rate adaptation (steps 5350, 5370) the process restarts at step 5110.

Figure 5c is a flow chart illustrating an embodiment of step 5200 of Figures 5a and 5b in detail. At step 5210, a plurality of path correction schemes are determined. It is possible that all PCs are determined as options: let us consider a communication path composed of N links, and M error correction methods available, then, a total of NM PCs can be applied.

As a reminder, the path correction schemes and their corresponding PC maximum latency values that can be generated for a communication path composed of a first and second links using the FEC and ARQ methods are as follows: (FEC, FEC): Lff = 2 * Lo + (Tp / PERI) + (Tp / PER2) (FEC, ARQ): Lfa = 4 * Lo + TP * (1+ 1 / PERI) (ARQ, FEC): Laf = 4 * Lo + TP * (1+ 1 / PER2)

(ARQ, ARQ): Laa = 6 * Lo + 2 * TP with PERI (respectively PER2), the packet error rate measured on the first (respectively second) link before applying a correction at the transport level, and TP the interval between packet transmission. In other words, the maximum latency of a given path correction scheme corresponds to the sum of the maximum latencies of each link of the path correction scheme.

At step 5220, the master node determines, for each PC, if its PC maximum latency value is less than or equal to the maximum latency to be complied with. If there is no PC among the plurality that fits (so is less than or equal to) the maximum latency to be complied with, the maximum latency of at least one link of the communication path shall be decreased. The decrease of a link latency value can be obtained by decreasing the acknowledgment window size when ARQ is applied, or decreasing the FEC window size when FEC is applied. In a real-time systems, the minimum acknowledgment window size should be equal to 1, and in some cases the only solution consists in applying the FEC method as an ECC and in inserting additional FEC packets on links. As a matter of fact, the plurality of determined PCs at step 5210 were tending to obtain a null packet error rate over each link of the communication path, and inserting further FEC packets on a link corresponds to overprotecting the link.

At step 5230, a PC with at least one link applying FEC, or with at least one link applying ARQ and with an acknowledgment window size different from 1 is selected among the plurality. Optionally, the selected PC further corresponds to the one having the lowest maximum latency among the plurality. The FEC or acknowledgment window size of the at least one link is then reduced until the PC maximum latency matches the maximum latency constraint (Step 5250). Process then exits back to step 5300 illustrated by Figure 5a.

Alternatively, it is also possible to distribute the latency reduction among the different links of the communication path. It can be performed according to different performance criteria.

According to an embodiment, the same latency reduction coefficient is applied to all links, the advantage being to equally over protect each link. Let us consider Lk the latency obtained with an optimal FEC/ARQ window, for link k, with k=l to N, N being the total number of links over the communication path for which the maximum latency can be reduced, and Lmax the end-to-end latency to comply with, then the same corrective factor to apply to each latency is as follows: corrective factor = Pax , Z.k=iLk the FEC window Wfec(i) to apply to link i with FEC (l<i<N) is: and the acknowledgment window WarqO) to apply to link) with ARQ (l<j <N) is: T.T x-x fLjLmax _ \ 1

War^~ L°)p·

It shall be understood that the ECC may be different on each link. For instance some links are protected by an ECC based on FEC defined by a FEC window, while others are protected by an ECC based on ARQ defined by an ARQ window.

According to another embodiment, the latency reduction is applied by minimizing the bandwidth added by the insertion of redundancy data. This is particularly relevant when error correction is based on FEC. For XOR-based FEC, the additional bandwidth introduced per link is 1/ Wfec. Let us consider Xi the corrective factor to apply to latency for link i, with i=l to N, then Σί^ι Ιί·Χί = Lmax, and for each link i, Lo + WFEC(i). Tp = L£. xt.

Minimizing the bandwidth means to determine the set of corrective factor Xi in order to get 1 τ

Min -—) which also corresponds to Min (Σ^=ι—~—) This condition is obtained when x, =

Wfec (0 Li.xi-L0 i^rnax Ly -2222 and the FEC window size to apply for link i (i=l to N) equals WFEC(i) = —--. N.Li Tp

It can be noted that if Lt < , then xi > 1 and the associated FEC window size is greater than the optimal FEC window pER^· This may be acceptable if the resulting packet error rate after correction is below the acceptable threshold for the application.

Let us consider Lk the latency obtained with the optimal FEC window for link k (l<k<N). Since the objective is to reduce the packet error rate close to zero, the latency reduction minimizing the bandwidth for redundancy can be performed by the following algorithm: if , then the associated corrective factor xk = 1, else the set of remaining corrective factor Xi for the links with Li >

E™* is determined in order to get Min (Σ—-—) w 6 V wFEC J

Let us consider the topology of Figure la, assuming Lo = 4ms, TP= 1ms, a measured packet error rate (without TLEC) of 1/20 for link 111 and 1/24 for link 112, then the optimal FEC window is WFEc_i_oPtim = 19 and WFEc_2_oPtim = 23, leading to a maximum latency for link 111 equals to Li = 23ms and a maximum latency for link 112 equals to L2 = 27ms. Assuming that the end-to-end latency to be complied with Lmax equals 30ms, then: 30 - With a balanced latency reduction, the corrective factor equals — = 0.6, Wfecjl = 9 and

Wfec_2 = 12, - With a minimized bandwidth consumption, Wfecjl = Wfec_2 = 11.

Let us now consider a measured packet error rate (without TLEC) of 1/8 for link 111 and 1/22 for link 112, then the optimal FEC window size is Wfec 1 opt™ = 7 and Wfec 2 opt™ =21, leading to a maximum latency for link 111 equals to LI = 11ms and a maximum latency for link 112 equals to L2 = 25ms. Assuming that the end-to-end latency to comply Lmax equals 30ms, then: 30 - With a balanced latency reduction, the corrective factor equals — = 0.83, Wfecjl = 5 and 36

Wfec_2 = 16, - With a minimized bandwidth consumption, Wfec_i= 7, Wfec_2 = 15. (Lmax - Li - Lo).

Lastly, in order to avoid overloading a link with large amount of data redundancy, a minimum FEC window size may be defined with the rule to not set a FEC window below this threshold.

Back to step 5220 in Figure 5c, the master node determines, for each PC, if its PC maximum latency value is less than or equal to the maximum latency to be complied with. The test, which is applied on the plurality of PCs, results in the obtaining of at least one PC (but possibly a plurality of PCs) that comply with the maximal latency constraint.

If several PCs among the plurality fit the maximum latency to comply with, the master node selects one PC that fits the maximum latency. Optionally, it corresponds to the PC with the lowest maximum latency (step 5290).

Alternatively, the master node detects if at least one link of the communication path present at least one error burst (step 5260) over a predetermined burst window. An error burst occurs if a predetermined threshold of lost packets is exceeded among the received packets received over a predetermined burst window. According to a preferred embodiment, the predetermined threshold equals 2. In such a case, if the size of the burst window and the FEC window are equal, the ARQ method is better that FEC for those links, since FEC only allows recovery of one lost packet per FEC window. As a consequence, at step 5260, links of the communication path with at least one error burst are identified.

At step 5270, it is determined if, the at least one PC that comply with the maximal latency constraint apply the ARQ method on at least one link of the communication path with error bursts. Possibly, it is determined if the at least one PC that complies with the maximal latency constraint applies the ARQ method on each link of the communication path with at least one error burst. In case several PCs comply with the maximal latency constraint and apply the ARQ method on at least one link of the communication path with error bursts, the PC with the higher number of links with at least one error burst that are corrected with the ARQ method is selected. In the case several PCs correspond to this constraint, the one with the lowest maximum latency is selected.

Let us consider the architecture illustrated by Figure lb, with at least one error burst detected on links 132 and 133, but not on link 131. Let us consider that the following PCs comply with the maximal latency constraint: {(FEC, FEC, ARQ), (ARQ, FEC, ARQ), (FEC, ARQ, ARQ)}. By applying steps 5260, 5270 and 5280 of the algorithm illustrated by Figure 5c, the PC (FEC, ARQ, ARQ) is selected since it applies the ARQ method on all links with at least one error burst.

If at step 5260 no link with at least one error burst is detected, the PC (that complies with the maximal latency constraint and) with the lowest maximum latency is selected (step 5290). Similarly, if at step 5270 no PC (that complies with the maximal latency constraint and) applies the ARQ method on at least one link of the communication path with at least one error burst, the PC with the lowest maximum latency is selected (step 5290).

Previous paragraphs were concerning the determination (5200) and the launching of the application of PC (5300) by a master node. The following paragraphs are related to the process in step 5300 and concern the application of ECCs by nodes of the communication path transmitting data. According to an embodiment, nodes of the communication path with an ECC to apply apply the ECC without delay at the reception of the ECC parameters, or at the reception of a dedicated message from the master node. However, in that case, some data may be transmitted with an end-to-end latency above the maximum latency to comply. This configuration arises when the application of an ECC that generates an increase of maximum latency over a link is applied before the application of an ECC that generates a decrease of maximum latency over another link.

Let us consider the topology of Figure la with a maximal latency of 30ms, a first path correction scheme (PC) resulting in a maximum latency of 20ms on link 111 and a maximum latency of 10ms on link 112, and a second path correction scheme resulting in a maximum latency of 12ms on link 111 and 18ms on link 112. When switching from the first to the second configuration, if the ECC on link 112 is modified before the one of link 111, the path latency value may be temporary equal to 38ms. When switching from the first to the second configuration, if the ECC on link 111 is modified before the one of link 112, the intermediate node 102 may apply the second configuration ECC on link 112 only when all the data received through link 111 with a latency of 20ms is transmitted over link 112 with a maximum latency of 10ms. In the same manner, when switching from the second to the first configuration, the source node 101 may only apply the ECC when it is confirmed that node 102 can transmit data with a maximum latency of 10ms.

As a consequence, another embodiment concerns the application of a path correction scheme while complying with the maximal latency, even during the application step. This embodiment limits the risk of interruption of service at the application level. It is illustrated by Figures 6a, 6b, 7a, 7b and 7c.

Figure 6a illustrates a first application of a path correction scheme over a path with a topology similar to the one of Figure lb. The application of the path correction scheme leads to a modification of link latencies. In a first configuration, the maximum latencies are 10ms for link 131,15ms for link 132 and 15ms for link 133. In a second configuration, resulting from the application of a path correction scheme, the maximum latencies are 20ms for link 131, 10ms for link 132 and 10ms for link 133. The evolution of time is given by the timeline 600 and the intermediate times tO to t4.

The maximal latency to be complied with (between nodes 121 and 124) equals 40ms. Node 121 first receives a SWITCH_REQUEST message (not represented) from a master node, indicating to apply the path correction scheme, and as a consequence, to switch to the second configuration. The source node 121 compares the current latency of link 131 with a latency resulting from the application of an ECC on link 131. Since it leads to an increase of latency (from 10 to 20ms), the source node 121 does not immediately apply the ECC, but rather waits for that the other links, for which the application of an ECC may decrease their current latency, have applied their ECC.

At time to, the source node 121 sends a SWITCH_START message 601 to the first intermediate node 122. Said message is received by node 122 attime ti. When receivingthe SWITCH_START message 601, the intermediate node 122 waits until the end of the retransmission window for the data transmitted over link 132, and applies the ECC that leads to a decrease of latency over link 132 from 15ms to 10ms. Attime t2, the intermediate node 122 forwards the SWITCH_START message 601 to the next intermediate node 123. The behavior of node 123 is similar to the one of node 122.

At time t3, the intermediate node 123 forwards the SWITCH_START message 601 to the destination node 124. This latter node 124 acknowledges the reception of the SWITCH_START message 601 by sending an acknowledgment (ACK) message 602. This ACK message 602 is progressively forwarded by each intermediate node up to the source node 121. When receiving the ACK message 602, the source node infers that ECCs resulting in a decrease of latency have been applied. The source node 122 waits until the end of the retransmission window for the data transmitted over link 131, and then applies the ECC resulting in an increase of latency from 10 to 20ms over link 131.

At time U, the source node 121 sends a SWITCH_END message 603 to the first intermediate node 122, which is progressively forwarded by each intermediate node up to the destination node 124. Node 124 acknowledges the reception of the SWITCH_END message 603 by sending an acknowledgment (ACK) message 604. This ACK message 604 is progressively forwarded by each intermediate node up to the source node 121. When receiving the ACK message, the source node 121 infers that the application of the path correction scheme is completed.

Alternatively, the ACK messages 602 and 604 can be generated by the last intermediate node 123 instead of the destination node 124. The transmission of the SWITCH_END message 603 and its associated ACK signal 604 can be skipped since the ACK message 602 guarantees that all nodes except the source node have already switched to the new configuration. Furthermore, the transmission of the ACK messages 602 and 604 can be skipped when the source node is also the destination node.

In addition to the described messages, a node applying an ECC on a link can notify the receiver of this link about the change. It can be done through a dedicated control message or through information inserted in each transmitted packet header.

According to a further embodiment, the messages are not progressively forwarded by each node of the communication path, but the SWITCH_START, SWITCH_END and ACK messages only occur between nodes of the path and a master node of the network. In this embodiment, the master node sends the SWITCH_START message to the set of nodes that will reduce the maximum latency of a link. Once these nodes have all acknowledged the application of new ECC for their data transmission (ACK messages received by the master node), the master node sends the SWITCH_START message to other nodes along the path. Once these latter nodes have all acknowledged the application of new ECC for their data transmission, the master node may send the SWITCH_END message to all nodes along the path to indicate that switching operation is completed.

Figure 6b illustrates a second application of a path correction scheme over a path with a topology similar to the one of Figure lb.

In a third configuration, the maximum latencies are 15ms for link 131,10ms for link 132 and 15ms for link 133. In a fourth configuration, resulting from the application of a path correction scheme, the maximum latencies are 10ms for link 131, 20ms for link 132 and 10ms for link 133. The evolution of time is given by the timeline 600 and the intermediate times tio to ti4.

Node 121 first receives a SWITCH_REQUEST message (not represented) indicating to apply the path correction scheme, and as a consequence, to switch to the fourth configuration. The source node 121 compares the current latency of link 131 with a latency resulting from the application of an ECC on link 131. Since it leads to a decrease of latency (from 15 to 10ms), the source node 121 waits until end of the retransmission window for the data transmitted over link 131, and applies the ECC that leads to a decrease of latency over link 131.

Attime tio, node 121 sends a SWITCH_START message 611 to the first intermediate node 122. Said message is received by node 122 at time tn. The node 122 compares the current latency of link 133 with a latency resulting from the application of an ECC on link 132. Since it leads to an increase of latency, the node 122 directly forwards the SWITCH_START message 611 to the next intermediate node 123. The behavior of node 123 is similar to the one of node 121. At time ti2, the intermediate node 123 forwards the SWITCH_START message 611 to the destination node 124. This latter node 124 acknowledges the reception of the SWITCH_START message 611 by sending a specific acknowledgment (ACK) message 612. This ACK message 612 is progressively forwarded by each intermediate node up to the source node 121. When receiving the ACK message 612, the source node infers that ECCs resulting in a decrease of latency have been applied. At time ti3, the source node 121 sends a SWITCH_END message 613 to the first intermediate node 122.

When receiving the SWITCH_END message 613, the intermediate node 122 waits until the data received with at a latency of 15ms has been sent over link 132

Let us consider T1 the processing time of the intermediate node 122. The intermediate node applies the new configuration at a time Tswitch, when the value Tswitch respects the following constraint: Tswitch -tn > Tl. Then, the intermediate node 122 waits for the end of the retransmission window for the transmission of data over the link 132. Once these two conditions are fulfilled, the intermediate node 122 applies the ECC that results in the increase of the latency on link 132 (from 10 to 20ms). Then, the SWITCH_END message 613 is forwarded to the next intermediate node up to the destination node 124.

This latter node 124 acknowledges the reception of the SWITCH_END message 613 by sending an acknowledgment (ACK) message 614. This ACK message 614 is progressively forwarded by each intermediate node up to the source node 121.

Alternatively, the reception ofthe ACK message 612 by the intermediate node 122 can be used to directly trigger the switching operation at this intermediate node. The intermediate node 122 forwards the ACK message 612 once the ECC is applied. The complete application of the path correction scheme is inferred by the source node 121 through the reception ofthe ACK message 612. In such a case, the transmission of the SWITCH_END message 613 and its associated ACK message 614 can be skipped.

Figure 7a illustrates different types of protocol messages exchanged by nodes when applying a path correction scheme.

Fields 711, 712, 713 form a first type of protocol message generated by a receiver node, i.e., an intermediate node or destination node of the communication path, to report the measured packet error rate for up to two links. This message is destined to the master node controlling the communication path. The case of two receiving links is illustrated by node 162 in Figure Id. The periodicity of transmission is predefined, for instance every 100ms. There may be two different types of such message: one for the packet error rate measured before applying an ECC, i.e., without TLEC (which is considered by the master node at Step 5110), and one for the packet error rate measured after applying an ECC, i.e., with TLEC (which is considered by the master node at Step 5330). With this information, the master node is able to provide an ECC adapted to the link, while minimizing the packet error rate. The "Msg Type” field 711 indicates the type of message, the field "PERI” 712 is a value representative of the measured packet error rate for a first receiving link, and the field "PER2” 713 is representative of the measured packet error rate for a second receiving link. Each field may be 8-bit wide. Fields 712 and 713 can be extended to indicate the presence of bursts of missing packets.

Fields 721, 722, 723, 724 and 725 form a second type of protocol message generated by the master node to send the ECCs to apply for up to two links. This message is destined to a node involved in the transmission of application data along the path, i.e., the source node or an intermediate node. The case of two transmission links is illustrated by node 162 in Figure Id. This type of message is sent only when a new configuration shall be applied. The "Msg Type” field 721 indicates the type of message, the field "ECI type” 722 indicates the type of ECC to apply, e.g., ARQ or FEC, for the first transmission link, the field "ECI window” 723 indicates the retransmission or acknowledgment window size for the first transmission link, and the fields "EC2 type” 724 and "EC2 window” 725 are equivalent to the fields 722, 723 for the second transmission link. Fields 721, 723, 725 may be 8-bit wide, and fields 722, 724 may be 2-bit wide.

Fields 731, 732, 733, form a third type of protocol message generated by a node transmitting application data along the path, i.e., the source node or an intermediate node. This message is destined to the next node receiving the application data in the path. This type of message is used to describe the currently applied ECC. The "Msg Type” field 731 indicates the type of message, the field "EC type” 732 indicates the type of applied ECC, e.g., ARQ or FEC, the field "EC window” 733 indicates the associated retransmission or acknowledgment window size. Fields 731, 733, may be 8-bit wide, and field 732 may be 2-bit wide.

Several other types of protocol message can be formed by only one field "Msg Type” 741. It is the case of: - the "SWITCH REQUEST” message generated by the master node. It is used to trigger the application of a path correction scheme. - the "SWITCH_START” message generated by the source node that initiates the application of the PC, and then relayed by the intermediate nodes. It is used to indicate the beginning of a switching operation. - the "SWITCH_END” message generated by the source node that initiates the application of the PC, and then relayed by the intermediate nodes. It is used to indicate the completion of a switching operation. - the acknowledgment of "SWITCH_START” message generated by the destination node or the last intermediate node, and then relayed by other nodes up to the source node. - the acknowledgment of "SWITCH_END” message generated by the destination node or the last intermediate node, and then relayed by other nodes up to the source node. - the "DEACTIVATE_ECC” message generated by the master node and requesting a node transmitting data to deactivate the application of ECC. - The "RATE_CONTROL_INCREASE” message generated by the master node and allowing a source node to increase the application data rate. - The "RATE_CONTROL_DECREASE” message generated by the master node and requesting a source node to decrease the application data rate.

Fields 751, 752, 753, 754, 755 and 756 form a combination of signaling information that can be used in the particular case of Figure la. These fields can be inserted in the packet header of each transmitted packet. Using these fields prevents from using all the protocol messages previously described. The advantage to concatenate these information with packet payload is to reduce the protocol overhead. Moreover, the transmission is reliable (multiple transmission of same information) as the information is transmitted within each packet.

The "Switch” field 751 indicates if the application of a path correction scheme is currently in progress. It may be 1 bit-wide with value "1” when the operation is ongoing and back to "0” when it is completed. It is filled by both nodes 101 and 102: first by the master node (e.g. node 101) in charge of controlling the system, and then by the slave node (e.g. node 102) for acknowledgment. The field "EC type Tx” 752 indicates the type of ECC being applied, i.e., ARQ or FEC, and the field "EC window” 753 indicates the associated retransmission or acknowledgement window size. Fields 752 and 753 are filled by both nodes 101 and 102 to describe the ECC applied over the transmission link. The field "PER” 754 is a value representative of the measured packet error rate when receiving data packets. It is filled by the slave node (e.g. node 102) to provide the reception link status to the master node (e.g. node 101). The field "EC type Rx” 755 indicates the type of ECC to apply, i.e., ARQ or FEC, on the reception link and the field "EC window” 756 indicates the associated retransmission or acknowledgement window size. Fields 755 and 756 are filled by the master node to request the slave node to apply the described ECC for its transmission link. Fields 753, 754, 756 maybe 8-bit wide, and fields 752, 755 maybe 2-bit wide.

Figure 7b illustrates the progress of the application of a path correction scheme over a path the topology of which is similar to Figure la.

Fields 761, 762, 763, 764, 765, 766 are equivalent to the fields 751, 752, 753, 754, 755, 756 of Figure 7a. They are filled by the node 101 and are inserted in each data packet transmitted by node 101. Fields 771, 772, 773, 774, 775, 776 are equivalent to the fields 751, 752, 753, 754, 755, 756 of Figure 7a. They are filled by the node 102 and are inserted in each data packet transmitted by node 102. Timeline 700 illustrates the progress of the application of the path.

Initially, both nodes transmit data packets without ECC applied at the transport level, and measure the packet error rate related to the received packets.

At time to, the node 102 sends to the node 101 a message 780 that contains an update of the field PER 774 with the measured packet error rate (it supposed to be an average value of 1/25). By combining this information with its own packet error rate measurement, the node 101, which is the master node, selects appropriate ECCs for both links 111 and 112.

At time ti, the node 101 sends to the node 102 a message 781 that contains an update of the fields 761,762, 763, 765 and 766. They indicate the start of the application of a PC (bit Switch = 1), the use of the ARQ method by the node 101 over the link 111 (EC type Tx = ARQ and EC window Tx = 1), and a request destined to node 102 to use FEC over the link 112 (EC type Rx = FEC and EC window Rx = 15).

At time t2, the node 102 sends to node 101 a message 782 that contains an update of the fields 771, 772 and 773: the node 102 acknowledges the start ofthe operation and applies the ECC described in fields 772 and 773 (EC type Tx = FEC and EC window Tx = 15).

At time t3, the node 101 sends to node 102 a message 782 that contains an update of the field 761 (bit Switch returns to value 0). It notifies the completion of the application of the PC which is acknowledged by node 102 at time t4 via the message 784 that contains an update of field 771 (bit Switch returns to value 0).

Figure 7c illustrates the progress of a second application of a path correction scheme over a path the topology of which is similar to Figure la. More precisely, the Figure illustrates the switch from a first PC to a second PC.

Fields 761 to 766 and 771 to 776 are equivalent to the fields 751 to 756 of Figure 7a. Attime tio, the fields 761 to 766 and 771 to 776 are equal to the fields at time t3 and U of Figure 7b. The maximum end-to-end latency is equal to 30ms, and each link gets a latency of 15ms. The node 101 initially detects a variation of the PER on link 112 which leads to the selection of new ECC to apply for link 111 (FEC with a transmission window of 12 packets), and link 112 (FEC with a transmission window of 18 packets). The new latencies are supposed to be equal to 12ms for link 111 and 18ms for link 112.

At time tii, the source node 101 sends to node 102 a message 791 that contains an update of the fields 761, 762, 763, 765 and 766. It indicates the start of the switching operation (bit Switch = 1), the use of FEC by the node 101 over the link 111 (EC type Tx = FEC and EC window Tx = 12), a request destined to the node 102 to apply FEC (EC type Rx = FEC and EC window Rx = 18). Since the link latency of link 111 should decrease (from 15 to 12ms) when applying the new ECC, the new ECC is applied by node 101 at the same time the message 791 is transmitted.

At time ti2, the node 102 sends to node 101 a message 792 that contains an update ofthe field 771 only. The node 102 acknowledges the start of switching operation (bit Switch = 1). Since the latency for link 112 is increasing (from 15 to 18ms), the new ECC is not immediately applied by node 102. As a matter of fact, this node has to wait that all application data received with a link latency of 15ms have been processed, and transmitted with a link latency of 15ms.

At time ti3, the node 101 sends to node 102 a message 793 that contains an update ofthe field 761. Such update (bit Switch set from 1 to 0) corresponds to the fact that node 101 has completed switch operation and is waiting for confirmation of completion from node 102.

Starting at time tii, the node 102 has to wait for a time corresponding to the processing time T plus the time corresponding to the end of the current FEC window before applying the new ECC. At time ti4, when these conditions are fulfilled, the node 102 applies the new ECC given by fields 772 and 773 (EC type Tx = FEC and EC window Tx = 18), and acknowledges the application of the new path correction scheme by sending a message 794 to node 101 that contains an update of the field 771 (bit Switch set from 1 to 0).

Figure 8 is a flow-chart illustrating an algorithm implemented by the source node according to the invention. State 800 corresponds to the initialization. Then, the source node goes to state 801 and starts transmitting application data with a combination of transmission rate and size of packets determined to sustain the application data rate.

At state 801, if the source node receives a new ECC to apply (that may be sent by the master node at Step 5310), it stores these information, acknowledges the configuration reception in state 802 and returns to state 801. When a "DEACTIVATE_ECC”, or "RATE_CONTROL_INCREASE", or "RATE_CONTROL_DECREASE” is received, the corresponding operation is applied immediately by the source node. When a SWICH_REQUEST message is received from the master node, the source node goes to step 803 to check for the evolution of the latency of the link over which it sends data.

The source node compares the latency of said link with the latency resulting in the application of the ECC. If the application of the ECC results in an increase of the link latency, the source node does not directly apply the ECC, but only sends a SWITCH_START message to the node immediately following it, e.g., the first intermediate node (State 804). With the reception of an acknowledgment of the "SWITCH_START” message, the source node can infer that all nodes of the path that should have applied an ECC resulting in a decrease of latency have correctly applied the ECCs. After having received the acknowledgment, the source node waits for the end of the current retransmission window (if necessary) and goes to the state 805. At state 805, the source node applies the new ECC, and sends to the node immediately following it, data related to the new applied ECC and a SWITCH_END message. Once the SWITH_END message is acknowledged, the source node returns to state 801.

Back to state 803, if the application of the ECC results in a decrease of the link latency, the source node waits for the end of the current retransmission window (if necessary) and goes to the state 806. At this state, the source node applies the new ECC, and sends to the immediately following it, data related to the new applied ECC and a SWITCH_START message. Once the SWITH_START message is acknowledged, the source node goes to state 807 to send a SWITCH_END message to the node immediately following it After reception of acknowledgment of SWITCH_END message, the source node returns to state 801.

Optionally, the sending of the SWITCH_END message can be skipped. Then, the source node directly returns to state 801 after the application of a new ECC in state 806 or in state 805.

Figure 9 is a flow-chart illustrating an algorithm implemented by an intermediate node according to the invention. Let us consider the topology of Figure Id, and assume that the intermediate node 162 is also performing data processing. Then, this finite state machine shall be concurrently executed by two processes in intermediate node 162: a first process is in charge of controlling reception through the link 171 and transmission through the link 172, and a second one is in charge of controlling reception through the link 173 and transmission through the link 174.

For the first process, we define the node 161 as the node immediately preceding the intermediate node 162, and the node 163 as the node immediately following it. For the second process, we define the node 163 as the node immediately preceding the intermediate node 162, and the node 161 as the node immediately following it.

Step 900 corresponds to the initialization. Then, the intermediate node goes to state 901 to start receiving and transmitting application data. In this state, the intermediate node performs packet error rate measurements (without and with TLEC) over the concerned reception link. The measurement is transmitted to the master node at a regular pace, and it is used to compute the appropriate path correction scheme. As a reminder, the packet error rate without TLEC is used at Step 5110 to determine if a new PC should be applied, at Step 5210 to determine the latency of each PC. The packet error rate with TLEC is used at step 5330 to determine if the coding rate of the application should be increased or decreased.

In state 901, if the intermediate node receives a new ECC to be applied, stores these information, acknowledges the configuration reception in state 902 and returns to state 901. When a "DEACTIVATE_ECC” is received, the corresponding operation is applied immediately by the intermediate node. If a SWICH_START message is received from the node immediately preceding said intermediate node in the communication path, the intermediate node goes to step 903 to check for the evolution of the latency of the link over which it sends data, i.e., the transmission link.

The intermediate node compares the latency of said link with the latency resulting from the application of the new ECC. If the application of the ECC results in an increase of the link latency, the intermediate node goes in state 904 to forward the SWITCH_START message to the node immediately following it in the transmission path. When an acknowledgment of the SWITCH_START message is received, the intermediate node goes to the state 905 to forward this message to the node immediately preceding it, and goes back to State 904. After reception of a SWITCH_END message, the intermediate node waits for the end of the transmission of processed data received since the reception of SWITCH_START message. Then, it waits for the end of the current retransmission window (if necessary) and goes to the state 906. In state 906, the intermediate node applies the new ECC, sends to the node immediately following it data related to the new applied ECC, and forwards the SWITCH_END message. When an acknowledgment of the SWITCH_END ACK message is received, the intermediate node goes to the state 907 to forward this message to the node immediately preceding it, and then it returns to state 901.

Back to state 903, if the application of the ECC results in a decrease of the link latency, the intermediate node waits for the end of the current retransmission window (if necessary) and goes to the state 906. In this state, the intermediate node applies the new ECC, sends to the node immediately following it data related to the new applied ECC, and forwards the SWITCH_START message to the node immediately following it Once the SWITCH_END message is acknowledged, the intermediate node forwards the SWITCH_END message in the state 907, and then returns to the state 901.

Optionally, the sending of the SWITCH_END message can be skipped. Then, the transition from state 904 to state 906 is performed at the reception of the SWITCH_START ACK message and this message is forwarded in state 906. Consequently, states 905 and 907 are no more required.

Figure 10 is a flow-chart illustrating an algorithm implemented by a destination node according to the invention. Step 1000 corresponds to the initialization. Then, the destination node goes to state 1001 to start receiving application data. In this state, the destination node performs packet error rate measurements (without and with ECC) for the concerned reception link. The measurement is transmitted to the master node at a regular pace, and it is used to compute the appropriate path correction scheme. As a reminder, the packet error rate without TLEC is used at Step 5110 to determine if a new PC should be applied, at Step 5210 to determine the latency of each PC. The packet error rate with TLEC is used at step 5330 to determine if the coding rate of the application should be increased or decreased.

When a SWICH_START message is received from the node immediately preceding it in the communication path, the destination node sends an acknowledgment (Step 1002). When the SWICH_END message is received from the node immediately preceding it in the communication path, the destination node sends an acknowledgment to the node immediately preceding it (Step 1003). Then, it returns to the state 1001.

Optionally, the sending of the SWITCH_END message can be skipped. Then the destination node directly returns to state 1001 after the state 1002.

In the particular case where the source node is also the destination node, this finite state machine is not implemented. With that particular topology, in the state 801 of the finite state machine of Figure 8, the source node also measures the packet error rate of the reception link. The measurement is transmitted to the master node (when it is different from the source node) at a regular pace, and it is used to compute the appropriate system configuration.

Although the present invention has been described hereinabove with reference to specific embodiments, the present invention is not limited to the specific embodiments, and modifications will be apparent to a skilled person in the art which lie within the scope of the present invention.

Many further modifications and variations will suggest themselves to those versed in the art upon making reference to the foregoing illustrative embodiments, which are given by way of example only and which are not intended to limit the scope of the invention, that being determined solely by the appended claims. In particular the different features from different embodiments may be interchanged, where appropriate.

In the claims, the word "comprising” does not exclude other elements or steps, and the indefinite article "a” or "an” does not exclude a plurality. The mere fact that different features are recited in mutually different dependent claims does not indicate that a combination of these features cannot be advantageously used.

Claims (24)

1. A method for controlling transmission of a data stream, the method comprising, at a master node: obtaining a maximum latency value, wherein the maximum latency value is to be complied with while transmitting the data stream from a source node to a destination node over a communication path comprising a plurality of links, a link having a status; obtaining a Path Correction scheme (PC] defined by selecting, for each link of the communication path, an Error Correction Code (ECC] from among a plurality of ECCs, an ECC imposing a latency, wherein the selecting of an ECC is adapted to the status of said link, and depends on a comparison between a PC latency value, defined by a total latency of the selected ECCs, and the obtained maximum latency value; and, launching the application of the PC.

2. A method according to Claim 1, wherein the communication path comprises at least at first and second links, wherein the ECC applied to the first link differs from the ECC applied to the second link.

3. A method according to claim 2, wherein a different type of ECC is applied to the first link and the second link.

4. A method according to claim 2, wherein the ECC applied to the first link and the second link is defined by a window size and wherein the window size of the ECC applied to the first link differs from the window size of the ECC applied to the second link.

5. A method according to Claim 1, wherein the status is an error rate.

6. A method according to claim 5, wherein the ECC is defined by a code rate, wherein the code rate is determined so as to correct a number of errors determined by the error rate, wherein selecting an ECC comprises adapting the code rate such that the PC latency value complies with the maximum latency value.

7. A method according to claim 6, wherein the ECC is defined by a window size, and wherein the window size is determined so as to correct a number of errors determined by the error rate.

8. A method according to Claim 7, wherein the ECC is defined by a window size greater than 1, and wherein selecting an ECC comprises reducing the window size such that the PC latency value complies with the maximum latency value.

9. A method according to Claim 8, wherein an ECC is selected for a plurality of links, and wherein each link of the plurality equally applies the reducing step.

10. A method according to Claim 8, wherein the reduction step is based on a minimal increase of bandwidth along the communication path.

11. A method according to one of the preceding Claims wherein obtaining a PC comprises determining a plurality of different PCs; and, selecting a PC among the plurality of different PCs.

12. A method according to Claim 11 wherein selecting a PC comprises obtaining data indicating that at least one link of the communication path gets at least one error burst, selecting at least one PC among the plurality of PCs comprising the higher number of links with at least one error burst corrected by an ARQ method.

13. A method according to Claim 12 wherein selecting a PC further comprises selecting the path correction scheme having the minimum latency value among the plurality of different path correction schemes.

14. A method according to Claim 1, further comprising, prior to obtaining a PC, obtaining a non-corrected transport layer error rate for each link of the communication path; determining a path error rate based on the obtained error rates; comparing the path error rate with a predetermined value; and, in response to the comparing step, adapting application data rate of the data stream.

15. A method according to Claim 1, further comprising: obtaining a corrected transport layer error rate for each link of the communication path; determining a path error rate based on the obtained error rates; comparing the path error rate with a predetermined value; and, in response to the comparing step, adapting application data rate of the data stream.

16. A method according to Claim 14 or 15 wherein determining a path error rate comprises selecting the highest error rate among the obtained error rates.

17. A method according to Claim 14 or 15 wherein determining a path error rate comprises determining the sum of the obtained error rates.

18. A method according to Claim 14 or 15, wherein the adapting step comprises increasing application data rate of the data stream.

19. A method according to Claim 14 or 15, further comprising, deactivating any ECC applied on each link of the communication path and decreasing application data rate of the data stream.

20. A method according to Claim 18 in combination with Claim 14, further comprising, deactivating any ECC applied on each link of the communication path.

21. A method according to Claim 1 wherein the launching step comprises sending error correction methods of the selected path correction scheme to nodes of the path; and, sending a message to the source node indicating to apply the selected path correction scheme.

22. A system for controlling transmission of a data stream, comprising: a module configured for obtaining a maximum latency value, wherein the maximum latency value is to be complied with while transmitting the data stream from a source node to a destination node over a communication path comprising a plurality of links, a link having a status; a module configured for obtaining a Path Correction scheme (PC] defined by selecting, for each link of the communication path, an Error Correction Code (ECC] from among a plurality ofECCs, an ECC imposing a latency, wherein the selecting of an ECC is adapted to the status of said link, and depends on a comparison between a PC latency value, defined by a total latency of the selected ECCs, and the obtained maximum latency value; and, a module configured for launching the application of the PC.

23. A computer program which on execution by a programmable node causes the node to execute the method of claim 1.

24. A non-transitory computer-readable medium storing a program which, when executed by a microprocessor or computer system in a system, causes the system to perform the method of Claim 1.