GB2545177A

GB2545177A - Automatic calibration of a DC current detecting circuit

Info

Publication number: GB2545177A
Application number: GB1521506.4A
Authority: GB
Inventors: Smith Lee; O'brien Donal; Ryan Enda
Original assignee: Shakira Ltd
Current assignee: Shakira Ltd
Priority date: 2015-12-07
Filing date: 2015-12-07
Publication date: 2017-06-14
Anticipated expiration: 2035-12-07
Also published as: GB201521506D0; GB2545177B

Abstract

Calibration circuit for use in e.g. an RCD device comprises a further winding W3 on the ferromagnetic core 10 of the current transformer of a DC detector, through which a primary winding L1 (such as that carrying current to a load to be protected) passes. In embodiments, the calibration occurs when the load is disconnected via open contacts, such that the vector sum of DC current(s) flowing in the primary is zero (though can be any predetermined amount). An oscillating signal from oscillator 12 is applied across a secondary winding W1a, W1b and means 14, C1, Tr1, Tr2, R1, C2 are provided for detecting a DC offset. During calibration, a voltage is established across the further winding W3 and there are means 20 for adjusting the voltage until the DC offset equals a predetermined value. The oscillator frequency may be an order of magnitude higher than mains supply.

Description

Automatic Calibration of a DC Current Detecting Circuit

This invention relates to a circuit for auto-calibrating a DC current detecting circuit.

It is often desirable to detect and measure DC currents in circuits or installations. Detection of DC currents is often achieved by the use of a shunt. Shunts have to be inserted in the circuit being monitored and this involves direct contact with the DC supply. In many cases direct contact with the circuit being monitored is undesirable or even impractical. Hall Effect devices are also commonly used for detection of DC currents, but these tend to be bulky and expensive.

Current transformers (CTs) are not normally used to detect DC currents because CTs are only responsive to alternating currents and are not inherently responsive to a steady state current. However, current transformers have the advantage of being compact and inexpensive, and would be an attractive means for achieving contactless detection of DC currents if the above technical problem could be overcome. US8975890 (WA/49) describes various embodiments of DC current detecting and measuring circuits using a current transformer. Figure 1 of the present specification is a reproduction of Figure 3 of US8975890 (WA/49).

In Figure 1 two secondary windings Wla, Wlb are wound separately on a ferromagnetic toroidal core 10, and a capacitor Cl is connected in series between the secondary windings. It will be understood that in the present Figure 1 the core 10 is shown schematically, in the same manner as it is shown in Figure 3 US8975890 (WA/49). A primary conductor LI passes through the aperture of the toroidal core. An oscillator 12 is supplied with a 15V supply from Vcc to ground. The oscillator 12, the two windings Wla, Wlb and the capacitor Cl form a loop or a first circuit for current flow from Vcc to ground. The oscillator current as represented by H+ and H- will flow back and forth through Wla, Cl and Wlb at the oscillator frequency F which, as mentioned in US8975890 (WA/49), will typically be substantially higher than the normal mains supply frequency of 50Hz, for example about 3KHz.

During the positive half cycles Vcc will be distributed approximately as 15V, 7.5V, 7.5V and OV at points 1, 2, 3 and 4 respectively, and during the negative half cycles Vcc will be distributed approximately as OV, 7.5V, 7.5V and 15V at points 1, 2, 3 and 4 respectively. So, whilst points 1 and 4 will swing fully between 15V and ground, the voltages at points 2 and 3 will remain relatively stable at 7.5V. In the absence of any DC current flow in the primary conductor LI the DC current through the secondary windings and the DC voltage across Cl will be substantially zero. When a DC current +ldc or -Idc flows in the primary conductor LI a resultant DC shift as shown in Figure 2c or 2d of US8975890 (WA/49) will occur and the current in the oscillator circuit will now have a DC offset with the result that the voltages at points 2 and 3 will no longer be the same. The resultant differential voltage at those points can be used to control rectifying means (bipolar transistors Trl, Tr2 in the present embodiment) and so detect the DC current in the primary conductor LI.

To this end, a second circuit to ground is formed by the bipolartransistorsTrl and Tr2, a resistor R1 and a further capacitor C2. When a DC current Idc flows in the primary conductor LI the difference in the DC voltage between points 2 and 3 will increase proportionately. When Idc is of a certain polarity and of sufficient magnitude, corresponding to a DC offset greater than a pre-determined magnitude, point 2 will reach approximately 0.7V higher than point 3 during the oscillator cycles and transistor TR2 will start to conduct. This will allow the DC current to flow to ground via resistor R1 and develop a voltage across R1 and capacitor C2 will charge up to a certain voltage

Vout. When Idc is of the same magnitude but of opposite polarity point 3 will reach approximately 0.7V higher than point 2 during the oscillator cycles and transistor TR1 will conduct. The oscillator current will again flow to ground via resistor R1 and develop a voltage Vout across C2. Thus a DC voltage will be developed across C2 which will be proportional to the DC current flowing in LI and, therefore, to a predetermined magnitude of DC offset in the oscillator circuit.

In the arrangement of Figure 1 the transistors Trl and Tr2 are used to "siphon off" the DC component in the oscillator current by way of a rectifying action so as to detect a DC current flow in the primary conductor, the capacitor Cl allowing the high frequency current produced by the oscillator 12 to bypass the transistors. To this end, Trl and Tr2 are used as current control means to control the current flow into C2.

If there is a DC current in LI, the voltage across Cl will always reach a level where Trl starts conducting independent of the magnitude of the current and the value of Cl.

The small capacitor Cl is intended to absorb the AC ripple current, typically at 3KHz, produced by the oscillator 12. The ripple voltage across Cl stays well below 0.7V. The value of the capacitor Cl is much smaller than that of the capacitor C2 and its part in time delay is negligible. The tripping threshold is adjusted by suitable choice of the values on the components Rl, C2 and the number of turns in the windings Wla and Wlb.

The circuit of Figure 1 may be configured to detect AC currents as well as DC currents if the oscillator 12 frequency is sufficiently high compared to the frequency of the current to be detected, preferably at least an order of magnitude higher. Also, the primary winding may comprise more than the one conductor LI shown, in which case the circuit can detect and measure the vector sum of the DC currents (or AC currents if the oscillator 12 frequency is sufficiently high) flowing in the primary conductors. The circuit of Figure 1 may be used in any suitable application where a DC current is to be detected and measured, but it is especially useful in RCD applications.

In the context of residual current devices (RCDs) where at least two primary conductors pass through the CT core 10, in a perfect system Vout will always be zero when the vector sum of primary currents flowing through the core 10 is zero, and Vout will have a value greater than zero when a non-zero differential current ΙΔ flows in the primary conductors, i.e. the vector sum is non-zero. Such value of Vout will be proportional to ΙΔ, and residual current detecting circuitry (integrated circuit 1C 14) is calibrated so as to cause an event, e.g. tripping or activation of an alarm, when ΙΔ exceeds a predetermined threshold ΙΔη.

However, in certain cases Vout may be greater than zero when the vector sum of primary currents is zero. This may be due to imperfections in the CT core material or composition, etc. Such an output may also be caused by the residual effect of a large differential current that previously flowed in the primary circuit resulting in partial magnetization or saturation of the CT core in one direction. In such a case Vout may have a value greater than zero in the absence of any differential current in the primary circuit. This value can be referred to as Vos (standing value of Vout). Regardless of the cause, any value of Vos that is greater than zero for zero differential current in the primary circuit will result in a standing error in the residual current measuring circuit. A subsequent differential current in the primary circuit will also produce an output Vout, but depending on its polarity, the true differential current may produce an output that adds to or subtracts from the value of Vos with the result that Vout will no longer correspond to ΙΔ and activation of the RCD may occur at a value higher or lower than ΙΔη. This could result in nuisance tripping when the activation value is less than ΙΔ n, or non-tripping and reduced protection when the activation value is greater than ΙΔη.

It is an object of the invention to provide a circuit in which this problem is avoided or mitigated, so that activation of the RCD occurs at or very close to the intended ΙΔη value.

According to the present invention there is provided a circuit for calibrating a DC current detecting circuit ("DC circuit"), wherein the DC circuit comprises a current transformer ("CT") having a ferromagnetic core (10), at least one primary winding comprising a conductor (LI) passing through the core, and at least one secondary winding (Wla, Wlb), the DC circuit further including an oscillator (12) for supplying an oscillating signal across the secondary winding (Wla, Wlb) and means (Cl, Trl, Tr2, Rl, C2,14) for detecting a DC offset in the current flowing in the secondary winding, and wherein the calibrating circuit comprises a further secondary winding (W3) on the core (10), means for establishing a predetermined vector sum of DC current(s) flowing in the primary winding(s) (LI), and means (Vref, 20) for establishing a voltage across the further secondary winding (W3) and for adjusting the voltage so established until the DC offset equals a predetermined value.

The term "winding" is used in relation to the CT in accordance with conventional terminology, even though a winding may constitute a single conductor passing directly through a current transformer core.

Preferably, the predetermined vector sum of DC current(s) established in the primary winding(s) (LI) is zero. In such case, the circuit preferably forms part of an RCD of which the conductor (LI) forms a supply conductor to a load, and the predetermined vector sum of DC current(s) is established in the primary winding(s) (LI) as zero by disconnecting the load.

Preferably, too, at least one capacitor is connected in series with the secondary winding, and wherein the detecting means is arranged to detect a non-zero voltage across the capacitor above a certain level, the non-zero voltage corresponding to a dc offset greater than a predetermined magnitude.

The oscillator frequency is preferably at least an order of magnitude higher than mains supply frequency to allow the detection of mains frequency AC currents in the conductor.

In preferred embodiments the circuit includes at least one capacitor in series with the secondary winding, wherein the detecting means is arranged to detect a non-zero voltage across the capacitor above a certain level, the non-zero voltage corresponding to a dc offset greater than a predetermined magnitude.

Ideally, the RCD should be powered up on the supply side of the load contacts to ensure that it has power to facilitate the recalibration process while the load is disconnected.

The RCD may be a mechanically latching type or an electrically closing or latching type.

An embodiment of the invention will now be described, by way of example, with reference to the accompanying drawings, in which:

Figure 1 is a schematic diagram of a known circuit for detecting a DC current, and

Figure 2 is a schematic diagram of an embodiment of the invention based on Figure 1.

The embodiment of Figure 2 is in the form of a residual current device (RCD). For simplicity, the load, the load disconnection contacts, the solenoid which opens/closes the contacts, any neutral conductor passing through the CT core alongside LI, and other features conventionally found in such devices, are omitted to avoid overcrowding the drawing. A third secondary winding W3 has been added to the CT core 10. A voltage regulator Vref provides a stable fixed voltage which is connected to one end of W3. The other end of W3 is connected to a microcontroller (pC) 20 which can provide to the other end of W3 a variable DC voltage at a level above or below that of Vref. Thus, the voltage regulator Vref can sink or supply current. Vout is connected to the pC 20, and when the vector sum of the primary currents is zero, for example, when the load contacts are open and the load is disconnected, Vout should also be zero. However, if Vout is greater than zero when the vector sum of primary currents is zero, the pC 20 automatically increases its output voltage to W3 to a level slightly higher than Vref. If Vout starts to decrease in value, the pC output voltage continues to increase incrementally until Vout reaches its minimum value, which preferably approximates zero. However, if Vout starts to increase in value once the pC 20 voltage is applied to W3, the pC output voltage automatically decreases below Vref at which point it will see a reduction in the value of Vout. The pC 20 continues to reduce its output voltage value incrementally until Vout is minimised. When Vout has minimised, the output voltage from the pC 10 is then fixed and remains fixed. This calibration process takes place after the RCD trips and the load contacts are open.

In operation of the circuit, when a differential current equal to or greater than ΙΔη flows in the primary conductors, the RCD activation output voltage from 1C 14 will go high and cause the RCD to trip, resulting in opening of the load contacts. This results in a re-calibrate signal being sent to the pC 20 to indicate that the RCD has tripped and the load is disconnected. This in turn will re-initiate the self-calibration process such that pC 20 will drive Vout to its minimal value as described above. This ensures that if the RCD trips due to a very large differential current, any magnetization of the core will be compensated for by the CT calibration circuit. This feature also ensures that each time the RCD trips due to activation of a test circuit or external testing by a user, the RCD will go through the recalibration process before the user can reclose the RCD contacts.

Although the calibration process as described above adjusts Vout to zero or a minimum value, it could be adjusted to any predetermined value which is recognised by the 1C 14 as corresponding to a zero vector sum of the primary currents. Also, the invention can be readily applied to the current detection circuits shown in Figures 4 and 5 of US8975890 (WA/49), as well as more generally where DC currents are to be calibrated.

The invention is not limited to the embodiments described herein which may be modified or varied without departing from the scope of the invention.

Claims

1. A circuit for calibrating a DC current detecting circuit ("DC circuit"), wherein the DC circuit comprises a current transformer ("CT") having a ferromagnetic core (10), at least one primary winding comprising a conductor (LI) passing through the core, and at least one secondary winding (Wla, Wlb), the DC circuit further including an oscillator (12) for supplying an oscillating signal across the secondary winding (Wla, Wlb) and means (Cl, Trl, Tr2, Rl, C2,14) for detecting a DC offset in the current flowing in the secondary winding, and wherein the calibrating circuit comprises a further secondary winding (W3) on the core (10), means for establishing a predetermined vector sum of DC current(s) flowing in the primary winding(s) (LI), and means (Vref, 20) for establishing a voltage across the further secondary winding (W3) and for adjusting the voltage so established until the DC offset equals a predetermined value.

2. A circuit as claimed in claim 1, wherein the predetermined vector sum of DC current(s) established in the primary winding(s) (LI) is zero.

3. A circuit as claimed in claim 2, wherein the circuit forms part of an RCD of which the conductor (LI) forms a supply conductor to a load, and the predetermined vector sum of DC current(s) is established in the primary winding(s) (LI) as zero by disconnecting the load.

4. A circuit as claimed in claim 1, 2 or 3, including at least one capacitor in series with the secondary winding, wherein the detecting means is arranged to detect a nonzero voltage across the capacitor above a certain level, the non-zero voltage corresponding to a dc offset greater than a predetermined magnitude.

5. A circuit as claimed in claim 4, wherein the oscillator circuit comprises two secondary windings and the capacitor is connected in series between the secondary windings.

6. A circuit as claimed in any preceding claim, wherein the oscillator frequency is at least an order of magnitude higher than mains supply frequency to allow the detection of mains frequency AC currents in the conductor.