GB2545155A - Assembly of semiconductor devices - Google Patents

Assembly of semiconductor devices Download PDF

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Publication number
GB2545155A
GB2545155A GB1515564.1A GB201515564A GB2545155A GB 2545155 A GB2545155 A GB 2545155A GB 201515564 A GB201515564 A GB 201515564A GB 2545155 A GB2545155 A GB 2545155A
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United Kingdom
Prior art keywords
chips
iled
pled
head
deformable material
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Granted
Application number
GB1515564.1A
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GB201515564D0 (en
GB2545155B (en
Inventor
Hughes Padraig
O'keeffe Joseph
Oyer Celine
Henry William
Massoubre David
Saketi Pooya
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
STARBOARD ACQUISITIONS SUB, LLC
Facebook Technologies LLC
Original Assignee
Oculus VR Inc
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
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Publication date
Application filed by Oculus VR Inc filed Critical Oculus VR Inc
Priority to GB1515564.1A priority Critical patent/GB2545155B/en
Publication of GB201515564D0 publication Critical patent/GB201515564D0/en
Priority to GB1609422.9A priority patent/GB2541970B/en
Priority to EP18188965.0A priority patent/EP3425618B1/en
Priority to US15/753,959 priority patent/US10878733B2/en
Priority to CN201680064111.6A priority patent/CN108352143B/en
Priority to EP21216481.8A priority patent/EP3996076A1/en
Priority to PCT/GB2016/052722 priority patent/WO2017037475A1/en
Priority to JP2018511279A priority patent/JP2018531504A/en
Priority to CN201810504950.6A priority patent/CN108682370B/en
Priority to KR1020187010685A priority patent/KR20180041772A/en
Priority to KR1020187008607A priority patent/KR20180048812A/en
Priority to EP16778087.3A priority patent/EP3345178B1/en
Publication of GB2545155A publication Critical patent/GB2545155A/en
Priority to US15/918,985 priority patent/US10600823B2/en
Priority to JP2018077594A priority patent/JP2018142713A/en
Application granted granted Critical
Publication of GB2545155B publication Critical patent/GB2545155B/en
Active legal-status Critical Current
Anticipated expiration legal-status Critical

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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/67—Apparatus specially adapted for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus specially adapted for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components ; Apparatus not specifically provided for elsewhere
    • H01L21/683—Apparatus specially adapted for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus specially adapted for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components ; Apparatus not specifically provided for elsewhere for supporting or gripping
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L25/00—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof
    • H01L25/03—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof all the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. assemblies of rectifier diodes
    • H01L25/04—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof all the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. assemblies of rectifier diodes the devices not having separate containers
    • H01L25/075—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof all the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. assemblies of rectifier diodes the devices not having separate containers the devices being of a type provided for in group H01L33/00
    • H01L25/0753—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof all the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. assemblies of rectifier diodes the devices not having separate containers the devices being of a type provided for in group H01L33/00 the devices being arranged next to each other
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L25/00—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof
    • H01L25/16—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof the devices being of types provided for in two or more different main groups of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. forming hybrid circuits
    • H01L25/167—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof the devices being of types provided for in two or more different main groups of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. forming hybrid circuits comprising optoelectronic devices, e.g. LED, photodiodes
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L33/00—Semiconductor devices having potential barriers specially adapted for light emission; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof
    • H01L33/005—Processes
    • H01L33/0093—Wafer bonding; Removal of the growth substrate
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2221/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof covered by H01L21/00
    • H01L2221/67—Apparatus for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components; Apparatus not specifically provided for elsewhere
    • H01L2221/683—Apparatus for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components; Apparatus not specifically provided for elsewhere for supporting or gripping
    • H01L2221/68304—Apparatus for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components; Apparatus not specifically provided for elsewhere for supporting or gripping using temporarily an auxiliary support
    • H01L2221/68354—Apparatus for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components; Apparatus not specifically provided for elsewhere for supporting or gripping using temporarily an auxiliary support used to support diced chips prior to mounting
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2221/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof covered by H01L21/00
    • H01L2221/67—Apparatus for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components; Apparatus not specifically provided for elsewhere
    • H01L2221/683—Apparatus for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components; Apparatus not specifically provided for elsewhere for supporting or gripping
    • H01L2221/68304—Apparatus for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components; Apparatus not specifically provided for elsewhere for supporting or gripping using temporarily an auxiliary support
    • H01L2221/68368—Apparatus for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components; Apparatus not specifically provided for elsewhere for supporting or gripping using temporarily an auxiliary support used in a transfer process involving at least two transfer steps, i.e. including an intermediate handle substrate
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2221/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof covered by H01L21/00
    • H01L2221/67—Apparatus for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components; Apparatus not specifically provided for elsewhere
    • H01L2221/683—Apparatus for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components; Apparatus not specifically provided for elsewhere for supporting or gripping
    • H01L2221/68304—Apparatus for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components; Apparatus not specifically provided for elsewhere for supporting or gripping using temporarily an auxiliary support
    • H01L2221/68381—Details of chemical or physical process used for separating the auxiliary support from a device or wafer
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10—Bump connectors; Manufacturing methods related thereto
    • H01L2224/15—Structure, shape, material or disposition of the bump connectors after the connecting process
    • H01L2224/16—Structure, shape, material or disposition of the bump connectors after the connecting process of an individual bump connector
    • H01L2224/161—Disposition
    • H01L2224/16151—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/16221—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/16225—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
    • H01L2224/80001—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected by connecting a bonding area directly to another bonding area, i.e. connectorless bonding, e.g. bumpless bonding
    • H01L2224/80003—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected by connecting a bonding area directly to another bonding area, i.e. connectorless bonding, e.g. bumpless bonding involving a temporary auxiliary member not forming part of the bonding apparatus
    • H01L2224/80004—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected by connecting a bonding area directly to another bonding area, i.e. connectorless bonding, e.g. bumpless bonding involving a temporary auxiliary member not forming part of the bonding apparatus being a removable or sacrificial coating
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/74—Apparatus for manufacturing arrangements for connecting or disconnecting semiconductor or solid-state bodies
    • H01L24/75—Apparatus for connecting with bump connectors or layer connectors
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/10—Details of semiconductor or other solid state devices to be connected
    • H01L2924/11—Device type
    • H01L2924/12—Passive devices, e.g. 2 terminal devices
    • H01L2924/1204—Optical Diode
    • H01L2924/12041—LED
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L33/00—Semiconductor devices having potential barriers specially adapted for light emission; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof
    • H01L33/005—Processes
    • H01L33/0062—Processes for devices with an active region comprising only III-V compounds
    • H01L33/0066—Processes for devices with an active region comprising only III-V compounds with a substrate not being a III-V compound
    • H01L33/007—Processes for devices with an active region comprising only III-V compounds with a substrate not being a III-V compound comprising nitride compounds
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L33/00—Semiconductor devices having potential barriers specially adapted for light emission; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof
    • H01L33/005—Processes
    • H01L33/0095—Post-treatment of devices, e.g. annealing, recrystallisation or short-circuit elimination

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  • Engineering & Computer Science (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Computer Hardware Design (AREA)
  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Manufacturing & Machinery (AREA)
  • Devices For Indicating Variable Information By Combining Individual Elements (AREA)

Abstract

A deformable elastomer layer is arranged on the surfaces of micro ILEDs to facilitate assembly using a pick up tool. A flat glass, plastic or silicon pick up tool head is brought into contact with the elastomer layer of a micro ILED chip and a conformal contact between the pick up tool head and the elastomer layer is established which allows the chip to be picked up. Dies that are picked up may be bonded to a TFT substrate and once bonded the pick up tool is pulled away from the micro ILED chip with sufficient peel strength to release the pick tool head. A UV, temperature or pressure switchable adhesive may also be used on the pick up tool head. The deformable layer may also comprise microstructures that increases the adhesive force between the chip and the pick up tool head.

Description

ASSEMBLY OF SEMICONDUCTOR DEVICES
Technical field
The invention relates to methods and apparatus for assembling semiconductor devices. In particular, the invention relates to methods and apparatus for assembling semiconductor devices by contact printing. The invention may specifically relate to methods and apparatus for assembling semiconductor inorganic light emitting diode (ILED) devices.
Background
Displays are ubiquitous and are a core component of every wearable device, smart phone, tablet, laptop, desktop, TV or display system. Common display technologies today range from Liquid Crystal Displays (LCDs) to more recent Active Matrix Organic Light Emitting Diode Displays (AMOLEDs).
The display architectures include passive and active matrix displays depending on whether each pixel is driven separately or not. Active drive circuitry uses thin film transistor (TFT) where transistors based on amphorous, oxide or polysilion technology are manufactured using GEN glass panel manufacturing which has enlarged glass substrate sizes from the 1st generation of 30 cm x 40 cm to the 10th generation of 2.88 m x 3.15m.
However, in most portable devices (i.e. battery powered) the display uses the majority of the available battery power. Additionally, the most common user issue for portable devices is insufficient display brightness. To extend battery life and improve brightness levels, it is necessary to develop new display technologies that reduce power consumption and produce higher luminance emission from the light source.
Inorganic LEDs (ILEDs) are emerging as the third generation of flat display image generators based on superior battery perfromance and enhanced brightness. The ILED Display is at a basic level a variation of the OLED (organic LED) display. The OLED concept is based on passing current through organic or polymer materials that is sandwiched between two glass planes to produce light. The proposed ILED Display concept essentially replaces the organic LED material with a discrete standard LED (which is made of inorganic materials) at each pixel of the display (each pixel consists of three individual Red, Green and Blue LEDs for colour displays).
Standard (i.e. inorganic) LED devices have been around for many years and their performance (efficiency, brightness, reliability and lifetime) has been optimised over many years as the LED industry has pursued many commercial opportunities -especially the challenge of developing LED technology to enable it to replace the standard incandescent bulbs for general light applications, i.e. inorganic LEDs are significantly more efficient, bright and reliable than the new and less developed OLED materials.
The concept of individually switchable standard LEDs (R, G & B) at each pixel in a display is well known. This approach is in widespread use for large information displays. However, to-date it has not been possible to scale this approach down to smaller displays as standard LEDs are typically planar chips which are inefficient for light direction control. Additionally, the assembly of the many millions of pixels needed for a laptop or smart phone display is not feasible using existing assembly manufacturing techniques.
The current challenges with ILED display manufacture are significant and include assembly techniques to overcome wafer yields losses need to be factored into the manufacturing strategy of ILED displays for today’s yields and higher anticipated yields in the future. Selective pick up tools (PUTs) is one solution to overcoming yields problems where defective die are identified and replaced at source. Depending on the yield, it may not be practical or economical to either replace known bad die or transfer only KGD from a wafer to a temporary carrier for pick to the TFT substrate. Both approaches require wafer level testing to determine KGD or defect chips on the wafer which is complicated.
Smart assembly processes with resolutions to manipulate and handle small die improve ILED assembly on the glass panel. There is therefore a need for an assembly process with high throughput that can enable massive parallel pick and transfer of ILED dies of size < 10pm a side from the native LED wafer onto a glass TFT substrate at accuracies approx ±3pm or less.
Smart assembly methods are being developed in the industry for ILED displays and range from “non selective” elastomer conformal stamps, laser assisted transfer, direct self-assembly methods, fluidic assembly and selective MEMs based printheads. All techniques require the preparation of assembly ready chips where the bulk of the substrate is removed or the epilayer released from the substrate. For ILED displays to become a commercial reality, many or all of the above challenges need to be solved.
Summary of this Invention
According to the invention in a first aspect, there is provided a method for moving a semiconductor chip, the method comprising: contacting a pick up tool, PUT, head with a surface of a semiconductor chip at a first location, wherein the surface of the semiconductor chip comprises a deformable material configured to adhere to the PUT on contact; moving the PUT to a second location and releasing the semiconductor.
Optionally, the deformable material comprises an elastic material.
Optionally, the elastic material comprises an elastomeric material.
Optionally, the deformable material comprises a structured surface for contacting the PUT head and configured facilitate adhesion and/or release of the semiconductor chip.
Optionally, the structured surface comprises elongate pillars extending from the surface.
Optionally, the contact between the PUT head and the deformable material results in substantially no voids therebetween.
Optionally, the method further comprises depositing the deformable material on a surface of the semiconductor chip.
Optionally, the method further comprises removing the deformable material from the surface of the semiconductor chip.
Optionally, removal of the deformable material is by a process of etching. Optionally, the removal of the deformable material is by one of dissolving the deformable material or washing the deformable material away using a solution.
Optionally, the deformable material is deposited on top of a sacrificial layer deposited on the surface of the semiconductor chip, and wherein the etching process etches away the sacrificial layer.
Optionally, the PUT head is substantially rigid and/or substantially planar.
Optionally, method further comprises selectively adhering the PUT head to one or more of a plurality of semiconductor chips.
Optionally, there are a plurality of semiconductor chips, the method further comprising selectively removing the deformable material from one or more semiconductor chips before contact with the PUT head such that the PUT head does not adhere to those semiconductor chips.
Optionally, the method further comprises adhering the PUT head to a plurality of semiconductor chip.
Optionally, the semiconductor chips comprise ILED and/or pLED chips.
Optionally, the second location is a substrate of a semiconductor device.
Optionally, the substrate comprises a glass or plastics thin film transistor panel.
Optionally, the method further comprises arranging a plurality of ILED and/or pLED chips on the substrate to form an image generator of a display.
According to the invention in another aspect, there is provided a method for forming an image generator of an LED display, the method comprising: depositing a deformable material on a surface of a plurality of ILED and/or pLED chips; contacting a pick up tool, PUT, head with the deformable material deposited on one or more of the plurality of ILED and/or pLED chips, such that the one or more of the plurality of ILED and/or pLED chips adheres to the PUT head; moving the PUT head such that the one or more ILED and/or pLED chips are positioned such that contacts of the one or more ILED and/or pLED chips are in electrical communication with pads of thin film transistors of a glass or plastics thin film transistor panel; and releasing the one or more ILED and/or pLED chips from the PUT head.
According to the invention in another aspect, there is provided an image generator for an LED display, comprising: a plurality of ILED and pLED chips arranged on a glass or plastics thin film transistor panel, wherein the one or more ILED and/or pLED chips have been arranged on the glass or plastics thin film transistor panel by: depositing a deformable material on a surface of the plurality of ILED and/or pLED chips; contacting a pick up tool, PUT, head with the deformable material deposited on one or more of the plurality of ILED and/or pLED chips, such that the one or more of the plurality of ILED and/or pLED chips adheres to the PUT head; moving the PUT head such that the one or more ILED and/or pLED chips are positioned such that contacts of the one or more ILED and/or pLED chips are in electrical communication with pads of thin film transistors of a glass or plastics thin film transistor panel; and releasing the one or more ILED and/or pLED chips from the PUT head.
According to the invention in another aspect, there is provided a method for moving a semiconductor chip, the method comprising: contacting a pick up tool, PUT, head with a surface of a semiconductor chip at a first location, wherein the surface of the semiconductor chip comprises an intermediate layer that is conformal and results in a conformal surface contact between the surface of the intermediate layer and the PUT head.
Detailed description
Manufacturing processes are disclosed which address the assembly of semiconductor chips to form an ILED image generator for display products.
It is an objective of the methods and apparatus disclosed to provide an image generator and associated method of manufacture using a plurality of ILED chips which are specially designed to enable their contact and conformance to a PUT tool for handling and manipulation onto a TFT glass panel.
An Inorganic Light Emitting Diode (ILED) image generator is disclosed using a novel micro LED design and micro transfer assembly method. The ILED image generator comprises a substrate and a pluarility of pLED chips and an intermediate layer. In exemplary methods and apparatus, the term ILED encompasses a pLED. The intermediate layer is disposed onto at least one surface of the pLED chip and covers the pLED surface. The intermediate layer is deformable and may conform to the surface of the PUT. The intermediate layer may be a continuous layer or can be patterned with microstructures which facilitate the adhesion of the pLED chip for pickup, transfer and release using a non-conformal Pick Up Tool (PUT) transfer head. After assembly the intermediate layer can be removed using a release layer or through chemical degradation.
The method disclosed facilitates the assembly of pLED chips in pre-determined positions to manufacture an ILED image generator
An assembly method to manufacture inorganic light emitting diode (ILED) image generator for displays is disclosed. ILED displays are a new generation of display technology for use particularily, but not only, in energy sensitive/battery powered display applications such as wearables devices, wearable device, smart phone, tablet, laptop.
In exemplary methods and apparatus, an assembly method to manufacture an image generator for an ILED display is disclosed. Specifically, a method for pick and place (or movement) of ILED chips is disclosed using an intermediate layer which is on the ILED chip (and may be structured) and “intermediate” between the ILED chip and the print head during assembly. The use of the intermediate layer results in a conformal contact between the contact surface of the pick up tools (PUT) and the conformal (or deformable) surface of the intermediate layer leading to intimate contact substantially without voids - a necessity for optimal stiction of the ILED chip onto the contact surface of the PUT. The chips whether individually or collectively form the subpixels of the display pixel and are assembled using this technique onto a glass thin flim transistor (TFT) panel in a predefined pitch to create the ILED image generator. μΙ-ED technology in as used herein encompasses micron size LED device manufacture which directionalise the light output and maximise the brightness level observed by the user. The pLED as first disclosed in US7518149 is a next generation LED technology developed specifically to deliver directionalised light, i.e. only to where it is required. The pLED is typically < 20pm in diameter with a parabolic structure etched directly onto the LED die during the wafer processing steps to form a quasi-collimated light beam emerging from the chip (Figure 2). The micro ILED emitter shows a micro ILED structure similar to that proposed in WO 2004/097947 (US 7,518,149) with a high extraction efficiency and outputting quasi-collimated light because of its shape. Such a micro ILED 300 is shown in Figure 1, wherein a substrate 302 has a semiconductor epitaxial layer 304 located on it. The epitaxial layer 104 is shaped into a mesa 306. An active (or light emitting) layer 308 is enclosed in the mesa structure 306. The mesa 306 has a truncated top, on a side opposed to a light transmitting or emitting face 310. The mesa 306 also has a near-parabolic shape to form a reflective enclosure for light generated or detected within the device. The arrows 312 show how light emitted from the active layer 308 is reflected off the walls of the mesa 306 toward the light exiting surface 310 at an angle sufficient for it to escape the LED device 300 (i.e. within the angle of total internal reflection). The electrical contact pad of the device are not shown in Figure 1 but are located on the opposite surface to the emitting face 310.
This shaped structure results in a significant increase in the efficiency into low illumination angles when compared to unshaped or standard LED chips, see Figure 2. This increased efficiency and collimated output of the pLED is such that it can produce light visible to the human eye with only nano-amps of drive current.
Conformal pLEDs comprise of pLED chip having an intermediate layer. The intermediate layer is disposed onto at least one surface of the pLED chip and covers the pLED surface (i.e. emission surface 310 of Figure 1). The intermediate layer is conformal enabling this layer to form a conformal contact with another contact surface, such as a substantially rigid surface of a PUT.
By way of example, a process flow is disclosed in Figure 3, Figure 4 and Figure 5 based on GaN on sapphire material system for blue and green emitting pLEDs. It should be appreciated that this invention is not restricted to this material system nor the sequence of process flow proposed in this disclosure.
The process starts with a GaN on sapphire wafer with epi-layer and/or template plus the substrate which is tailored for ILED chip manufacture and assembly readiness.
The intial step in the process is the manufacture of the pLED device and together with a p and n contact pad. After pLED fabrication the chips are partially singulated on the wafer by a combination of photolithography to define a hard mask and dry etch methods (e.g. DRIE or ICP etch tools) which etches a typically 2pm wide, 3-5pm deep trench in the GaN epilayer/template between neighbouring devices. As an example, a SiOx hard mask is deposited and patterned using deep UV resist &amp; photolith tools to transfer the defined pattern into the SiOx using CF4/CHF3 ICP etch chemisty. This is followed by a second chlorine based etch chemistry to etch the GaN. The hard mask is left on the devices for isolation purposes.
After the partial singulation, a mechanical layer is applied to the top surface which acts as a handle layer for subseqent processing steps. Once the handle layer is applied a laser lift-off process is applied which removes the sapphire substrate using a laser beam. Laser lift-off processing is a technique to detach the sapphire substrate from the GaN epilayers using excimer laser photons. The technology is of interest for high throughput and superior quality in the manufacture of HB-LEDs (high brightness) and flexible displays.
Once the sapphire substrate is detached the structure is inverted and presented for further thin-film processing. Specifically according to this invention an intermediate layer is applied to the emitting surface of the pLED chip; i.e. surface 310 in Figure 1. The chip after LLO processis now fully singulated with the substrate removed and mounted to the handle layer.
The intermediate layer may comprise of a two layer structure consisting first of a sacrifical layer such as a resist which is deposited on the emitting surface. A second conformal (or deformable) layer such as an an elastomer is then applied on top of the sacrifical layer. The intermediate layer may be removed in the trenches between neighbouring devices in order to ensure the devices remained separate. A method for doing this includes a photolithography step to define and hard mask followed by a dry etch step.
The intermediate layer is referred to as being intermediate by location between the ILED chip and the transfer head used to pick up and place the die (semiconductor chips).
The intermediate layer is conformal and is a continuous layer across the surface of the pLED chip having a substantially uniform thickness. Alternatively, the intermediate layer can be patterned with microstructures which facilitate the pick up, transfer and/or release using a non-conformal transfer head. The intermediate layer is patterned such that the intermediate layer is patterned directly over the ILED chip so that the devices remain separated.
The transfer head or pick up tool (PUT) transfer head is a flat non-elastomeric head which when applied to the conformal intermediate layer on the pLED device resulting in a conformal contact which enables the chip to be picked up. The pick-up head maybe made from plastic, glass or silicon with a dimple protruding for each ILED chip to be picked up
Die that are picked up are directly transferred to and bonded to the TFT pads of the glass panel. Once placed and/or bonded, the pick up head can be removed from the conformal ILED chip using a suitable release mechanism. Mechanisms to release the PUT transfer head from the intermediate layer include 1). pull to generate sufficent peel strength to detach, 2). switchable adhesives surfaces on the PUT transfer head where the adhesive is switched by the application of an external parameter (examples include UV radiation, temperature &amp; pressure) 3). Microstructures on the intermedicate layer which can control the adhesion forces between the transfer head and the intermediate layer.
After assembly the intermediate layer can be removed by etching or removal of the sacrifical layer which is a release layer which effectively lift-offs the elastomer layer from the ILED chip.
In other embodiments of this invention, it maybe acceptable or desirable to leave the elastomeric layer on the chip. In this case the intermediate layer need only be a single layer without the underlying sacrifical layer.
The integration of the elastomeric layer with the ILED chips provides a significant benefit for display manufacture. The ability to selectively pick ILED devices represents a significant challenge. Current approaches focus on the selective addressing at the PUT. In the disclosed exemplary methods and apparatus, the material that enables the pick (i.e. the adhesive layer) is on the individual chips. As such this layer can be selectively modified to stop the pick of non-function devices. This could be achieved using a number of techniques. In an exemplary embodiment, a Digital Micro-mirror Device (DMD) can be used to scan a laser beam across the surface of the ILED wafer. This laser beam is used to selectively damage the elastomeric layer of the ILEDs which are not functioning. This would prevent the devices from binding to the PUT and from being picked. The ability to provide a wafer in which no non-functioning devices can be picked results in a great simplification of the assembly process.
This method facilitates the assembly of pLED chips in predetermined positions to manufacture an ILED image generator, see Figure 5 which is an exemplary cross section through an ILED display. The die is referred to as a display subpixel and consists of single emitter per chip with p and n electrodes formed on the same side as the mesa. The light output is in the opposite direction and through the epilayer of the ILED device. Figure 5 is a simple concept illustration of an ILED Display. R, G and B ILED’s are assembled onto a TFT glass panel substrate. Electrical tracks connects to the pLED with the electrode typically to the p-contact of the pLED and a separate electrode or ground to the n-contact - facilitating two contacts down approach as shown in this Figure. Further assembly of critical element of the full stack for an ILED image generator is not included in this disclosure but is assumed for an ILED display product. These include touch screen sensors, polarisers, glass cover etc.
The skilled person will be able to envisage other exemplary embodiments without departing from the scope of the appended claims.

Claims (20)

1. A method for moving a semiconductor chip, the method comprising: contacting a pick up tool, PUT, head with a surface of a semiconductor chip at a first location, wherein the surface of the semiconductor chip comprises a deformable material configured to adhere to the PUT on contact; moving the PUT to a second location and releasing the semiconductor.
2. A method according to claim 1, wherein the deformable material comprises an elastic material.
3. A method according to claim 2, wherein the elastic material comprises an elastomeric material.
4. A method according to any preceding claim, wherein the deformable material comprises a structured surface for contacting the PUT head and configured facilitate adhesion and/or release of the semiconductor chip.
5. A method according to claim 4, wherein the structured surface comprises elongate pillars extending from the surface.
6. A method according to any preceding claim, wherein the contact between the PUT head and the deformable material results in substantially no voids therebetween.
7. A method according to any preceding claim, further comprising depositing the deformable material on a surface of the semiconductor chip.
8. A method according to any preceding claim, further comprising removing the deformable material from the surface of the semiconductor chip.
9. A method according to claim 8, wherein removal of the deformable material is by a process of etching.
10. A method according to claim 9, wherein the deformable material is deposited on top of a sacrificial layer deposited on the surface of the semiconductor chip, and wherein the etching process etches away the sacrificial layer.
11. A method according to any preceding claim, wherein the PUT head is substantially rigid and/or substantially planar.
12. A method according to any preceding claim, further comprising selectively adhering the PUT head to one or more of a plurality of semiconductor chips.
13. A method according to any preceding claim, wherein there are a plurality of semiconductor chips, the method further comprising selectively removing the deformable material from one or more semiconductor chips before contact with the PUT head such that the PUT head does not adhere to those semiconductor chips.
14. A method according to any preceding claim, further comprising adhereing the PUT head to a plurality of semiconductor chip.
15. A method according to any preceding claim, wherein the semiconductor chips comprise ILED and/or pLED chips.
16. A method according to claim 15, wherein the second location is a substrate of a semiconductor device.
17. A method according to claim 16, wherein the substrate comprises a glass or plastics thin film transistor panel.
18. A method according to any of claims 16 to 17, further comprising arranging a plurality of ILED and/or pLED chips on the substrate to form an image generator of a display.
19. A method for forming an image generator of an LED display, the method comprising: depositing a deformable material on a surface of a plurality of ILED and/or pLED chips; contacting a pick up tool, PUT, head with the deformable material deposited on one or more of the plurality of ILED and/or pLED chips, such that the one or more of the plurality of ILED and/or pLED chips adheres to the PUT head; moving the PUT head such that the one or more ILED and/or pLED chips are positioned such that contacts of the one or more ILED and/or pLED chips are in electrical communication with pads of thin film transistors of a glass or plastics thin film transistor panel; and releasing the one or more ILED and/or pLED chips from the PUT head.
20. An image generator for an LED display, comprising: a plurality of ILED and pLED chips arranged on a glass or plastics thin film transistor panel, wherein the one or more ILED and/or pLED chips have been arranged on the glass or plastics thin film transistor panel by: depositing a deformable material on a surface of the plurality of ILED and/or pLED chips; contacting a pick up tool, PUT, head with the deformable material deposited on one or more of the plurality of ILED and/or pLED chips, such that the one or more of the plurality of ILED and/or pLED chips adheres to the PUT head; moving the PUT head such that the one or more ILED and/or pLED chips are positioned such that contacts of the one or more ILED and/or pLED chips are in electrical communication with pads of thin film transistors of a glass or plastics thin film transistor panel; and releasing the one or more ILED and/or pLED chips from the PUT head.
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GB1609422.9A GB2541970B (en) 2015-09-02 2016-05-27 Display manufacture
CN201810504950.6A CN108682370B (en) 2015-09-02 2016-09-02 Display and method for manufacturing the same
EP16778087.3A EP3345178B1 (en) 2015-09-02 2016-09-02 Assembly of semiconductor devices
CN201680064111.6A CN108352143B (en) 2015-09-02 2016-09-02 Assembly of semiconductor devices
EP21216481.8A EP3996076A1 (en) 2015-09-02 2016-09-02 Assembly of semiconductor devices
PCT/GB2016/052722 WO2017037475A1 (en) 2015-09-02 2016-09-02 Assembly of semiconductor devices
JP2018511279A JP2018531504A (en) 2015-09-02 2016-09-02 Assembly of semiconductor devices
EP18188965.0A EP3425618B1 (en) 2015-09-02 2016-09-02 Assembly of semiconductor devices
KR1020187010685A KR20180041772A (en) 2015-09-02 2016-09-02 Assembly of semiconductor devices
KR1020187008607A KR20180048812A (en) 2015-09-02 2016-09-02 Assemblies of semiconductor devices
US15/753,959 US10878733B2 (en) 2015-09-02 2016-09-02 Assembly of semiconductor devices using multiple LED placement cycles
US15/918,985 US10600823B2 (en) 2015-09-02 2018-03-12 Assembly of semiconductor devices
JP2018077594A JP2018142713A (en) 2015-09-02 2018-04-13 Assembly for semiconductor device

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