GB2537391B - Methods and systems for generating shaders to emulate a fixed-function graphics pipeline - Google Patents

Methods and systems for generating shaders to emulate a fixed-function graphics pipeline Download PDF

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Publication number
GB2537391B
GB2537391B GB201506372A GB201506372A GB2537391B GB 2537391 B GB2537391 B GB 2537391B GB 201506372 A GB201506372 A GB 201506372A GB 201506372 A GB201506372 A GB 201506372A GB 2537391 B GB2537391 B GB 2537391B
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Prior art keywords
shaders
emulate
generating
systems
methods
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Active
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GB201506372A
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GB201506372D0 (en
GB2537391A (en
Inventor
Fabius Aidan
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Channel One Holdings Inc
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Channel One Holdings Inc
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Publication date
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Priority to GB201506372A priority Critical patent/GB2537391B/en
Publication of GB201506372D0 publication Critical patent/GB201506372D0/en
Publication of GB2537391A publication Critical patent/GB2537391A/en
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Publication of GB2537391B publication Critical patent/GB2537391B/en
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Classifications

    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06T—IMAGE DATA PROCESSING OR GENERATION, IN GENERAL
    • G06T15/00—3D [Three Dimensional] image rendering
    • G06T15/005—General purpose rendering architectures
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F9/00—Arrangements for program control, e.g. control units
    • G06F9/06—Arrangements for program control, e.g. control units using stored programs, i.e. using an internal store of processing equipment to receive or retain programs
    • G06F9/30—Arrangements for executing machine instructions, e.g. instruction decode
    • G06F9/38—Concurrent instruction execution, e.g. pipeline, look ahead
    • G06F9/3836—Instruction issuing, e.g. dynamic instruction scheduling or out of order instruction execution
    • G06F9/3853—Instruction issuing, e.g. dynamic instruction scheduling or out of order instruction execution of compound instructions
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F9/00—Arrangements for program control, e.g. control units
    • G06F9/06—Arrangements for program control, e.g. control units using stored programs, i.e. using an internal store of processing equipment to receive or retain programs
    • G06F9/30—Arrangements for executing machine instructions, e.g. instruction decode
    • G06F9/38—Concurrent instruction execution, e.g. pipeline, look ahead
    • G06F9/3867—Concurrent instruction execution, e.g. pipeline, look ahead using instruction pipelines
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F9/00—Arrangements for program control, e.g. control units
    • G06F9/06—Arrangements for program control, e.g. control units using stored programs, i.e. using an internal store of processing equipment to receive or retain programs
    • G06F9/44—Arrangements for executing specific programs
    • G06F9/445—Program loading or initiating
    • G06F9/44521—Dynamic linking or loading; Link editing at or after load time, e.g. Java class loading
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F9/00—Arrangements for program control, e.g. control units
    • G06F9/06—Arrangements for program control, e.g. control units using stored programs, i.e. using an internal store of processing equipment to receive or retain programs
    • G06F9/44—Arrangements for executing specific programs
    • G06F9/455—Emulation; Interpretation; Software simulation, e.g. virtualisation or emulation of application or operating system execution engines
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06T—IMAGE DATA PROCESSING OR GENERATION, IN GENERAL
    • G06T1/00—General purpose image data processing
    • G06T1/20—Processor architectures; Processor configuration, e.g. pipelining
GB201506372A 2015-04-15 2015-04-15 Methods and systems for generating shaders to emulate a fixed-function graphics pipeline Active GB2537391B (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
GB201506372A GB2537391B (en) 2015-04-15 2015-04-15 Methods and systems for generating shaders to emulate a fixed-function graphics pipeline

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
GB201506372A GB2537391B (en) 2015-04-15 2015-04-15 Methods and systems for generating shaders to emulate a fixed-function graphics pipeline

Publications (3)

Publication Number Publication Date
GB201506372D0 GB201506372D0 (en) 2015-05-27
GB2537391A GB2537391A (en) 2016-10-19
GB2537391B true GB2537391B (en) 2020-01-01

Family

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Family Applications (1)

Application Number Title Priority Date Filing Date
GB201506372A Active GB2537391B (en) 2015-04-15 2015-04-15 Methods and systems for generating shaders to emulate a fixed-function graphics pipeline

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GB (1) GB2537391B (en)

Families Citing this family (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN117152320A (en) * 2023-02-15 2023-12-01 荣耀终端有限公司 Image processing method and electronic device

Citations (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
WO2002101649A1 (en) * 2001-06-08 2002-12-19 Nvidia Corporation Software emulator for optimizing application-programmable vertex processing
US7463259B1 (en) * 2003-12-18 2008-12-09 Nvidia Corporation Subshader mechanism for programming language
US20110279473A1 (en) * 2004-07-27 2011-11-17 Nvidia Corporation Translation of register-combiner state into shader microcode
US20140354658A1 (en) * 2013-05-31 2014-12-04 Microsoft Corporation Shader Function Linking Graph

Patent Citations (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
WO2002101649A1 (en) * 2001-06-08 2002-12-19 Nvidia Corporation Software emulator for optimizing application-programmable vertex processing
US7463259B1 (en) * 2003-12-18 2008-12-09 Nvidia Corporation Subshader mechanism for programming language
US20110279473A1 (en) * 2004-07-27 2011-11-17 Nvidia Corporation Translation of register-combiner state into shader microcode
US20140354658A1 (en) * 2013-05-31 2014-12-04 Microsoft Corporation Shader Function Linking Graph

Also Published As

Publication number Publication date
GB201506372D0 (en) 2015-05-27
GB2537391A (en) 2016-10-19

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Legal Events

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COOA Change in applicant's name or ownership of the application

Owner name: CHANNEL ONE HOLDINGS INC.

Free format text: FORMER OWNER: AIDAN FABIUS