GB2533603A - Debugging data processing transactions - Google Patents

Debugging data processing transactions Download PDF

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Publication number
GB2533603A
GB2533603A GB1423041.1A GB201423041A GB2533603A GB 2533603 A GB2533603 A GB 2533603A GB 201423041 A GB201423041 A GB 201423041A GB 2533603 A GB2533603 A GB 2533603A
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Prior art keywords
transaction
execution
conflict
target
detecting
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GB1423041.1A
Inventor
Diestelhorst Stephan
John Williams Michael
Roy Grisenthwaite Richard
James Horsnell Matthew
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ARM Ltd
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ARM Ltd
Advanced Risc Machines Ltd
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Priority to GB1423041.1A priority Critical patent/GB2533603A/en
Priority to GB1500183.7A priority patent/GB2533650B/en
Priority to US15/538,365 priority patent/US10394557B2/en
Priority to PCT/GB2015/053559 priority patent/WO2016102919A1/en
Priority to CN201580064594.5A priority patent/CN107003895B/en
Priority to PCT/GB2015/053561 priority patent/WO2016102920A1/en
Priority to CN201580069226.XA priority patent/CN107111488B/en
Priority to US15/532,286 priority patent/US10228942B2/en
Publication of GB2533603A publication Critical patent/GB2533603A/en
Withdrawn legal-status Critical Current

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    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F9/00—Arrangements for program control, e.g. control units
    • G06F9/06—Arrangements for program control, e.g. control units using stored programs, i.e. using an internal store of processing equipment to receive or retain programs
    • G06F9/30—Arrangements for executing machine instructions, e.g. instruction decode
    • G06F9/38—Concurrent instruction execution, e.g. pipeline or look ahead
    • G06F9/3854—Instruction completion, e.g. retiring, committing or graduating
    • G06F9/3858—Result writeback, i.e. updating the architectural state or memory
    • G06F9/38585—Result writeback, i.e. updating the architectural state or memory with result invalidation, e.g. nullification
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F11/00—Error detection; Error correction; Monitoring
    • G06F11/36—Preventing errors by testing or debugging software
    • G06F11/362—Software debugging
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F9/00—Arrangements for program control, e.g. control units
    • G06F9/06—Arrangements for program control, e.g. control units using stored programs, i.e. using an internal store of processing equipment to receive or retain programs
    • G06F9/30—Arrangements for executing machine instructions, e.g. instruction decode
    • G06F9/38—Concurrent instruction execution, e.g. pipeline or look ahead
    • G06F9/3824—Operand accessing
    • G06F9/3834—Maintaining memory consistency
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F9/00—Arrangements for program control, e.g. control units
    • G06F9/06—Arrangements for program control, e.g. control units using stored programs, i.e. using an internal store of processing equipment to receive or retain programs
    • G06F9/30—Arrangements for executing machine instructions, e.g. instruction decode
    • G06F9/38—Concurrent instruction execution, e.g. pipeline or look ahead
    • G06F9/3836—Instruction issuing, e.g. dynamic instruction scheduling or out of order instruction execution
    • G06F9/3842—Speculative instruction execution
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F11/00—Error detection; Error correction; Monitoring
    • G06F11/36—Preventing errors by testing or debugging software
    • G06F11/3664—Environments for testing or debugging software
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F9/00—Arrangements for program control, e.g. control units
    • G06F9/06—Arrangements for program control, e.g. control units using stored programs, i.e. using an internal store of processing equipment to receive or retain programs
    • G06F9/44—Arrangements for executing specific programs
    • G06F9/455—Emulation; Interpretation; Software simulation, e.g. virtualisation or emulation of application or operating system execution engines
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F9/00—Arrangements for program control, e.g. control units
    • G06F9/06—Arrangements for program control, e.g. control units using stored programs, i.e. using an internal store of processing equipment to receive or retain programs
    • G06F9/46—Multiprogramming arrangements
    • G06F9/466—Transaction processing
    • G06F9/467—Transactional memory

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  • Engineering & Computer Science (AREA)
  • Theoretical Computer Science (AREA)
  • Software Systems (AREA)
  • Physics & Mathematics (AREA)
  • General Engineering & Computer Science (AREA)
  • General Physics & Mathematics (AREA)
  • Computer Hardware Design (AREA)
  • Quality & Reliability (AREA)
  • Advance Control (AREA)

Abstract

A target transaction comprises a plurality of program instructions that execute to generate speculative updates to architectural state data. Upon detecting 200 a trigger condition the trigger condition corresponding to direct execution 202 of the transaction by processing hardware software emulation 204 of the target transaction is initiated. Preferably, the emulation permits single-stepping of the transaction instructions. Any conflict with the target transaction is detected 208, e.g. access to memory used by the transaction. If the target transaction completes without conflict then the software emulation stores data representing speculative updates generated during emulation of execution of the target transaction, i.e. the speculative updates are committed 214. The claimed invention finds typical application in debugging hardware transactions, e.g. transactional memory access. Also disclosed is an arrangement in which a memory access request is issued, receipt of a non-standard response thereto is detected and subsequent, dependent updating of architectural state occurs by one of two different processing paths (fig. 7). Also disclosed is an arrangement in which, on detecting a trigger condition, execution of a transaction is stopped prior to its completion and at least some of its speculative updates to state data are committed (fig. 9).

Description

DEBUGGING DATA PROCESSING TRANSACTIONS
This disclosure relates to data processing systems
There may be provided data processing systems supporting transactions in which a plurality of program instructions execute to generate speculative updates to state data and to commit the speculative updates if the transaction completes without a conflict. Such transactions may be used, for example, to facilitate multi-threaded processing using a shared memory in which transactions using data values within the shared memory may be allowed to proceed in parallel relying upon the ability to avoid committing speculative updates should a conflict arise between memory accesses. In most cases, such conflicts do not arise and accordingly the parallel processing proceeds efficiently without the need to support the overhead of more rigid mechanisms, such as the use of memory locks, and yet when a conflict does arise it is possible to recover as the speculative updates to state data will not have been committed.
In at least some example embodiments of the disclosure there is provided a method of processing data comprising: executing program instructions including a target transaction having a plurality of program instructions that execute to generate speculative updates to state data and to commit said speculative 20 updates if said target transaction completes without a conflict; detecting a trigger condition corresponding to direct execution by processing hardware of a program instruction of said target transaction; upon detecting said trigger condition, initiating software emulation of execution of said target transaction, said software emulation operating: to store data representing one or more versions of said speculative updates generated during emulation of execution of said target transactions; and to detect a conflict with said target transaction.
In at least some example embodiments of the disclosure there is provided apparatus for 30 processing data comprising processing hardware directly to execute program instructions including a target transaction comprising a plurality of program instructions that execute to generate speculative updates to state data and to commit said speculative updates if said transaction completes without a conflict; detection circuitry to detect a trigger condition corresponding to direct execution by said processing hardware of a program instmction of said target transaction; emulation circuitry to perform, upon detecting said trigger condition, software emulation of execution of said target transaction, said software emulation operating: to store data representing one or more versions of said speculative updates generated during emulation of execution of said target transactions; and to detect a conflict with said target transaction.
In at least some example embodiments of the disclosure there is provided a method of processing data comprising: issuing a memory access request from a request source; detecting receipt of a non-standard response signal at said request source; in dependence upon detection of receipt of said non-standard response signal initiating either 15 a first path of subsequent processing that updates architectural state data of said request source or a second path of subsequent processing that updates architectural state data of said request source, said first path being different from said second path.
In at least some example embodiments of the disclosure there is provided apparatus for 20 processing data comprising: issue circuitry to issue a memory access request from a request source; detection circuitry to detect receipt of a non-standard response signal at said request source; processing path control circuitry operating in dependence upon detection of receipt of said non-standard response signal to initiate either a first path of subsequent processing that updates 25 architectural state data of said request source or a second path of subsequent processing that updates architectural state data of said request source, said first path being different from said second path.
In at least some example embodiments of the disclosure there is provided a method of 30 processing data comprising: executing program instructions including a transaction having a plurality of program instructions that execute to generate speculative updates to state data and to commit said speculative updates if said transaction completes without a conflict; detecting a trigger condition; upon detecting said trigger condition, stopping execution of said transaction prior to completion of said transaction and committing at least some of said speculative updates to state data.
In at least some example embodiments of the disclosure there is provided apparatus for processing data comprising: processing circuitry to execute program instructions including a transaction having a 10 plurality of program instructions that execute to generate speculative updates to state data and to commit said speculative updates if said transaction completes without a conflict, detection circuitry to detect a trigger condition; control circuitry operating upon detecting said trigger condition to stop execution of said transaction prior to completion of said transaction and to commit at least some of said speculative 15 updates to state data.
Example embodiments will now be described, by way of example only, with reference to the accompanying drawings: Figure 1 schematically illustrates a stream of program instructions including a transaction; Figure 2 schematically illustrates a data processing system for executing program instructions, Figure 3 is a flow diagram schematically illustrating transaction execution; Figure 4 is a flow diagram schematically illustrating software emulated transaction execution, Figure 5 is a diagram schematically illustrating types of conflict which can arise between transactions; Figure 6 is a flow diagram schematically illustrating the issue of a non-standard response to a request source, Figure 7 is a flow diagram schematically illustrating control of subsequent processing in 5 response to receipt of a non-standard response; Figure 8 is a diagram schematically illustrating a data processing apparatus comprising multiple processor cores; and Figure 9 is a flow diagram schematically illustrating stopping execution of a transaction saving speculative updates when a triggered condition is detected.
When executing program instructions as part of a transaction which generates speculative updates that are discarded if the transaction is not completed without a conflict, there are difficulties in obtaining diagnostic data (debug data) which can be used to understand faults arising in such transactions. In particular, conventional diagnostic/debug mechanisms such as breakpoints and watchpoints which halt the execution occurring at particular points in the processing typically have the side effect of the loss of the speculative updates associated with a partially completed transaction as these will typically be flushed as a consequence of invoking the diagnostic/debug mechanisms. In some embodiments of the disclosure, this may be addressed by detecting a trigger condition corresponding to direct execution by processing hardware of a target transaction and using this to initiate software emulation of that target transaction in place of the direct execution. The software emulation can operate to store/preserve one or more versions of the speculative updates generated during the emulation such that these may be available for use in debugging/ diagnostic operations. The software emulation can continue to detect any conflict with the transaction being emulated in order that it interacts with the remaining system in a manner substantially corresponding to direct execution by the processing hardware.
Whilst conflict between transactions can take a number of forms (e.g. competing for a 30 shared resource), one common source of conflict is an access to a memory address that is used by the target transaction being emulated. The software emulation can trap such an access and indicate it as a conflict. The access may be any access (e.g. read or write) to the same address or one within the same region tracked as in use A useful feature that can be supported in some example embodiments is that the software emulation provides for the single-stepping of execution of the target transaction such that the software emulation can be stopped after emulation of execution of individual instructions of the target transactions This may permit a fine grained understanding of the behaviour of the target transaction to be obtained.
While it is possible that the emulation may be restricted to a single transaction, the present 10 disclosure also provides that a plurality of target transactions may be concurrently subject to software emulation. The software emulation may serve to detect conflicts arising between such a plurality of concurrently executing target transactions supported by software emulation.
In some example embodiments the start of a target transaction may be marked by a 15 transaction start instruction. In such circumstances, the trigger condition which triggers the start of software emulation may be the execution of such a transaction start instruction for a target transaction.
When a given target transaction is being subject to software emulation, it may be desired to identify sources of requests for memory accesses which conflict with the target transaction being subject to software emulation. Such behaviour may be facilitated by issuing a non-standard response to a request source issuing such a conflicting memory access request. This non-standard response may then serve to trigger non-standard behaviour in the request source to facilitate an understanding of its behaviour. Such non-standard responses may include, for example, stalling execution of the request source, retrying the request, or initiating software emulation of execution at the request source.
The understanding of the interaction of potentially conflicting different portions of a system may be facilitated in some example embodiments of the disclosure in which a relative rate of 30 software emulation of execution for a request source which conflicts and the software emulation of the target transaction may be controlled.
In some example embodiments of the disclosure the software emulation may also serve to model the availability of resources for storing the speculative updates to state data. The availability of such resources may be an issue which gives rise to incorrect operation and accordingly it is useful that such behaviour be emulated.
Data processing systems which support transactions typically include detecting hardware circuitry which serves to detect conflicts arising during direct hardware based execution of transactions. Such detecting hardware circuitry may, for example, include memory snoop hardware for supporting data coherence. Within such systems, the software emulation of a transaction may reuse the conflict detecting hardware circuitry to detect conflict arising during emulation of execution of the target transaction. The software emulation may program the conflict detecting hardware circuitry with appropriate data/parameters such that it serves to detect conflicts with transaction being subject to the software emulation.
Some example embodiments of the present disclosure support different forms of behaviour depending upon whether or not a non-standard response signal is received in response to a memory access request. Within such embodiments either a first path of subsequent processing that proceeds to update architectural state data or a second path of subsequent processing that proceeds differently to update architecturally state data is followed in dependence upon whether or not the non-standard response signal has been received These different paths are both legitimate paths for further processing and forward progress.
In some example embodiments, the non-standard response signal may be returned when a conflicting memory access at a request destination is detected when that request destination is performing software emulation of a transaction. In this way, request sources which interact with a software emulated transaction may be triggered to follow a different path of processing than would otherwise be the case through the return of the non-standard response signal. For example, the nonstandard response signal may trigger the request source itself to start software emulation of its processing.
While it will be appreciated that the normal assumption for transaction based processing is that speculative updates are not committed if a conflict arises, in some example embodiments of the disclosure, this model may be broken such that upon detection of a triggered condition the execution of the transaction is stopped and the speculative updates to state data are committed even though the transaction has not completed normally. Such behaviour deviates from the architectural assumption associated with transactions and so ongoing processing may no longer be possible, but in some circumstances the visibility achieved of the speculative updates of state data may permit a useful understanding of the behaviour of the system to be achieved in a manner that would otherwise be difficult.
As well as freezing the execution of the transaction for which the trigger condition was detected, in some embodiments of the disclosure the execution of one or more concurrently executing program threads which interact with that transaction may also be stopped. This may be facilitated by the use of the non-standard response signals as previously discussed to trigger the halting of execution of any concurrently executing program threads which request access to any of the data within a working set of data used by the transaction which has itself been halted. These further threads may themselves be further transactions which then save their speculative updates even though they have not completed It will be appreciated that the trigger condition associated with the stopping of a partially completed transaction and the saving of its speculative updates can take a variety of different forms.
These forms may include, for example, detecting execution of a triggered program instruction, detecting execution of a program instruction having an associated program counter value matching a predetermined triggered program counter; and/or detecting access to a predetermined memory address or range of addresses.
Figure 1 schematically illustrates a stream of program instructions 2 which may be executed by processing circuitry. It will be appreciated that this stream of program instructions may be one thread executing within a multi-threaded system. Alternatively, the stream of program instructions may be the single thread of program instructions executing. Within the stream of program instructions illustrated in Figure 1, there are included a transaction start instruction TStart and a transaction end instruction TEnd. These instructions respectively indicate the boundaries of a transaction comprising instructions IA, IB, IC and ID. These transactions bounded by the TStart and the Tend are executed by the processing circuitry to generate speculative updates to state data.
These speculative updates are stored within memory, or other storage resources of the system (e.g. shadow registers, special purpose memory permitting roll back, and the like), until it is determined that the transaction has completed without a conflict at which point the speculative updates are committed to the system (e.g. update the architectural state (e.g. the state forming the programmers model of the system) of the system with the stored roll back data then being discarded freeing up the associated memory resource to support a further transaction).
Figure 2 schematically illustrates a data processing system 4 including a processor core 6 and a memory system 8. The memory system 8 may be a hierarchical system including one or more levels of cache memory as well as a main memory. The hierarchical memory system 8 may be shared with other processors, or with other threads running on the same processor. The processor core 6 provides processing circuitry for executing program instructions fetched from the memory 8. The results of the execution of the program instructions may be written back to the memory 8. Load and store program instructions may be used to read and write data from and to the memory 8.
The processor core 6 includes a register bank 10, a multiplier 12, a shifter 14 and an adder 16 which together perform processing operations to execute the program instructions until control of control signals generated by an instruction decoder 18 as program instructions reach the decode stage within an instruction pipeline 20. Also associated with the processor core 6 is debug and diagnostic circuitry 22 which serves to perform, for example, instruction sampling to capture instruction diagnostic data and tracking of transactions which include sampled instructions so as to generate transaction diagnostic data. This instruction diagnostic data and transaction diagnostic data may be written out to the memory 8 or may be output in a trace data stream depending upon the embodiment and/or the requirements for operating an embodiment supporting both potential output mechanisms. The debug and diagnostic circuitry 22 may also detect a trigger condition to start software emulation of a transaction.
Figure 3 is a flow diagram schematically illustrating the execution of a transaction comprising multiple program instructions. At step 24 processing waits until a transaction start instruction is executed. Step 26 allocates transaction resources used, for example, to store the speculative updates to state data prior to the transaction completing without conflict and the speculative updates being committed. Step 28 selects the first instruction within the transaction. Step 30 determines whether or not there are any conflicts or aborts detected at that time. If there are any such conflicts or aborts detected, then step 32 serves to discard any speculative updates and return the transaction resources allocated at step 26 for use in other transactions If there are no conflicts or aborts detected at step 30, then step 34 serves to execute the 5 selected instruction. Step 36 stores the results of the execution at step 34 as speculative updates to state data within the allocated transaction resources. Step 38 selects a next instruction. Step 40 determines whether or not the selected instruction is a transaction end instruction. If the instruction is not a transaction end instruction, then processing returns to step 30. If the determination at step 40 is that the selected instruction is a transaction end instruction, then step 42 serves to commit the 10 speculative updates stored within the allocated transaction resources so as to update the architectural state of the system since the transaction has executed without a conflict or an abort arising.
Figure 4 is a flow diagram schematically illustrating software emulated transaction execution. At step 200 processing waits until a trigger condition is detected by the debug and diagnostic circuitry 22. This triggered condition may take a variety of different forms. One example form would be the execution of a transaction start instruction associated with a particular transaction. One way this might be achieved would be to detect the execution of a transaction start instruction with a program counter value matching a predetermined program counter value and correspond to the start of a target transaction to be subject to diagnosis/debugging.
When the triggered condition is detected, step 202 serves to stop hardware execution of the target transaction. Step 204 starts software emulation of the target transaction. This software emulation may be instruction-by-instruction software emulation (i.e. single-stepping execution) 25 facilitating single-stepping analysis of the behaviour of the target transaction.
Step 206 serves to store, under software control, the speculative updates to the state data associated with the target transaction for each emulated instruction This provides stored versioning of the speculative updates to facilitate an understanding of the behaviour of the target transaction.
Step 208 determines whether or not any conflict or abort has arisen for the target transaction being subject to software emulation. If such a conflict or abort arises, then the software emulated transaction execution is finished If no conflict or abort is detected, then step 210 serves to advance the execution point to the next instruction to be emulated. Step 212 determines whether the next instruction is a transaction end instruction. If the next instruction is a transaction end instruction, then step 214 serves to commit the speculative updates to the architectural state of the system. If the determination at step 212 is that the next instruction is not a transaction end instruction, then step 216 serves to emulate that next instruction and processing returns to step 206.
Figure 5 schematically illustrates various forms of conflict which may arise between concurrently executing transactions. Thread 0 is subject to software emulation. The regions within the memory address space of the system which are part of a work set of data being used by Thread 0 10 are marked with "#" in Figure 5 In the case of Thread 1, this performs a write as action a0 to part of the work set of data for Thread 0. Conflict detecting hardware circuitry identifies this as a conflict. Such conflict detecting hardware circuitry may comprise, for example, snoop or data coherency mechanisms provided to support shared memory operation (and programmed/configured as part of the setup of the software emulation). The detected conflict serves to trigger a notify signal being sent to Thread 0 as action al so that the emulation of Thread 0 is made aware of the conflict. Furthermore, a signal triggering Thread 1 to commence software emulation of Thread 1 and to pause is sent at step a.
A further example of a conflict that can arise is illustrated in relation to Thread 0 and Thread 2. In this case, Thread 0 performs a write to a memory address within its work set of data as step b0. Subsequently Thread 2 performs a read to this memory address (or at least to the same region of memory corresponding to the granularity at which memory accessed are being tracked). This read operation is indicated as bl in Figure 5. The conflicting read triggers the software emulated Thread 0 to be aborted via action b2 and the return of a non-standard response signal NACK as action b3. The non-standard response signal is sent to Thread 2 which was the request source for the read request sent as bl.
Figure 6 is a flow diagram schematically illustrating the detection of conflicts between a 30 transaction having a work set of data and other processing within the system. At step 218, a request to access a memory address within a work set of the data for the emulated transaction is detected. Step 220 determines whether the request is a write to an address that the emulated transaction has accessed. If the request is a write, then step 222 issues a non-standard response request to the source in the form of, for example, an NACK signal as shown in Figure 5. Step 222 determines whether the request is a read address that the emulated transaction has accessed. If the request is a read, then again a non-standard response signal may be issued. If neither the determination at step 220 or step 224 is positive, then step 226 serves to permit the access to be performed.
Figure 7 schematically illustrates the behaviour at a request source in response to receipt of a non-standard response. At step 228, processing waits until there is a memory access to perform. Step 230 sends the memory access request to the request destination. Step 232 waits until a response is received from the request destination. Step 234 determines whether the response received is a non-standard response. If the received response is a non-standard response, then step 236 serves to trigger the request source to follow a first path of subsequent processing, such as, for example, stalling, retrying the request, or software emulation of processing at the request source. If the response returned is not a non-standard response, then step 238 serves to control the request source to follow a second path of subsequent processing, such as performing the access which was requested at step 228. It will be appreciated that both the first path of subsequent processing and the second path of subsequent processing serve to update the architectural state of the system and are both legitimate paths for forward progress to be made in the processing performed.
Figure 8 schematically illustrates a data processing apparatus 240 comprising a plurality of processor cores 242, 244, 246 and 248 each having a local cache memory. A shared cache memory 250 as well as a main memory 252 are also provided within the hierarchical memory system of the data processing apparatus 240. A snoop control unit and transaction memory support circuitry 254 is provided and is coupled to the memory system at various points. The snoop control unit and transactional support circuitry 254 serves to ensure data coherence for different threads of processing using the shared memory system as well as serving to detect conflicts arising between a partially completed transaction with its associated speculative updates to state data and other memory accesses within the system. If such a conflict is detected, then the transaction concerned may be aborted and the speculative updates discarded.
Also illustrated in Figure 8 is debug circuitry 256 which serves to support debug and diagnostic operations of the data processing apparatus 240. The debug circuitry 256 includes detection circuitry 258 which detects trigger conditions for triggering the initiation of diagnostic or debug operations, such as software emulations of transactions, stalling or retrying of transactions and the like The detection circuitry may detect trigger conditions of a variety of different forms including, for example, execution of a trigger program instruction, execution of a program instruction having an associated program counter value matching a predetermined program counter and/or detecting access to a predetermined memory address or memory address region.
Figure 9 is a flow diagram schematically illustrating further example behaviour which may be provided in some embodiments in understanding transactions. Processing waits at step 260 until execution of a transaction is detected. Step 262 then determines whether or not a trigger condition associated with "freezing" execution of that transaction has occurred. If such a trigger condition has not arisen, then step 264 determines whether or not the transaction is still executing and if so returns processing to step 262. If the transaction terminates without the trigger condition being detected, then processing returns to step 260.
If the triggered condition is detected at step 262, then step 266 serves to commit the speculative updates being held for the transaction being executed to architectural state of the system. This goes against the normal behaviour of transactions in which the architectural state of the system is normally only updated if the whole of the transaction completes without a conflict being detected. However, saving the speculative updates partway through the execution of a transaction may provide useful information in understanding the behaviour of the transaction.
Processing then proceeds to step 268 where a determination is made as to whether any conflicting request to the transaction which has been halted is made. If any such conflicting request is received, then step 270 serves to return a non-response signal to the request source for the conflicting request. This non-standard response signal can serve to trigger the request source to itself stop its execution and save its state, e.g. if the request source is another transaction, then that other transaction may have its operation halted and its state saved partway through its execution.
Although illustrative embodiments have been described in detail herein with reference to the accompanying drawings, it is to be understood that the claims are not limited to those precise embodiments, and that various changes, additions and modifications can be effected therein by one skilled in the art without departing from the scope and spirit of the appended claims. For example, various combinations of the features of the dependent claims could be made with the features of the independent claims

Claims (7)

  1. CLAIMSI. A method of processing data comprising: executing program instructions including a target transaction having a plurality of program 5 instructions that execute to generate speculative updates to state data and to commit said speculative updates if said target transaction completes without a conflict; detecting a trigger condition corresponding to direct execution by processing hardware of a program instruction of said target transaction; upon detecting said trigger condition, initiating software emulation of execution of said 10 target transaction, said software emulation operating: to store data representing one or more versions of said speculative updates generated during emulation of execution of said target transactions; and to detect a conflict with said target transaction.
  2. 2. A method as claimed in claim 1, wherein said conflict comprises an access to a memory address in use by said target transaction
  3. 3. A method as claimed in claim 2, wherein said access comprises one of a write to a memory address that has been accessed by said target transaction; and a read from a memory address that has been accessed by said target transaction.
  4. 4. A method as claimed in any one of the preceding claims, wherein said software emulation single steps execution of said target transaction to permit said software emulation to be stopped after emulation of execution of individual instructions of said target transaction
  5. 5. A method as claimed in any one of the preceding claims, wherein said program instructions include a plurality of target transactions and said software emulation operates to emulate a plurality of concurrently executing target transactions and to detect conflict between said plurality of concurrently executing target transactions.
  6. 6. A method as claimed in claim 5, wherein said software emulation operates to control relative rates of emulated execution of said plurality of concurrently executing target transactions.
  7. 7. A method as claimed in any one of the preceding claims, wherein a start of said target transaction is marked with a transaction start instruction arid said trigger condition is execution of said transaction start instruction.8 A method as claimed in any one of the preceding claims, comprising upon detection of a request from a request source to perform a memory access conflicting with said target transaction undergoing software emulation, issuing a non-standard response to said request source.9 A method as claimed in claim 8, comprising upon receipt of said non-standard response at said request source, one of: stalling execution at said request source; retrying said request; and initiating software emulation of execution at said request source.10. A method as claimed in claim 9, comprising controlling a relative rate of software emulated execution at said request source and said software emulation of said target transaction.11. A method as claimed in any one of the preceding claims, wherein said software emulation models availability of resources for storing said speculative updates to state data.12. A method as claimed in any one of the preceding claims, wherein conflict detecting hardware circuitry operates to detect said conflict during direct execution of said target transaction 25 by said processing hardware and said software emulation reuses said conflict detecting hardware circuitry to detect said conflict during emulation of execution of said target transaction.13 A method as claimed in claim 12, wherein said software emulation configures said conflict detecting hardware circuitry to detect said conflict during emulation of execution of said target 30 transaction.14. Apparatus for processing data comprising processing hardware directly to execute program instructions including a target transaction comprising a plurality of program instructions that execute to generate speculative updates to state data and to commit said speculative updates if said transaction completes without a conflict, detection circuitry to detect a trigger condition corresponding to direct execution by said processing hardware of a program instruction of said target transaction; emulation circuitry to perform, upon detecting said trigger condition, software emulation of execution of said target transaction, said software emulation operating: to store data representing one or more versions of said speculative updates generated during emulation of execution of said target transactions; and to detect a conflict with said target transaction 15. A method of processing data comprising: issuing a memory access request from a request source; detecting receipt of a non-standard response signal at said request source; in dependence upon detection of receipt of said non-standard response signal initiating either a first path of subsequent processing that updates architectural state data of said request source or a second path of subsequent processing that updates architectural state data of said request source, said first path being different from said second path.16. A method as claimed in claim 15, comprising receiving said memory access request at a request destination and, if said request destination is performing software emulation of a transaction, said transaction having a plurality of program instructions that execute to generate speculative updates to state data and to commit said speculative updates if said transaction completes without a conflict, then returning said non-standard response signal to said request source.17 A method as claimed in any one of claims 15 and 16, wherein said first path is software emulation of program instruction execution 18. A method as claimed in any one of claims 15, 16 and 17, wherein said non-standard response signal has a plurality of different forms that respectively trigger different first paths of subsequent processing 19. Apparatus for processing data comprising: issue circuitry to issue a memory access request from a request source; detection circuitry to detect receipt of a non-standard response signal at said request source; processing path control circuitry operating in dependence upon detection of receipt of said non-standard response signal to initiate either a first path of subsequent processing that updates architectural state data of said request source or a second path of subsequent processing that updates architectural state data of said request source, said first path being different from said second path.20. A method of processing data comprising: executing program instructions including a transaction having a plurality of program instructions that execute to generate speculative updates to state data and to commit said speculative updates if said transaction completes without a conflict; detecting a trigger condition; upon detecting said trigger condition, stopping execution of said transaction prior to completion of said transaction and committing at least some of said speculative updates to state data.21. A method as claimed in claim 20, comprising upon detecting said trigger condition, stopping execution of one or more concurrently executing program threads that interact with said transaction.22. A method as claimed in claim 21, wherein said transaction has a working set of data used by said transaction and comprising returning a non-standard response signal to any concurrently 25 executing program threads requesting access to any of said working set of data.23 A method as claimed in claim 22, wherein receipt of said non-standard response signal by a given concurrently executing program thread triggers stopping execution of said given concurrently executing program thread 24. A method as claimed in any one of claims 21 to 23, wherein at least one of said one or more concurrently executing program threads is also executing a further transaction and stopping executing said further transaction comprises stopping execution of said further transaction prior to completion of said further transaction and committing at least some of speculative updates of said further transaction to state data 25. A method as claimed in any one of claims 20 and 24, wherein detecting said trigger condition comprises at least one of: detecting execution of a trigger program instruction; detecting execution of a program instruction haying an associated program counter value matching a predetermined trigger program counter value; and detecting access to a predetermined memory address.26. Apparatus for processing data comprising: processing circuitry to execute program instructions including a transaction haying a plurality of program instructions that execute to generate speculative updates to state data and to 15 commit said speculative updates if' said transaction completes without a conflict; detection circuitry to detect a trigger condition; control circuitry operating upon detecting said trigger condition to stop execution of said transaction prior to completion of said transaction and to commit at least some of said speculative updates to state data.27. A method of processing data substantially as hereinbefore described with reference to the accompanying drawing.28. Apparatus for processing data substantially as hereinbefore described with reference to the accompanying drawing.
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GB1423041.1A GB2533603A (en) 2014-12-23 2014-12-23 Debugging data processing transactions
GB1500183.7A GB2533650B (en) 2014-12-23 2015-01-07 Debugging data processing transactions
US15/538,365 US10394557B2 (en) 2014-12-23 2015-11-23 Debugging data processing transactions
PCT/GB2015/053559 WO2016102919A1 (en) 2014-12-23 2015-11-23 Debugging data processing transactions
CN201580064594.5A CN107003895B (en) 2014-12-23 2015-11-23 Instruction sampling within transactions
PCT/GB2015/053561 WO2016102920A1 (en) 2014-12-23 2015-11-23 Instruction sampling within transactions
CN201580069226.XA CN107111488B (en) 2014-12-23 2015-11-23 Debugging data processing transactions
US15/532,286 US10228942B2 (en) 2014-12-23 2015-11-23 Instruction sampling within transactions

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