GB2530977A

GB2530977A - Printhead having driver circuit

Info

Publication number: GB2530977A
Application number: GB1415990.9A
Authority: GB
Inventors: L Van Brocklin Andrew
Original assignee: Xaar Technology Ltd
Current assignee: Xaar Technology Ltd
Priority date: 2014-09-10
Filing date: 2014-09-10
Publication date: 2016-04-13
Also published as: GB201415990D0

Abstract

A printhead has a piezoelectric actuator and a driver circuit 100, the actuator having a first electrode 40 for receiving a common drive signal, and a second electrode 50 for use by a return path; the driver circuit includes a n-channel switching transistor 32 in an open drain configuration; the drain of the transistor 32 is connected to the second electrode 50 and the source is connected to the return path for the drive signal; when the transistor 32 is not conducting a voltage between the first 40 and second 50 electrodes is not affected by changes in the drive signal; a body diode or similar functionality diode 42 provides a conduction path to the substrate of the transistor 32 when a voltage between the electrodes exceeds a threshold. The transistor 32 is preferably an LDMOS transistor and the driver circuit may include a timing control circuit; a greyscale circuit or a logic lift circuit.

Description

PRINTHEAD HAVING DRIVER CIRCUIT

Technical Field

The present invention relates to printheads, and to printers having such printheads, and to integrated circuits for such printheads.

Background

It is known to provide printheads having driver circuits for driving actuating elements to eject fluid from a nozzle in an actuating chamber in inkjet printers. Existing piezoelectric (piezo) cold switch driver ASIC5 have the limitation of the cost and power dissipation of the high voltage pass gates and associated level shifter used to gate a cold switch power waveform on to each individual actuating element. The problem is how to provide electrical drive for a piezoelectric actuating element at the lowest cost and with the lowest power dissipation while still meeting minimum drive requirements.

The inkjet industry has been working intensively on how to drive piezoelectric actuating elements for more than twenty years. Multiple drive methods have been produced and there are multiple different types in use today. Some are briefly discussed now.

Hot Switch: This is the class of driving methods that keep the demux function and the power dissipation (CVA2) in the same driver IC. This was the original drive method, before cold switch became popular.

Rectangular Hot Switch: This describes hot switch systems that have no flexible control over rise and fall time and only two voltages (OV and 30V for example). In some cases waveform delivery is uniform to all the actuating elements. The waveform has some level of programmability.

DAC Hot Switch describes a class of drive options that has a logic driving an arbitrary digital value stream to a DAC (Digital Analog Converter) per actuating element, outputs a high voltage drive power waveform scaled from this digital stream. In terms of driving flexibility, this option has the most capability. It is limited only by the number of digital gates and the complexity that that system designers can use and/or tolerate.

Cold Switch Demux: This describes an arrangement in which all actuating elements are fed the same drive signal through a pass gate type demultiplexer. The drive signal is gated at sub-pixel speeds.

It is known from US2005200639 to provide a switch for providing drive pulses by coupling a common drive waveform to one side of many individual actuating elements. The other side of the actuating elements are coupled to a return path via switches. The switches are individually controlled according to which pixels are to be printed. A timing of the switching on is adjusted according to a waveform adjustment data to provide more uniform printing by adjusting a drive pulse width without needing to adjust the common drive waveform. A diode is coupled across each switch to enable conduction when the common drive signal has a greater potential than the return path, to avoid needing to switch on the switch again.

Summary

Embodiments of the invention can provide improved apparatus or methods or computer programs. According to a first aspect of the invention, there is provided a printhead comprising a plurality of actuating elements, and a driver circuit for each of the actuating elements, the actuating elements each having at least a first electrode for receiving a common drive signal, and a second electrode for coupling to a return path for the common drive signal, the driver circuit having an input for a print signal, and having an n-channel switching transistor having a drain coupled to the second electrode, and a source coupled to the return path, and operable according to the print signal, to couple the second electrode to the return path to drive the actuating element, the switching transistor being configured to have an open drain such that, when the switching transistor is not conducting, a voltage between the first and second electrodes is unaffected by changes in the common drive signal on the first electrode.

This design is distinct from pass gate in that the voltage on both of the electrodes on the actuator moves with the drive voltage when the actuator is not being driven and the switching transistor in most configurations, having a body diode providing a conduction path to a substrate of the switching transistor when a voltage between the second electrode and the substrate becomes negative by more than a threshold, to enable a voltage between the first and second electrodes to follow changes in the voltage on the first electrode. This drive technique will work without a body diode, but this makes trimming using this drive technique more difficult. If a diode is desired, there are several ways to create it, such as the body diode inherent in an [DM03, or to parallel this body diode with a Schottky or other diode.

That has the advantage of reduced parasitic substrate current, but costs area. It is also possible to use a process that has only HVCMOS, not LDMOS, available. In this case, there is no body diode, for example in an HVNMOS. So all three cases are possible: no body diode, a body diode and a Schottky diode. Both body and Schottky diodes would be in the same orientation. In the case of no body diode, care should be taken not to have negative voltages, since these would conduct through the ESD structures on the die.

By providing the conduction path through the body diode or similar functionality source to drain diode, protection can be provided against undesirable effects from negative voltages caused by the capacitive load of the actuating element, with more efficient use of circuit area than by only using external components. This also provides advantages in greyscale trimming and rejoining to the cold switch waveform as explained below. Also, the combination of open drain and body diode or similar functionality source to drain diode can enable pulse height control to be implemented more easily with less complex control circuitry.

This combination enables such pulse height control because the switching transistor can be switched off after part of a leading edge and the body diode conduction can start to conduct after part of the trailing edge. This can provide an improved trade-off between complexity of circuitry for control of the switching transistor and precision of pulse height control.

Furthermore, the combination of open drain and having the switching transistor on the return path side of the actuating element can enable lower voltages to be used for controlling the switching transistor, compared to a pass gate type circuit. This can enable simpler circuitry with reduced circuit area, thermal dissipation and costs. See Figures 1, 2, 3 for example.

Any additional features can be added to any of the aspects, or disclaimed, and some such additional features are described and some set out in dependent claims. One such additional feature is the switching transistor comprising an [DM03 transistor. [DM03 (Laterally Diffused Metal Oxide Semiconductor) devices have the lowest resistance per unit area for switching devices in low cost BCD (Bipolar CMOS DM03) semiconductor fabrication processes, and have relatively low parasitic capacitance values. In comparison, bipolar transistors have much higher power due to biasing currents needed, and high voltage MOS (Metal Oxide Semiconductor) transistors have much higher resistance per unit area.

Another such additional feature is the driver circuit having a timing control circuit for each of the switching transistors configured to switch off the switching transistor during a leading edge of the common drive signal. See Figures 4, 5 and 8 for example. The body diode or Schottky or other diode has the advantage that it can be used to "rejoin" the voltage on the actuator with the cold switch waveform without exact timing or a current pulse.

Another such additional feature is the timing control circuit being configured to switch on the switching transistor during a trailing edge of the common drive signal. This can help reduce power dissipation by reducing an amount of conduction through the body diode. The body diode is still useful to enable a precisely timed start to the conduction on the trailing edge, and therefore helps reduce or avoid the need for complex or expensive timing circuitry for precise control of switch on of the switching transistor. See Figures 4, Sand 8 for example.

Another such additional feature is an additional diode, Silicon or Schottky type, coupled in parallel with the body diode to provide an additional conduction path in parallel with the body diode. This can help reduce power dissipation since there is more freedom to choose characteristics of the additional diode to optimise power dissipation, or forward voltage characteristic. See Figure 12 for example.

Another such additional feature is the driver circuit being configured to receive a print signal representing a desired print level, and having control circuitry for controlling the switching transistor according to the print level. This can enable greyscale control with relatively little additional circuitry. See Figures 6, 7 and 8 for example.

Another such additional feature is the switching transistor being configured to have direct drive by a digital logic level control signal. This enables a relatively straightforward circuit implementation by avoiding the need for high voltage level shift circuitry. This can help avoid the power dissipation caused by such high voltage circuitry. See Figure 3 or Figure 5

for example.

Another such additional feature is a logic level shift circuit for converting a logic signal from a lower logic voltage level to a higher logic voltage level for controlling the switching transistor. This can enable power dissipation reduction by using lower voltage level logic for any control circuitry independently of the logic voltage level used to control the switching transistor, and therefore independently of the technology used for the switch. This is useful to meet the different limitations of the switch. See Figure 8 for example.

Another aspect provides a printer having any of the printheads as set out above, and a common drive signal amplifier external to the printhead and coupled to provide the common drive signal to the first electrodes on the printhead. This combination with the so called cold switch arrangement is especially advantageous to enable further reductions in power dissipation in the printhead. See Figure 11 for example.

Another aspect provides an integrated circuit having a driver circuit for use in any of the printheads set out above, the driver circuit having an interface pad for receiving the print signal, and having interface pads for coupling in series between the second electrode and the return path, the driver circuit also having an n-channel switching transistor having a drain coupled to the second electrode, and a source coupled to the return path, and operable according to the print signal, to couple the second electrode to the return path to drive the actuating element, the switching transistor being configured to have an open drain such that when the switching transistor is not conducting, a voltage between the first and second electrodes is unaffected by changes in a voltage on the first electrode, and the switching transistor having a body diode or similar functionality source to drain diode providing a conduction path to a substrate of the switching transistor when a voltage between the second electrode and the substrate becomes negative by more than a threshold, to enable a voltage between the first and second electrodes to follow changes in the voltage on the first electrode.

Another aspect provides a method of operating a printer having a printhead comprising a plurality of actuating elements, and a driver circuit for each of the actuating elements, the actuating elements each having at least a first electrode for receiving a common drive signal, and a second electrode for coupling to a return path forthe common drive signal, the driver circuit having an input for a print signal, and having an n-channel switching transistor having a drain coupled to the second electrode, and a source coupled to the return path, and operable according to the print signal, to couple the second electrode to the return path to drive the actuating element, the switching transistor being configured to have an open drain, and the switching transistor having a body diode providing a conduction path to a substrate of the switching transistor, the method having the steps of: providing the common drive signal as a positive voltage waveform with inverted pulses having an upgoing leading edge and a downgoing trailing edge and switching the switching transistor according to the print signal so that it is on during at least part of the leading edge so that a voltage across the actuating element follows at least part of the leading edge, using the body diode or similar functionality source to drain diode to conduct when the switching transistor is off if a voltage between the second electrode and the substrate becomes negative by more than a threshold to enable a voltage between the first and second electrodes to follow changes in the common drive signal on the first electrode.

Numerous other variations and modifications can be made without departing from the claims of the present invention. Therefore, it should be clearly understood that the form of the present invention is illustrative only and is not intended to limit the scope of the present invention.

Brief DescriDtion of the Drawings How the present invention may be put into effect will now be described by way of example with reference to the appended drawings, in which: Figure 1 shows a schematic view of a printhead according to an embodiment, Figure 2 shows a schematic view of printer circuitry and a printhead according to an embodiment, Figure 3 shows a timing diagram of signals during operation of the embodiments, Figure 4 shows a schematic view of a printhead according to an embodiment having a timing circuit, Figure 5 shows a timing diagram of signals during operation of an embodiment having timing control for trimming, Figure 6 shows a schematic view of an embodiment having a greyscale circuit, Figure 7 shows a timing diagram of signals during operation of an embodiment having timing control for greyscale processing, Figure 8 shows a schematic view of an embodiment having timing control for greyscale and trimming, Figure 9 shows a schematic view of an embodiment having a logic level shifter, and Figure 10 shows a schematic view of an embodiment having a printhead having ASIC and MEMS parts, Figure 11 shows a schematic view of a printer according to an embodiment having a printhead, and Figure 12 shows a schematic view of an embodiment having additional diodes in parallel with the switching transistor.

Detailed Description

The present invention will be described with respect to particular embodiments and with reference to drawings but note that the invention is not limited to features described, but only by the claims. The drawings described are only schematic and are non-limiting. In the drawings, the size of some of the elements may be exaggerated and not drawn to scale for illustrative purposes.

Definitions: Where the term "comprising" is used in the present description and claims, it does not exclude other elements or steps and should not be interpreted as being restricted to the means listed thereafter. Where an indefinite or definite article is used when referring to a singular noun e.g. "a" or "an", "the", this includes a plural of that noun unless something else is specifically stated.

References to programs or software can encompass any type of programs in any language executable directly or indirectly on any computer.

References to a computer are intended to encompass any kind of processing hardware which can be implemented in any kind of logic or analog circuitry, integrated to any degree, and not limited to general purpose processors, digital signal processors, ASICs, (Application Specific Integrated Circuits) FPGAs (Field Programmable Gate Arrays), discrete components or logic and so on, and are intended to encompass implementations using multiple processors which may be integrated together, or co-located or distributed at different locations for example.

References to actuating chambers are intended to encompass any kind of actuating chamber comprising one or more actuating elements for effecting the ejection of droplets from at least one nozzle that is associated with the actuating chamber. The actuating chamber may eject any kind of fluid from at least one fluid reservoir for printing 2D images or 3D objects for example, onto any kind of media, the actuating chambers having actuating elements for causing droplet ejection in response to an applied electrical voltage or current, and the actuating chambers representing any type of suitable configuration of the geometry between its actuating element(s) and nozzle(s) to eject droplets, such as for example but not limited to roof mode or shared wall geometry.

References to actuating elements are intended to encompass any kind of actuating element to cause the ejection of droplets from the actuating chamber, including but not limited to piezoelectric actuating elements typically having a predominantly capacitive circuit characteristic or electro thermal actuating elements typically having a predominantly resistive circuit chalacteristic. Furthermore, the arrangement and/or dimensions of the actuating element are not limited to any particular geometry or design, and in the case of a piezoelectric element may take the form of, for example, thin film, thick film, shared wall, or the like. The actuating element is sometimes referred to generally as a nozzle.

References to groups or sets of the actuating elements are intended to encompass linear arrays of neighbouring actuating elements, or 2-dimensional rectangles or other patterns of neighbouring actuating elements, or any pattern or arrangement, regular or irregular or random, of neighbouring or non-neighbouring actuating elements.

Figure 1, printhead according to embodiment Figure 1 shows a schematic view of a printhead 97 according to an embodiment. This shows actuating elements (1,2), and a driver circuit (100) for each of the actuating elements, the actuating elements each having at least a first electrode (40) for receiving a common drive signal, and a second electrode (50) for coupling to a return path for the common drive signal.

The dashed lines on the right of the figure indicate the possibility of repeating components for additional actuating elements.

This and other embodiments are based on driving actuators from a common drive waveform using a driver circuit 100 having an n-channel switching transistor 32, also known as a demux switch. A plurality of actuating elements 1, 2 are shown which can be piezoelectric and have first and second electrodes 40, 50 to enable the actuating element to be driven to carry out the printing according to a print signal for each actuating element. The electric potential across the electrodes is controlled by a common drive signal, which provides for example a regular waveform of pulses having a shape suitable for the desired printing, and to suit characteristics of the actuating elements. The switching transistor 32 controls when the common drive signal is applied across the actuating element, according to a print signal which indicates which pixels are to be printed and is coupled directly or optionally via further circuitry (examples are described below with respect to Figures 5 and 6) to the gate of the switching transistor. The switching transistor (32) has a drain coupled to the second electrode, and a source coupled to the return path, to couple the second electrode to the return path to drive the actuating element.

Notably the switching transistor is coupled in the return path, at the side of the second electrode, rather than at the side of the first electrode and the common drive signal. This configuration helps enable the switch control to be implemented using lower voltage or simpler components than would be needed if the switch is at the side of the common drive signal, where typically a high voltage level shifter is needed for example. This can help reduce power dissipation and reduce circuit size and costs. This is particularly the case where the print signal is a logic signal and where the switch can be directly driven by the logic signal without needing a high voltage level shifter circuit.

Although two actuators are shown there can be many, typically arranged in a linear array or set of arrays to enable a line across a page to be printed. The printer can have a mechanism to move the page perpendicular to the array, so that the entire page can be printed. The simpler circuitry and reduced power dissipation can become more important in such printheads where there are many actuating elements.

Figure 2, Printer circuitry and printhead Figure 2 shows a schematic view of an example of parts of a printer including the printhead 97 of Figure 1 and other parts of the printhead, for generating the common drive signal and the print signal. In some embodiments these can be integrated onto the printhead, but a benefit of having them external to the printhead is that power dissipation on the printhead can be reduced. This is known as a cold switch arrangement.

This "Cold Switch" technique reduces the amount of thermal dissipation on the printhead, moving much of the thermal dissipation onto a higher level circuit board for providing signals common to many printheads, such as the printer circuitry 170. This is a standard piezo printhead technique, used in the majority of industrial piezo printhead systems today, as well as other devices. This thermal dissipation shift is achieved by generating a common power drive waveform on the printer circuitry, and switching it to individual actuating elements on the printhead only during times at which the waveform is not transitioning, and hence not causing current flow in or out of the capacitive load of the actuating elements during switch opening or closing. Figure 2 illustrates the concept of cold switch drive, with arrows illustrating the location of substantial thermal dissipation.

In practice, the switching transistor 32 in the printhead ASIC has thermal dissipation, from the finite resistance of the switch used in it and for the dissipation in the level shifter used to control the switch. Typically, there is a trade-off between reducing the switch resistance for improved thermals and silicon area cost. The industrial printhead industry uses this technique due to the high cost of removing heat from the printhead. In Figure 2, the printer circuitry is provided external to the printhead, having a circuit such as an FPGA 120 for generating print signals for each actuator at appropriate timings. These print signals can be logic level signals representing pixel information in any way, coded or otherwise, and in black/white, or grey scale or colour and so on. These logic signals can be generated by the FPGA based on a file of digital information such as character codes and character positions for the page to be printed for example, fed to the printer from a PC, network, or any external source for example.

The same FPGA can also have an output to generate the common drive signal. This logic output is fed to a DAC 150, which produces an analog output which is fed to an amplifier 140 for generating sufficient power at high voltage (e.g. 40v) to drive the actuators. A DC power supply 130 is also shown. The common return path is coupled to the amplifier and to the DC power supply. The printhead 97 is shown implemented as an ASIC 82 and a MEMS 105.

The ASIC 82 incorporates the driver circuit 100 and switching transistor 32 or switches for each actuating element. The MEMS incorporates the actuating element 1,2, or array of such actuating elements. The common drive signal is fed to the actuating elements from the printer circuitry 170, and the return path is fed from the actuating elements to the printer circuitry 170 via the switching transistor 32 on the ASIC 82. There may be other parts incorporated on the ASIC.

Figure 3, Switch Operation according to an embodiment The common drive waveform is supplied by the printer circuitry 170, as a cold switch system would provide. This drive waveform is driven onto the common first electrode of the actuating element. When the actuating elements are switched on, the individual second electrodes remain near ground potential, with only a small <1V potential determined by the current and LDMOS switch resistance in the ASIC. When it is desired to not fire an actuating element (it is off), the second electrode will float and then no current will flow in or out of it, except from parasitic capacitance of the n-LDMOS in the ASIC. The drain voltage of that switching transistor will then closely follow the swing of the cold switch waveform, which is driven onto the common first electrode. In this off state, very little current will flow through the electrode, except that provided by the parasitic capacitance of the n-LDMOS in the ASIC. Some crosstalk to unfired actuating elements can be caused by parasitic capacitances in leads, flex connectors & ASIC paths for example.

Figure 3 shows a simulation output for an embodiment, showing voltage on the y axis and time on the x axis. The common drive waveform is represented by V(die_com_b) which is the trace at the bottom of the graph, as driven by the external cold switch waveform driver described above with respect to Figure 2. In this embodiment the voltage at the second electrode of an actuating element for aqueous fluid is V(per_nozzle_b) and the voltage at the second electrode of an actuating element for a UV fluid is shown as V(per_Nozzle_c). These electrode voltages are almost identical and overlaid on each other as the central waveform in Figure 3. Note that the 7 ohm resistance of the n-LDMOS (in this example) is noticeable in the difference in peak voltage between designs for UV and aqueous inks, which have different capacitance in their actuating elements, this can be seen at about 3.Sus and 5.2us.

The upper trace (V(potential_on_actuator_b) shows the potential across the actuator which is the difference between the V(per_Nozzle_b) and V(die_com_b) which is the resulting net potential difference across the actuating element. This shows how the actuating elements are turned on only for half of the pulses driven onto the common first electrode in this example. Note that for this simulation the control signal is configured to make the switch open circuit for the first pulse, so the net potential difference across the actuating element remains approximately constant. For the second pulse, the switch is closed during the first transition, so the second electrode is held to zero and does not follow the first transition. The switch can be made open during the peak of the second pulse, then closed again during the second transition of the second pulse, so that it does not follow that transition. Afterwards the switch can be opened again.

The ASIC pad only sees positive voltages (unless there is a fault to the common electrode).

Die failure is a risk if there is an actuator fault that causes a large negative voltage on the actuator pad. At transitions, depending on design choices, an enabled actuating element could see a negative voltage that is large enough to turn on the body diode or similar functionality source to drain diode in the switching device. This may be acceptable depending on the process specifications, and suitable care in design and layout of the ASIC can ensure no latch up results from current flow in this body diode or similar functionality source to drain diode.

As mentioned above, any resistive and capacitive parasitics in the [DM03 device, and in the flex cross coupling capacitance creates voltage bumps" experienced by actuating elements that are supposed to be not firing, see Figure 3, 3.2us and 5.5us, central trace.

The MEMS should have the ability to tolerate these bumps".

Keeper and Idle Bias Deselected actuating elements can have their charge maintained using some type of keeper interval or a keeper circuit. When an actuating element is not being fired, its bias voltage is required to stay at a certain level. The piezo devices can be actuated by reducing a field during a pulse. So when idle, the actuating elements have an electrical bias voltage and have the largest voltage (and field) that they will experience. Leakage in the actuating element and through the ASIC devices will alter the idle bias on an actuating element if it is not kept or refreshed in some manner. Some designs have used a keeper transistor that switches any idle actuating elements to a bias net provided on the ASIC. But while this is feasible for the pass gate cold switch solutions, an open drain solution does not have the topology that allows this, due to the requirement to float deselected actuating elements. For open drain, a digital function to turn the actuating element on during some idle period once per pixel cycle should be sufficient to maintain the proper bias on a completely idle actuating element, the "keeper interval." Figure 5, timing diagram of common drive waveform with trimming example Figure 5 shows a single pulse of the common drive waveform showing the effect of controlling the timing of switching to achieve trimming of pulse height. This shows a cold switch driver (also referred to as common drive) waveform as a positive voltage waveform with inverted pulses having a downgoing leading edge and an upgoing trailing edge. A dotted line A-B shows the effect of trimming the voltage level by 25v rather than the untrimmed 35v. These voltages can be selected according to the type of actuating element. In this case the pulse slopes are 300ns long though other values can be chosen. Below is a corresponding waveform of the switch state which corresponds to the control provided by the further trim signal. When the switch is on, the voltage across the actuating element will follow the common drive waveform. When the switch state is off, the voltage across the actuating element will remain roughly constant. Hence in the example shown, the switch is on for most of the downgoing slope, until the waveform has changed by 25v, at point A. Then the switch is switched off, at a timing controlled according to the trim signal. This means the voltage across the actuating element follows the dotted line, rather than following the solid line.

At point B, the switch state changes to the on state. The voltage across the actuating element follows the upgoing slope of the common drive waveform. At point B if the timing of switch on is not exact, there may be a negative voltage between the second electrode and the substrate. This can exceed the threshold which causes conduction of the body diode or similar functionality source to drain diode. This conduction can be useful to enable the voltage across the actuating element to follow the common drive signal even before the switching transistor is switched on. In fact it is possible to use the body diode or similar functionality source to drain diode conduction for the trailing edge without switching on the switching transistor at all. This would typically cause more thermal dissipation, so there is still some benefit in using the switching transistor to conduct for at least some of the trailing edge. The body diode or similar functionality source to drain diode conduction still enables a significant simplification in the timing circuitry since it is no longer necessary to have precise timing of the switch on of the switching transistor for the trailing edge.

Figure 6, embodiment having greyscale circuitry Figure 6 shows a schematic view of a printhead according to an embodiment similar to that of Figure 4 but showing the driver circuit 100 having greyscale circuitry (79) for processing the print signal. In this case the print signal represents a desired print level, such as having some indication of greyscale, which can encompass colour or colour saturation for example.

The greyscale circuitry can enable the switching of the switching transistor to be controlled according to the desired print level. This can be implemented in various ways, for example by modulating over a number of common drive waveform pulses as will be explained in more detail below with reference to Figure 7. In principle the modulation can be made with or without any timing control. If with timing control, then in principle it can be made after timing control has been generated, or can be used to selectively switch off any timing control circuitry. An example where the greyscale control is implemented by logical combination with a timing signal is explained below in more detail with reference to Figure 8.

Figure 7, Waveforms for Greyscale, Per Pixel and Per Sub-Drop The ASIC controls the switch to provide the externally provided drive signal waveform as a voltage differential across each actuating element during pre-programmed time intervals based on the print signal. The waveform will agitate the ink in the actuating chamber, causing a certain amount of ink to be ejected from the nozzle and deposited in certain pixel locations on the media, building up the image. The print data may demand more than one drop to be ejected from the nozzle for arrival at one pixel location. Each of these ink drops is called a "sub-drop". The two most significant time intervals for this function are the sub-drop period and the pixel period. The pixel period is the time taken for a media pixel to progress past the selected nozzle. The sub-drop period is the time allocated for firing each individual sub-drop.

The ASIC will be able to handle from one to seven sub-drops per pixel period, plus an optional damping period. The damping period fires an off phase pulse only if jetting pulses are fired, to reduce the residual energy in the MEMS for the next pixel.

Figure 7 shows example actuator waveforms for a system with up to three sub-drops per pixel fired plus the damping pulse. Slew rate, pulse width and maximum pulse height are set externally to the ASIC, by the externally generated common drive waveform. In Figure 7, the top waveform, marked "no drops" shows the case of no firing. This has a greyscale value of "0." The second from top waveform, marked "one drop", shows the case of one sub-drop firing, showing an ejection level pulse in the first sub-drop period and a damping pulse in the damping period. This has a greyscale value of "1." The third from top waveform, marked "two drops" shows the case of two sub-drops firing, showing an ejection level pulse in the first sub-drop and second sub-drop period and a damping pulse in the damping period. This has a grayscale value of "2". The bottom waveform, marked "three drops" shows the case of three sub-drops firing, showing an ejection level pulse in the first drop, second and third sub-drop periods and a damping pulse in the damping period. This has a greyscale value of"3". The sub-drops can be arranged to land on the same place and rely on the total quantity of ink to show the different greyscale, or in principle the media can be moved to offset slightly the sub-drops to cause more or less spread in the shape of the ink-spot according to which sub-drops are fired. If the common drive waveform has sub-drops with different peak voltages, as shown, then the amounts of ink in each sub-drop will be different, and so up to 8 different greyscales for a pixel can be achieved from different combinations of the three sub-drops.

In some embodiments, the printhead ASIC can handle the logic to implement greyscales by generating pulses to create the sub-drops, but in other embodiments this logic may be implemented by external off-printhead logic and the ASIC merely receives data for a series of sub-drops being demanded; the ASIC would not then need to determine which sub-drops make up which drop. In particular embodiments each nozzle can support up to 3 bits! 8 levels of greyscale, from 0 (no drop fired) to 7 drops fired. In particular embodiments it will be possible to run with 1, 2 and 3 bits of greyscale, depending on greyscale mode. Different modes of operation will require different numbers of bits of greyscale from 1 bit (either a drop or no drop) to a full 3 bits and 7 greyscale levels (any combination of 3 sub-drops).

Figure 8, printhead according to an embodiment having preyscale and timing control for trimming Figure 8 shows a schematic view of a printhead according to an embodiment. This has some features similar to the embodiments of Figure 4 and 6 and shows some features and options in more detail. As before, a common drive signal is coupled to an actuating element 1, and the common return is coupled via a switching transistor 32. In this case the control circuit 70 is shown in the form of switch logic 72, LVDS shift registers 84, and timing circuitry including a timer 74 and optionally a fixed trimming timing part 76 for compensating for manufacturing variations. The body diode or similar functionality source to drain diode is used to advantage in trimming, as discussed above. These logic parts and the switching transistor 32 can be implemented as shown on an ASIC 82. As indicated, one instance of the LVDS/Shift registers 84 is provided common to all actuating elements, while the other parts of the ASIC, that is the switching transistor 32, switch logic 72, and timing circuitry including a timer 74 and fixed trimming timing 76, are provided one set for each actuator. The LVDS/shift registers 84 can be arranged to demultiplex print signals such as pixel greyscale for each actuating element, and can pass on any dynamic timing information for trimming the timer part 74.

Outside the ASIC is shown an LVDS interface 86 for coupling logic input signals into the ASIC from for example the FPGA 120 in the printer circuitry 170 shown in Figure 2. These input signals can include print signals such as pixel values in the form of greyscale values for example, for each actuating element in an array, and optionally any dynamic trimming timing information which may help ensure more consistent and accurate printing. In principle the adjustments can be made in terms of pulse shape, or peak voltage difference of the pulse. If the drive waveform has ramped transitions then a change in timing can result in more or less of the ramp appearing as a voltage difference, and this can appear effectively as a change in peak voltage difference across the actuator. Note that the timing of the switching and also the finer timing for trimming should be synchronized with the media motion encoder driven timing; this is typically handled off ASIC and then synchronisation signals are provided to the timer part 74 on the ASIC as shown. The ASIC can baseline its timing from the provided LVDS clock and the start bits for each print I compensation data packet for

example.

Figure 9, Printhead according to an embodiment with logic level shift Figure 9 shows a schematic view of a printhead according to an embodiment similar to that of Figure 4 but showing a logic level shift circuit 79 for shifting a logic level of the print signal to a higher level for coupling to the gate of the switching transistor. The switching transistor 32 is still directly driven by a logic level, but the logic level shift circuit enables a different logic level to be used for the control circuit, while avoiding the need for a high voltage level shift circuit having current sources for example. In one example this low voltage level shifter can shift from a very low voltage of 1.8V used by logic circuitry, to the example 5V gate to source voltage of a typical n-LDMOS that can be used for this application. This type of level shifter is very low cost and can draw no or small static power. It may have a limitation in that ohmic driven voltage rise in the current returning conductor connected to the source of the n- [DM03 will reduce the Vgs (Voltage gate to Source) of the n-[DMOS, and thus increase its on-resistance and thermal dissipation. Designers of such a system will anticipate this and increase the size (and area) of the n-LDMOS to compensate. This will increase the cost of the system.

Another possible implementation is to use not just a low voltage level shifter, which by definition outputs a maximum voltage similar to that of the total maximum Vgs of the LDMOS, but a medium, high or higher voltage level shifter, all of which by definition output voltages in excess of the maximum Vgs of the switching LDMOS. (For comparison, the so-called high voltage level shifters in the conventional pass gate architecture have to be able to output the maximum waveform voltage plus the voltage needed to switch on the n-LDMOS, the Vgs.

Typically this is on the order of 40V, and this span multiplied by the current needed is a large power dissipation in the printhead.) To reduce or remove the degradation of n-[DMOS performance by low Vgs due to source voltage rise, a medium voltage level shifter could be used. Typically, this would be capable of supplying 8-12V onto the gate of the n-LDMOS. In this way, a very large rise in source voltage can be tolerated.

Thus some particular embodiments use a cold switch driver using only one power device, a single or sole transistor such as an n-LDMOS. This implementation enables a cold switch drive IC without needing a high voltage level shifter since the source terminal of the n-LDMOS is connected to power ground and the gate can then be driven using 0-3.3V (for 0.35um processes) orO.5V (for 0.l8um processes). In some cases, there may be a difference in logic levels between the logic level of the print signal and the logic level needed for direct drive of the transistor in the return path, in which case a logic level shifter could be used, which could be very small in chip area (and cost). In either case, since a high voltage level shifter no longer has to be used to drive the [DM05, this still reduces the area, power dissipation and complexity compared to a cold switch demux IC having a level shifter to translate 0-3.3V logic level to 0-40V to supply the gate drive current for the large power devices. It is compatible with a single waveform cold switch type system.

The driver circuit can include logic for timing of the switching and for demultiplexing individual print signals from a multiplexed signal, if it is desired to limit the number of physical connections between the printer circuitry 170 shown in Figure 2 and the printhead.

Figure 10, printhead embodiment using open drain switch Figure 10 shows a schematic view of an embodiment of a printhead having a MEMS 105 and an ASIC 82. An array of actuating elements is shown in the MEMS. Optionally there are unused actuating elements at the ends, for the case that these would be harder to operate consistently with the other actuating elements. This is because in some cases the MEMS structures for the actuating chambers have inlets and optionally outlets, for ink, and these are coupled to a plenum which supplies ink to the inlets and removes ink (from the outlets if recirculating). If there were no "dummy" actuating elements, the last one would only have one inlet and possibly outlet, next to it in the plenum, instead of two adjacents, making its print performance slightly different. Hence the end of row dummy actuating elements. This can apply in thermal as well as piezo inkjet systems.

Each of the operational actuating elements has a return path connected to a drain of a respective n-[DMOS device 62. The source of each device is connected to ground (ASIC power ground, -0V system potential). This means that the logic signals can be directly connected (or almost directly) connected to drive the gate of the n-[DMOS. There is no high voltage level shifter, which otherwise would use significant power and significant die area to level shift to a floating pass gate made of LDMOS. (Note that the level shifter power consumption is mainly due to the need to use current sources to bias the [DM05 gate as it floats, because the LDMOS gate oxide will have a voltage limitation and will be clamped to 3.3V or 5V. Bias current multiplied by the 30-40V high voltage supplied to the die can be a significant power use.) If the ASIC core is lower voltage than the LDMOS gate oxide allows, a small, low power, low voltage level shifter (as described above with reference to Figure 9) can be used to raise the gate drive signal from a core voltage of 1.3-1.8V to the LDMOS gate voltage of 3.3-5V. LDMOS gate voltage is larger because of the large source voltage rise that these devices typically experience due to the ohmic resistance of their power ground supply system, and a larger overall gate voltage allows this source voltage rise to become relatively less significant. Note that for this reason, a 5V [DM05 gate oxide is preferable, allowing generally smaller power ground width on the die.

The ASIC has a control circuit in the form of a digital logic block 71 with outputs to drive a gate of each n-LDMOS device directly. The digital logic block has inputs of power lines for logic and for low voltage [V analog, and an Input Output 10 bus command and status input, (for [VDS or 12C like) (Inter-Integrated Circuit, referred to as I-squared-C, I-two-C, or IIC is a multimaster serial single-ended computer bus used for attaching low-speed peripherals to a motherboard, embedded system, cellphone, or other digital electronic devices) and Data and Clock [VDS pairs. The digital logic block can process the print signal to provide the outputs to drive the actuators, and can implement per nozzle compensation or configuration.

The bidirectional communication link (such as 12C) may be used to allow read/write of control and status registers in the ASIC. 12C can set the mode using resister writes, modes such as test, idle, print, stop, and also allows reading of temperature, and sometimes die voltage measurements through register reads.

In a typical example the ASIC is arranged to drive 300 printhead actuating elements from a common power drive waveform via the per actuating element switching transistor, and externally generated waveforms will be generated off-ASIC and provided to the ASIC as inputs. The ASIC has inputs for print data to select which MEMS actuating elements are to receive the waveform pulses (i.e. which switches to switch on), and real time voltage trim data to adjust the voltage of these pulses. Data transfer to the ASIC can be via a single 300 Mbps LVDS differential pair with separate clock differential pair for example.

Figure 10 also shows inputs to the MEMS including the common drive signal in the form of a common electrode cold switch waveform, and an example is described above with reference to Figure 2 or FigureS. The MEMS can also have a heating resistor 65, and a corresponding sense resistor 67 for use by an external heating controller, for maintaining the MEMS on the printhead at a consistent operating temperature. Also shown is a NV (non volatile) memory 68, coupled to a serial connector, for use in storing configuration data for example, and this can be secured as desired using established techniques.

Figure 11 embodiment showing printer features The printhead embodiments described above can be used in various types of printer. Two notable types of printer are: a) a page-wide printer (where printheads in a single pass cover the entire width of the print medium, with the print medium (tiles, paper, fabric, or other example, in one piece or multiple pieces for example) passing in the direction of printing underneath the printheads), and b) a scanning printer (where one or more printheads pass back and forth on a printbar (or more than one printbar, for example arranged one behind the other in the direction of motion of the print medium), perpendicular to the direction of movement of the print medium, whilst the print medium advances in increments under the printheads, and being stationary whilst the printhead scans across).

There can be large numbers of printheads moving back and forth in this type of arrangement, for example 16 or 32, or other numbers.

In both scenarios, the printheads may be mounted on printbar(s) to print several different fluids, such as but not limited to, different colours, primers, fixatives, functional fluids or other special fluids or materials. Different fluids may be ejected from the same printhead, or separate printheads or printbars may be provided for each fluid or each colour for example.

Other types of printer can include 3D printers for printing fluids comprising polymer, metal, ceramic particles or other materials in successive layers to create solid objects, or to build up layers of an ink that has special properties, for example to build up conducting layers on a substrate for printing electronic circuits and the like. Post-processing operations can be provided to cause conductive particles to adhere to the pattern to form such circuits.

Figure 11 shows a schematic view of a printer 440 coupled to a source of data for printing, such as a host PC 460 (which can be external or internal to the printer). The printhead of Figure 1 corresponds to printhead circuit board 180 having one or more actuating element 1 and a driver circuit 100. Printer circuitry 170 is coupled to the printhead circuit board, and coupled to a processor 430 for interfacing with the host, and for synchronizing drive of actuating elements and location of the print media. This processor is coupled to receive data from the host, and is coupled to the printhead circuit board to provide synchronizing signals at least. The printer also has a fluid supply system 420 coupled to the printhead, and a media transport mechanism and control part 400, for locating the print medium 410 relative to the printhead. This can include any mechanism for moving the printhead, such as a movable printbar. Again this part can be coupled to the processor to pass synchronizing signals and for example position sensing information. A power supply 450 is also shown, for supplying power to the various parts of the printer (supply connections are omitted from the figure for the sake of clarity).

The printer can have a number (for example 16 or 32 or other numbers) of inkjet printheads attached to a rigid frame, commonly known as a print bar. The media transport mechanism can move the print medium beneath or adjacent the print bar. A variety of print media may be suitable for use with the apparatus, such as paper sheets, boxes and other packaging, or ceramic tiles. Further, the print media need not be provided as discrete articles, but may be provided as a continuous web that may be divided into separate articles following the printing process.

The printheads may each provide an array of actuating chambers having respective actuating elements for ink droplet ejection. The actuating elements may be spaced evenly in a linear array. The printheads can be positioned such that the actuating element arrays extend perpendicular to the motion and also such that the actuating element arrays overlap in the direction perpendicular to the direction of motion. Further, the actuating element arrays may overlap such that the printheads together provide an array of actuating elements that are evenly spaced in the width direction (though groups within this array, corresponding to the individual printheads, can be offset in the direction of motion). This may allow the entire width of the substrate to be addressed by the printheads in a single printing pass.

The printer can have circuitry for processing and supplying image data to the printheads. The input from a host PC for example may be a complete image made up of an array of pixels, with each pixel having a tone value selected from a number of tone levels, for example from 0 to 255. In the case of a colour image there may be a number of tone values associated with each pixel: one for each colour. For example, in the case of CMYK printing there will therefore be four values associated with each pixel, with tone levels 0 to 255 being available for each of the colours.

Typically, the printheads will not be able to reproduce the same number of tone values for each printed pixel as for the image data pixels. For example, even fairly advanced greyscale printers (which term refers to printers able to print dots of variable size, rather than implying an inability to print colour images) will only be capable of producing 8 tone levels per printed pixel. The printer may therefore convert the image data for the original image to a format suitable for printing, for example using a half-toning or screening algorithm. As part of the same or a separate process, it may also divide the image data into individual portions corresponding to the portions to be printed by the respective printheads. These packets of print data may then be sent to the printheads.

The fluid supply system can provide ink to each of the printheads, for example by means of conduits attached to the rear of each printhead. In some cases, two conduits may be attached to each printhead so that in use a flow of ink through the printhead may be set up, with one conduit supplying ink to the printhead and the other conduit drawing ink away from the printhead.

In addition to being operable to advance the print articles beneath the print bar, the media transport mechanism may include a product detection sensor (not shown), which ascertains whether the medium is present and, if so, may determine its location. The sensor may utilise any suitable detection technology, such as magnetic, infra-red, or optical detection in order to ascertain the presence and location of the substrate.

The print-medium transport mechanism may further include an encoder (also not shown), such as a rotary or shaft encoder, which senses the movement of the print-medium transport mechanism, and thus the substrate itself. The encoder may operate by producing a pulse signal indicating the movement of the substrate by each millimetre. The Product Detect and Encoder signals generated by these sensors may therefore indicate to the printheads the start of the substrate and the relative motion between the printheads and the substrate.

The processor can be used for overall control of the printer systems. This may therefore co-ordinate the actions of each subsystem within the printer so as to ensure its proper functioning. It may, for example signal the ink supply system to enter a start-up mode in order to prepare for the initiation of a printing operation and once it has received a signal from the ink supply system that the start-up process has been completed it may signal the other systems within the printer, such as the data transfer system and the substrate transport system, to carry out tasks so as to begin the printing operation.

Figure 12 embodiment with additional diode Figure 12 shows an embodiment similar to that of Figure 4 but showing an additional diode 42 coupled between the drain and source of the switching transistor, to conduct in parallel with the body diode, or instead of the body diode if there is no body diode. This can help reduce power dissipation since there is more freedom to choose characteristics of the additional diode to optimise power dissipation or forward voltage characteristic. This feature can be combined with any of the other features of embodiments described above.

Concluding remarks For the purpose of explaining the significance of some features of embodiments, a brief comparison will be made to a reference example without the feature of the common drive signal being coupled to the first electrode. So in this case the switches would not be in the common return path, but on the same side of the actuating elements as the drive signal. This means the switches do need a high voltage level shifter and cannot be arranged using a single transistor, or in an open drain configuration. Instead a pass gate pair of high voltage LDMOS transistors could be used for each actuating element. This requires a high voltage level shifter to shift the on/off signal from the logic level up to the level that the source terminal of the LDMOS is operating at. This also needs a much larger area for LDMOS due to the need to have two of the devices in series to form a pass gate.

As has been described, various embodiments can provide for lower cost devices through lower power dissipation in the printhead or a smaller size ASIC. In some cases only one high voltage switch device is used per nozzle vs. two large power devices and multiple high voltage level shifter devices for a cold switch demux. In some cases the switching transistor is a single LDMOS device driven directly with logic levels. This can keep the printhead cost to a minimum. This was conceived based on the insight that a rearrangement of the circuit could provide switching of the return path rather than the drive signal so that when the n-LDMOS was switched off, the voltage at the second electrode could rise during pulses, but not go negative beyond an acceptable threshold.

Other embodiments and variations can be envisaged within the scope of the claims.

Claims

Claims 1. A printhead (97) comprising a plurality of actuating elements (1,2), and a driver circuit (100) for each of the actuating elements, the actuating elements each having at least a first electrode (40) for receiving a common drive signal, and a second electrode (50) for coupling to a return path for the common drive signal, the driver circuit having an input for a print signal, and having an n-channel switching transistor (32) having a drain coupled to the second electrode, and a source coupled to the return path, and operable according to the print signal, to couple the second electrode to the return path to drive the actuating element, the switching transistor being configured to have an open drain such that when the switching transistor is not conducting, a voltage between the first and second electrodes is unaffected by changes in the common drive signal on the first electrode, and the switching transistor having a body diode or similar functionality source to drain diode providing a conduction path to a substrate of the switching transistor when a voltage between the second electrode and the substrate becomes negative by more than a threshold, to enable a voltage between the first and second electrodes to follow changes in the common drive signal on the first electrode.
2. The printhead of claim 1, the switching transistor comprising an LDMOS transistor.
3. The printhead of claim 1 or 2, the driver circuit having a timing control circuit (10, 72, 74, 76) for each of the switching transistors configured to switch off the switching transistor during a leading edge of the common drive signal.
4. The printhead of claim 3, the timing control circuit (10, 72, 74, 76) being configured to switch on the switching transistor during a trailing edge of the common drive signal.
5. The printhead of any preceding claim, the driver circuit having an additional diode (42) coupled in parallel with the switching transistor to provide the desired conduction path characteristics in parallel with the body diode or from drain to source of a switching transistor that does not have a body diode.
6. The printhead of any preceding claim, the driver circuit being configured to receive a print signal representing a desired print level, and having greyscale circuitry (33) for controlling the switching transistor according to the print level.
7. The printhead of any preceding claim, the switching transistor being configured to have direct drive by a digital logic level control signal.
8. The printhead of any of claims ito 6, the driver circuit comprising a logic level shift circuit (79) for converting a logic signal from a lower logic voltage level to a higher logic voltage level for controlling the switching transistor.
9. A printer (440) having the printhead of any preceding claim, and a common drive signal amplifier external to the printhead and coupled to provide the common drive signal to the first electrodes on the printhead.
i0. An integrated circuit (82) having a driver circuit (100) for use in the printhead of any of claims ito 8, the driver circuit having an interface pad for receiving the print signal, and having interface pads for coupling in series between the second electrode and the return path, the driver circuit also having an n-channel switching transistor (32) having a drain coupled to the second electrode, and a source coupled to the return path, and operable according to the print signal, to couple the second electrode to the return path to drive the actuating element, the switching transistor being configured to have an open drain such that when the switching tiansistor is not conducting, a voltage between the first and second electrodes is unaffected by changes in a voltage on the first electrode, and the switching transistor having a body diode or similar functionality source to drain diode providing a conduction path to a substrate of the switching transistor when a voltage between the second electrode and the substrate becomes negative by more than a threshold, to enable a voltage between the first and second electrodes to follow changes in the voltage on the first electrode.
ii. A method of operating a printer having a printhead (97) comprising a plurality of actuating elements (i, 2), and a driver circuit (100) for each of the actuating elements, the actuating elements each having at least a first electrode (40) for receiving a common diive signal, and a second electrode (50) for coupling to a return path for the common drive signal, the driver circuit having an input for a print signal, and having an n-channel switching transistor (32) having a drain coupled to the second electrode, and a source coupled to the return path, and operable according to the print signal, to couple the second electrode to the return path to drive the actuating element, the switching transistor being configured to have an open drain, and the switching transistor having a body diode providing a conduction path to a substrate of the switching transistor, the method having the steps of: providing the common drive signal as a positive voltage waveform with inverted pulses having an upgoing leading edge and a downgoing trailing edge and switching the switching transistor according to the print signal so that it is on during at least part of the leading edge so that a voltage across the actuating element follows at least part of the leading edge, using the body diode or similar functionality source to drain diode to conduct when the switching transistor is off if a voltage between the second electrode and the substrate becomes negative by more than a threshold to enable a voltage between the first and second electrodes to follow changes in the common drive signal on the first electrode.